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00052 #ifndef __CVMX_PKO_DEFS_H__
00053 #define __CVMX_PKO_DEFS_H__
00054
00055 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00056 #define CVMX_PKO_CHANNEL_LEVEL CVMX_PKO_CHANNEL_LEVEL_FUNC()
00057 static inline uint64_t CVMX_PKO_CHANNEL_LEVEL_FUNC(void)
00058 {
00059 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00060 cvmx_warn("CVMX_PKO_CHANNEL_LEVEL not supported on this chip\n");
00061 return CVMX_ADD_IO_SEG(0x00015400000800F0ull);
00062 }
00063 #else
00064 #define CVMX_PKO_CHANNEL_LEVEL (CVMX_ADD_IO_SEG(0x00015400000800F0ull))
00065 #endif
00066 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00067 #define CVMX_PKO_DPFI_ENA CVMX_PKO_DPFI_ENA_FUNC()
00068 static inline uint64_t CVMX_PKO_DPFI_ENA_FUNC(void)
00069 {
00070 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00071 cvmx_warn("CVMX_PKO_DPFI_ENA not supported on this chip\n");
00072 return CVMX_ADD_IO_SEG(0x0001540000C00018ull);
00073 }
00074 #else
00075 #define CVMX_PKO_DPFI_ENA (CVMX_ADD_IO_SEG(0x0001540000C00018ull))
00076 #endif
00077 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00078 #define CVMX_PKO_DPFI_FLUSH CVMX_PKO_DPFI_FLUSH_FUNC()
00079 static inline uint64_t CVMX_PKO_DPFI_FLUSH_FUNC(void)
00080 {
00081 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00082 cvmx_warn("CVMX_PKO_DPFI_FLUSH not supported on this chip\n");
00083 return CVMX_ADD_IO_SEG(0x0001540000C00008ull);
00084 }
00085 #else
00086 #define CVMX_PKO_DPFI_FLUSH (CVMX_ADD_IO_SEG(0x0001540000C00008ull))
00087 #endif
00088 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00089 #define CVMX_PKO_DPFI_FPA_AURA CVMX_PKO_DPFI_FPA_AURA_FUNC()
00090 static inline uint64_t CVMX_PKO_DPFI_FPA_AURA_FUNC(void)
00091 {
00092 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00093 cvmx_warn("CVMX_PKO_DPFI_FPA_AURA not supported on this chip\n");
00094 return CVMX_ADD_IO_SEG(0x0001540000C00010ull);
00095 }
00096 #else
00097 #define CVMX_PKO_DPFI_FPA_AURA (CVMX_ADD_IO_SEG(0x0001540000C00010ull))
00098 #endif
00099 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00100 #define CVMX_PKO_DPFI_STATUS CVMX_PKO_DPFI_STATUS_FUNC()
00101 static inline uint64_t CVMX_PKO_DPFI_STATUS_FUNC(void)
00102 {
00103 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00104 cvmx_warn("CVMX_PKO_DPFI_STATUS not supported on this chip\n");
00105 return CVMX_ADD_IO_SEG(0x0001540000C00000ull);
00106 }
00107 #else
00108 #define CVMX_PKO_DPFI_STATUS (CVMX_ADD_IO_SEG(0x0001540000C00000ull))
00109 #endif
00110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00111 static inline uint64_t CVMX_PKO_DQX_BYTES(unsigned long offset)
00112 {
00113 if (!(
00114 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00115 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00116 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00117 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00118 cvmx_warn("CVMX_PKO_DQX_BYTES(%lu) is invalid on this chip\n", offset);
00119 return CVMX_ADD_IO_SEG(0x00015400000000D8ull) + ((offset) & 1023) * 512;
00120 }
00121 #else
00122 #define CVMX_PKO_DQX_BYTES(offset) (CVMX_ADD_IO_SEG(0x00015400000000D8ull) + ((offset) & 1023) * 512)
00123 #endif
00124 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00125 static inline uint64_t CVMX_PKO_DQX_CIR(unsigned long offset)
00126 {
00127 if (!(
00128 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00129 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00130 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00131 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00132 cvmx_warn("CVMX_PKO_DQX_CIR(%lu) is invalid on this chip\n", offset);
00133 return CVMX_ADD_IO_SEG(0x0001540000280018ull) + ((offset) & 1023) * 512;
00134 }
00135 #else
00136 #define CVMX_PKO_DQX_CIR(offset) (CVMX_ADD_IO_SEG(0x0001540000280018ull) + ((offset) & 1023) * 512)
00137 #endif
00138 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00139 static inline uint64_t CVMX_PKO_DQX_DROPPED_BYTES(unsigned long offset)
00140 {
00141 if (!(
00142 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00143 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00144 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00145 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00146 cvmx_warn("CVMX_PKO_DQX_DROPPED_BYTES(%lu) is invalid on this chip\n", offset);
00147 return CVMX_ADD_IO_SEG(0x00015400000000C8ull) + ((offset) & 1023) * 512;
00148 }
00149 #else
00150 #define CVMX_PKO_DQX_DROPPED_BYTES(offset) (CVMX_ADD_IO_SEG(0x00015400000000C8ull) + ((offset) & 1023) * 512)
00151 #endif
00152 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00153 static inline uint64_t CVMX_PKO_DQX_DROPPED_PACKETS(unsigned long offset)
00154 {
00155 if (!(
00156 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00157 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00158 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00159 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00160 cvmx_warn("CVMX_PKO_DQX_DROPPED_PACKETS(%lu) is invalid on this chip\n", offset);
00161 return CVMX_ADD_IO_SEG(0x00015400000000C0ull) + ((offset) & 1023) * 512;
00162 }
00163 #else
00164 #define CVMX_PKO_DQX_DROPPED_PACKETS(offset) (CVMX_ADD_IO_SEG(0x00015400000000C0ull) + ((offset) & 1023) * 512)
00165 #endif
00166 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00167 static inline uint64_t CVMX_PKO_DQX_FIFO(unsigned long offset)
00168 {
00169 if (!(
00170 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00171 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00172 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00173 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00174 cvmx_warn("CVMX_PKO_DQX_FIFO(%lu) is invalid on this chip\n", offset);
00175 return CVMX_ADD_IO_SEG(0x0001540000300078ull) + ((offset) & 1023) * 512;
00176 }
00177 #else
00178 #define CVMX_PKO_DQX_FIFO(offset) (CVMX_ADD_IO_SEG(0x0001540000300078ull) + ((offset) & 1023) * 512)
00179 #endif
00180 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00181 static inline uint64_t CVMX_PKO_DQX_PACKETS(unsigned long offset)
00182 {
00183 if (!(
00184 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00185 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00186 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00187 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00188 cvmx_warn("CVMX_PKO_DQX_PACKETS(%lu) is invalid on this chip\n", offset);
00189 return CVMX_ADD_IO_SEG(0x00015400000000D0ull) + ((offset) & 1023) * 512;
00190 }
00191 #else
00192 #define CVMX_PKO_DQX_PACKETS(offset) (CVMX_ADD_IO_SEG(0x00015400000000D0ull) + ((offset) & 1023) * 512)
00193 #endif
00194 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00195 static inline uint64_t CVMX_PKO_DQX_PICK(unsigned long offset)
00196 {
00197 if (!(
00198 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00199 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00200 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00201 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00202 cvmx_warn("CVMX_PKO_DQX_PICK(%lu) is invalid on this chip\n", offset);
00203 return CVMX_ADD_IO_SEG(0x0001540000300070ull) + ((offset) & 1023) * 512;
00204 }
00205 #else
00206 #define CVMX_PKO_DQX_PICK(offset) (CVMX_ADD_IO_SEG(0x0001540000300070ull) + ((offset) & 1023) * 512)
00207 #endif
00208 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00209 static inline uint64_t CVMX_PKO_DQX_PIR(unsigned long offset)
00210 {
00211 if (!(
00212 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00213 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00214 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00215 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00216 cvmx_warn("CVMX_PKO_DQX_PIR(%lu) is invalid on this chip\n", offset);
00217 return CVMX_ADD_IO_SEG(0x0001540000280020ull) + ((offset) & 1023) * 512;
00218 }
00219 #else
00220 #define CVMX_PKO_DQX_PIR(offset) (CVMX_ADD_IO_SEG(0x0001540000280020ull) + ((offset) & 1023) * 512)
00221 #endif
00222 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00223 static inline uint64_t CVMX_PKO_DQX_POINTERS(unsigned long offset)
00224 {
00225 if (!(
00226 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00227 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00228 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00229 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00230 cvmx_warn("CVMX_PKO_DQX_POINTERS(%lu) is invalid on this chip\n", offset);
00231 return CVMX_ADD_IO_SEG(0x0001540000280078ull) + ((offset) & 1023) * 512;
00232 }
00233 #else
00234 #define CVMX_PKO_DQX_POINTERS(offset) (CVMX_ADD_IO_SEG(0x0001540000280078ull) + ((offset) & 1023) * 512)
00235 #endif
00236 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00237 static inline uint64_t CVMX_PKO_DQX_SCHEDULE(unsigned long offset)
00238 {
00239 if (!(
00240 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00241 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00242 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00243 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00244 cvmx_warn("CVMX_PKO_DQX_SCHEDULE(%lu) is invalid on this chip\n", offset);
00245 return CVMX_ADD_IO_SEG(0x0001540000280008ull) + ((offset) & 1023) * 512;
00246 }
00247 #else
00248 #define CVMX_PKO_DQX_SCHEDULE(offset) (CVMX_ADD_IO_SEG(0x0001540000280008ull) + ((offset) & 1023) * 512)
00249 #endif
00250 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00251 static inline uint64_t CVMX_PKO_DQX_SCHED_STATE(unsigned long offset)
00252 {
00253 if (!(
00254 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00255 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00256 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00257 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00258 cvmx_warn("CVMX_PKO_DQX_SCHED_STATE(%lu) is invalid on this chip\n", offset);
00259 return CVMX_ADD_IO_SEG(0x0001540000280028ull) + ((offset) & 1023) * 512;
00260 }
00261 #else
00262 #define CVMX_PKO_DQX_SCHED_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000280028ull) + ((offset) & 1023) * 512)
00263 #endif
00264 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00265 static inline uint64_t CVMX_PKO_DQX_SHAPE(unsigned long offset)
00266 {
00267 if (!(
00268 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00269 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00270 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00271 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00272 cvmx_warn("CVMX_PKO_DQX_SHAPE(%lu) is invalid on this chip\n", offset);
00273 return CVMX_ADD_IO_SEG(0x0001540000280010ull) + ((offset) & 1023) * 512;
00274 }
00275 #else
00276 #define CVMX_PKO_DQX_SHAPE(offset) (CVMX_ADD_IO_SEG(0x0001540000280010ull) + ((offset) & 1023) * 512)
00277 #endif
00278 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00279 static inline uint64_t CVMX_PKO_DQX_SHAPE_STATE(unsigned long offset)
00280 {
00281 if (!(
00282 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00283 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00284 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00285 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00286 cvmx_warn("CVMX_PKO_DQX_SHAPE_STATE(%lu) is invalid on this chip\n", offset);
00287 return CVMX_ADD_IO_SEG(0x0001540000280030ull) + ((offset) & 1023) * 512;
00288 }
00289 #else
00290 #define CVMX_PKO_DQX_SHAPE_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000280030ull) + ((offset) & 1023) * 512)
00291 #endif
00292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00293 static inline uint64_t CVMX_PKO_DQX_SW_XOFF(unsigned long offset)
00294 {
00295 if (!(
00296 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00297 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00298 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00299 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00300 cvmx_warn("CVMX_PKO_DQX_SW_XOFF(%lu) is invalid on this chip\n", offset);
00301 return CVMX_ADD_IO_SEG(0x00015400002800E0ull) + ((offset) & 1023) * 512;
00302 }
00303 #else
00304 #define CVMX_PKO_DQX_SW_XOFF(offset) (CVMX_ADD_IO_SEG(0x00015400002800E0ull) + ((offset) & 1023) * 512)
00305 #endif
00306 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00307 static inline uint64_t CVMX_PKO_DQX_TOPOLOGY(unsigned long offset)
00308 {
00309 if (!(
00310 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00311 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00312 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00313 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00314 cvmx_warn("CVMX_PKO_DQX_TOPOLOGY(%lu) is invalid on this chip\n", offset);
00315 return CVMX_ADD_IO_SEG(0x0001540000300000ull) + ((offset) & 1023) * 512;
00316 }
00317 #else
00318 #define CVMX_PKO_DQX_TOPOLOGY(offset) (CVMX_ADD_IO_SEG(0x0001540000300000ull) + ((offset) & 1023) * 512)
00319 #endif
00320 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00321 static inline uint64_t CVMX_PKO_DQX_WM_BUF_CNT(unsigned long offset)
00322 {
00323 if (!(
00324 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00325 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00326 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00327 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00328 cvmx_warn("CVMX_PKO_DQX_WM_BUF_CNT(%lu) is invalid on this chip\n", offset);
00329 return CVMX_ADD_IO_SEG(0x00015400008000E8ull) + ((offset) & 1023) * 512;
00330 }
00331 #else
00332 #define CVMX_PKO_DQX_WM_BUF_CNT(offset) (CVMX_ADD_IO_SEG(0x00015400008000E8ull) + ((offset) & 1023) * 512)
00333 #endif
00334 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00335 static inline uint64_t CVMX_PKO_DQX_WM_BUF_CTL(unsigned long offset)
00336 {
00337 if (!(
00338 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00339 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00340 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00341 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00342 cvmx_warn("CVMX_PKO_DQX_WM_BUF_CTL(%lu) is invalid on this chip\n", offset);
00343 return CVMX_ADD_IO_SEG(0x00015400008000F0ull) + ((offset) & 1023) * 512;
00344 }
00345 #else
00346 #define CVMX_PKO_DQX_WM_BUF_CTL(offset) (CVMX_ADD_IO_SEG(0x00015400008000F0ull) + ((offset) & 1023) * 512)
00347 #endif
00348 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00349 static inline uint64_t CVMX_PKO_DQX_WM_BUF_CTL_W1C(unsigned long offset)
00350 {
00351 if (!(
00352 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00353 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00354 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00355 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00356 cvmx_warn("CVMX_PKO_DQX_WM_BUF_CTL_W1C(%lu) is invalid on this chip\n", offset);
00357 return CVMX_ADD_IO_SEG(0x00015400008000F8ull) + ((offset) & 1023) * 512;
00358 }
00359 #else
00360 #define CVMX_PKO_DQX_WM_BUF_CTL_W1C(offset) (CVMX_ADD_IO_SEG(0x00015400008000F8ull) + ((offset) & 1023) * 512)
00361 #endif
00362 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00363 static inline uint64_t CVMX_PKO_DQX_WM_CNT(unsigned long offset)
00364 {
00365 if (!(
00366 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00367 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00368 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00369 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00370 cvmx_warn("CVMX_PKO_DQX_WM_CNT(%lu) is invalid on this chip\n", offset);
00371 return CVMX_ADD_IO_SEG(0x0001540000000050ull) + ((offset) & 1023) * 512;
00372 }
00373 #else
00374 #define CVMX_PKO_DQX_WM_CNT(offset) (CVMX_ADD_IO_SEG(0x0001540000000050ull) + ((offset) & 1023) * 512)
00375 #endif
00376 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00377 static inline uint64_t CVMX_PKO_DQX_WM_CTL(unsigned long offset)
00378 {
00379 if (!(
00380 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00381 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00382 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00383 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00384 cvmx_warn("CVMX_PKO_DQX_WM_CTL(%lu) is invalid on this chip\n", offset);
00385 return CVMX_ADD_IO_SEG(0x0001540000000040ull) + ((offset) & 1023) * 512;
00386 }
00387 #else
00388 #define CVMX_PKO_DQX_WM_CTL(offset) (CVMX_ADD_IO_SEG(0x0001540000000040ull) + ((offset) & 1023) * 512)
00389 #endif
00390 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00391 static inline uint64_t CVMX_PKO_DQX_WM_CTL_W1C(unsigned long offset)
00392 {
00393 if (!(
00394 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00395 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
00396 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
00397 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00398 cvmx_warn("CVMX_PKO_DQX_WM_CTL_W1C(%lu) is invalid on this chip\n", offset);
00399 return CVMX_ADD_IO_SEG(0x0001540000000048ull) + ((offset) & 1023) * 512;
00400 }
00401 #else
00402 #define CVMX_PKO_DQX_WM_CTL_W1C(offset) (CVMX_ADD_IO_SEG(0x0001540000000048ull) + ((offset) & 1023) * 512)
00403 #endif
00404 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00405 #define CVMX_PKO_DQ_CSR_BUS_DEBUG CVMX_PKO_DQ_CSR_BUS_DEBUG_FUNC()
00406 static inline uint64_t CVMX_PKO_DQ_CSR_BUS_DEBUG_FUNC(void)
00407 {
00408 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00409 cvmx_warn("CVMX_PKO_DQ_CSR_BUS_DEBUG not supported on this chip\n");
00410 return CVMX_ADD_IO_SEG(0x00015400003001F8ull);
00411 }
00412 #else
00413 #define CVMX_PKO_DQ_CSR_BUS_DEBUG (CVMX_ADD_IO_SEG(0x00015400003001F8ull))
00414 #endif
00415 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00416 #define CVMX_PKO_DQ_DEBUG CVMX_PKO_DQ_DEBUG_FUNC()
00417 static inline uint64_t CVMX_PKO_DQ_DEBUG_FUNC(void)
00418 {
00419 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00420 cvmx_warn("CVMX_PKO_DQ_DEBUG not supported on this chip\n");
00421 return CVMX_ADD_IO_SEG(0x0001540000300128ull);
00422 }
00423 #else
00424 #define CVMX_PKO_DQ_DEBUG (CVMX_ADD_IO_SEG(0x0001540000300128ull))
00425 #endif
00426 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00427 #define CVMX_PKO_DRAIN_IRQ CVMX_PKO_DRAIN_IRQ_FUNC()
00428 static inline uint64_t CVMX_PKO_DRAIN_IRQ_FUNC(void)
00429 {
00430 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00431 cvmx_warn("CVMX_PKO_DRAIN_IRQ not supported on this chip\n");
00432 return CVMX_ADD_IO_SEG(0x0001540000000140ull);
00433 }
00434 #else
00435 #define CVMX_PKO_DRAIN_IRQ (CVMX_ADD_IO_SEG(0x0001540000000140ull))
00436 #endif
00437 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00438 #define CVMX_PKO_ENABLE CVMX_PKO_ENABLE_FUNC()
00439 static inline uint64_t CVMX_PKO_ENABLE_FUNC(void)
00440 {
00441 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00442 cvmx_warn("CVMX_PKO_ENABLE not supported on this chip\n");
00443 return CVMX_ADD_IO_SEG(0x0001540000D00008ull);
00444 }
00445 #else
00446 #define CVMX_PKO_ENABLE (CVMX_ADD_IO_SEG(0x0001540000D00008ull))
00447 #endif
00448 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00449 static inline uint64_t CVMX_PKO_FORMATX_CTL(unsigned long offset)
00450 {
00451 if (!(
00452 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 31))) ||
00453 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 127))) ||
00454 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 127))) ||
00455 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 31)))))
00456 cvmx_warn("CVMX_PKO_FORMATX_CTL(%lu) is invalid on this chip\n", offset);
00457 return CVMX_ADD_IO_SEG(0x0001540000900800ull) + ((offset) & 127) * 8;
00458 }
00459 #else
00460 #define CVMX_PKO_FORMATX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001540000900800ull) + ((offset) & 127) * 8)
00461 #endif
00462 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00463 #define CVMX_PKO_L1_SQA_DEBUG CVMX_PKO_L1_SQA_DEBUG_FUNC()
00464 static inline uint64_t CVMX_PKO_L1_SQA_DEBUG_FUNC(void)
00465 {
00466 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00467 cvmx_warn("CVMX_PKO_L1_SQA_DEBUG not supported on this chip\n");
00468 return CVMX_ADD_IO_SEG(0x0001540000080128ull);
00469 }
00470 #else
00471 #define CVMX_PKO_L1_SQA_DEBUG (CVMX_ADD_IO_SEG(0x0001540000080128ull))
00472 #endif
00473 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00474 #define CVMX_PKO_L1_SQB_DEBUG CVMX_PKO_L1_SQB_DEBUG_FUNC()
00475 static inline uint64_t CVMX_PKO_L1_SQB_DEBUG_FUNC(void)
00476 {
00477 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00478 cvmx_warn("CVMX_PKO_L1_SQB_DEBUG not supported on this chip\n");
00479 return CVMX_ADD_IO_SEG(0x0001540000080130ull);
00480 }
00481 #else
00482 #define CVMX_PKO_L1_SQB_DEBUG (CVMX_ADD_IO_SEG(0x0001540000080130ull))
00483 #endif
00484 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00485 static inline uint64_t CVMX_PKO_L1_SQX_CIR(unsigned long offset)
00486 {
00487 if (!(
00488 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00489 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00490 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00491 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00492 cvmx_warn("CVMX_PKO_L1_SQX_CIR(%lu) is invalid on this chip\n", offset);
00493 return CVMX_ADD_IO_SEG(0x0001540000000018ull) + ((offset) & 31) * 512;
00494 }
00495 #else
00496 #define CVMX_PKO_L1_SQX_CIR(offset) (CVMX_ADD_IO_SEG(0x0001540000000018ull) + ((offset) & 31) * 512)
00497 #endif
00498 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00499 static inline uint64_t CVMX_PKO_L1_SQX_DROPPED_BYTES(unsigned long offset)
00500 {
00501 if (!(
00502 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00503 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00504 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00505 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00506 cvmx_warn("CVMX_PKO_L1_SQX_DROPPED_BYTES(%lu) is invalid on this chip\n", offset);
00507 return CVMX_ADD_IO_SEG(0x0001540000000088ull) + ((offset) & 31) * 512;
00508 }
00509 #else
00510 #define CVMX_PKO_L1_SQX_DROPPED_BYTES(offset) (CVMX_ADD_IO_SEG(0x0001540000000088ull) + ((offset) & 31) * 512)
00511 #endif
00512 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00513 static inline uint64_t CVMX_PKO_L1_SQX_DROPPED_PACKETS(unsigned long offset)
00514 {
00515 if (!(
00516 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00517 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00518 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00519 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00520 cvmx_warn("CVMX_PKO_L1_SQX_DROPPED_PACKETS(%lu) is invalid on this chip\n", offset);
00521 return CVMX_ADD_IO_SEG(0x0001540000000080ull) + ((offset) & 31) * 512;
00522 }
00523 #else
00524 #define CVMX_PKO_L1_SQX_DROPPED_PACKETS(offset) (CVMX_ADD_IO_SEG(0x0001540000000080ull) + ((offset) & 31) * 512)
00525 #endif
00526 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00527 static inline uint64_t CVMX_PKO_L1_SQX_GREEN(unsigned long offset)
00528 {
00529 if (!(
00530 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00531 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00532 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00533 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00534 cvmx_warn("CVMX_PKO_L1_SQX_GREEN(%lu) is invalid on this chip\n", offset);
00535 return CVMX_ADD_IO_SEG(0x0001540000080058ull) + ((offset) & 31) * 512;
00536 }
00537 #else
00538 #define CVMX_PKO_L1_SQX_GREEN(offset) (CVMX_ADD_IO_SEG(0x0001540000080058ull) + ((offset) & 31) * 512)
00539 #endif
00540 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00541 static inline uint64_t CVMX_PKO_L1_SQX_GREEN_BYTES(unsigned long offset)
00542 {
00543 if (!(
00544 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00545 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00546 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00547 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00548 cvmx_warn("CVMX_PKO_L1_SQX_GREEN_BYTES(%lu) is invalid on this chip\n", offset);
00549 return CVMX_ADD_IO_SEG(0x00015400000000B8ull) + ((offset) & 31) * 512;
00550 }
00551 #else
00552 #define CVMX_PKO_L1_SQX_GREEN_BYTES(offset) (CVMX_ADD_IO_SEG(0x00015400000000B8ull) + ((offset) & 31) * 512)
00553 #endif
00554 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00555 static inline uint64_t CVMX_PKO_L1_SQX_GREEN_PACKETS(unsigned long offset)
00556 {
00557 if (!(
00558 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00559 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00560 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00561 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00562 cvmx_warn("CVMX_PKO_L1_SQX_GREEN_PACKETS(%lu) is invalid on this chip\n", offset);
00563 return CVMX_ADD_IO_SEG(0x00015400000000B0ull) + ((offset) & 31) * 512;
00564 }
00565 #else
00566 #define CVMX_PKO_L1_SQX_GREEN_PACKETS(offset) (CVMX_ADD_IO_SEG(0x00015400000000B0ull) + ((offset) & 31) * 512)
00567 #endif
00568 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00569 static inline uint64_t CVMX_PKO_L1_SQX_LINK(unsigned long offset)
00570 {
00571 if (!(
00572 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00573 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00574 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00575 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00576 cvmx_warn("CVMX_PKO_L1_SQX_LINK(%lu) is invalid on this chip\n", offset);
00577 return CVMX_ADD_IO_SEG(0x0001540000000038ull) + ((offset) & 31) * 512;
00578 }
00579 #else
00580 #define CVMX_PKO_L1_SQX_LINK(offset) (CVMX_ADD_IO_SEG(0x0001540000000038ull) + ((offset) & 31) * 512)
00581 #endif
00582 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00583 static inline uint64_t CVMX_PKO_L1_SQX_PICK(unsigned long offset)
00584 {
00585 if (!(
00586 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00587 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00588 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00589 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00590 cvmx_warn("CVMX_PKO_L1_SQX_PICK(%lu) is invalid on this chip\n", offset);
00591 return CVMX_ADD_IO_SEG(0x0001540000080070ull) + ((offset) & 31) * 512;
00592 }
00593 #else
00594 #define CVMX_PKO_L1_SQX_PICK(offset) (CVMX_ADD_IO_SEG(0x0001540000080070ull) + ((offset) & 31) * 512)
00595 #endif
00596 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00597 static inline uint64_t CVMX_PKO_L1_SQX_RED(unsigned long offset)
00598 {
00599 if (!(
00600 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00601 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00602 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00603 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00604 cvmx_warn("CVMX_PKO_L1_SQX_RED(%lu) is invalid on this chip\n", offset);
00605 return CVMX_ADD_IO_SEG(0x0001540000080068ull) + ((offset) & 31) * 512;
00606 }
00607 #else
00608 #define CVMX_PKO_L1_SQX_RED(offset) (CVMX_ADD_IO_SEG(0x0001540000080068ull) + ((offset) & 31) * 512)
00609 #endif
00610 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00611 static inline uint64_t CVMX_PKO_L1_SQX_RED_BYTES(unsigned long offset)
00612 {
00613 if (!(
00614 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00615 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00616 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00617 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00618 cvmx_warn("CVMX_PKO_L1_SQX_RED_BYTES(%lu) is invalid on this chip\n", offset);
00619 return CVMX_ADD_IO_SEG(0x0001540000000098ull) + ((offset) & 31) * 512;
00620 }
00621 #else
00622 #define CVMX_PKO_L1_SQX_RED_BYTES(offset) (CVMX_ADD_IO_SEG(0x0001540000000098ull) + ((offset) & 31) * 512)
00623 #endif
00624 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00625 static inline uint64_t CVMX_PKO_L1_SQX_RED_PACKETS(unsigned long offset)
00626 {
00627 if (!(
00628 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00629 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00630 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00631 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00632 cvmx_warn("CVMX_PKO_L1_SQX_RED_PACKETS(%lu) is invalid on this chip\n", offset);
00633 return CVMX_ADD_IO_SEG(0x0001540000000090ull) + ((offset) & 31) * 512;
00634 }
00635 #else
00636 #define CVMX_PKO_L1_SQX_RED_PACKETS(offset) (CVMX_ADD_IO_SEG(0x0001540000000090ull) + ((offset) & 31) * 512)
00637 #endif
00638 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00639 static inline uint64_t CVMX_PKO_L1_SQX_SCHEDULE(unsigned long offset)
00640 {
00641 if (!(
00642 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00643 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00644 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00645 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00646 cvmx_warn("CVMX_PKO_L1_SQX_SCHEDULE(%lu) is invalid on this chip\n", offset);
00647 return CVMX_ADD_IO_SEG(0x0001540000000008ull) + ((offset) & 31) * 512;
00648 }
00649 #else
00650 #define CVMX_PKO_L1_SQX_SCHEDULE(offset) (CVMX_ADD_IO_SEG(0x0001540000000008ull) + ((offset) & 31) * 512)
00651 #endif
00652 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00653 static inline uint64_t CVMX_PKO_L1_SQX_SHAPE(unsigned long offset)
00654 {
00655 if (!(
00656 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00657 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00658 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00659 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00660 cvmx_warn("CVMX_PKO_L1_SQX_SHAPE(%lu) is invalid on this chip\n", offset);
00661 return CVMX_ADD_IO_SEG(0x0001540000000010ull) + ((offset) & 31) * 512;
00662 }
00663 #else
00664 #define CVMX_PKO_L1_SQX_SHAPE(offset) (CVMX_ADD_IO_SEG(0x0001540000000010ull) + ((offset) & 31) * 512)
00665 #endif
00666 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00667 static inline uint64_t CVMX_PKO_L1_SQX_SHAPE_STATE(unsigned long offset)
00668 {
00669 if (!(
00670 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00671 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00672 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00673 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00674 cvmx_warn("CVMX_PKO_L1_SQX_SHAPE_STATE(%lu) is invalid on this chip\n", offset);
00675 return CVMX_ADD_IO_SEG(0x0001540000000030ull) + ((offset) & 31) * 512;
00676 }
00677 #else
00678 #define CVMX_PKO_L1_SQX_SHAPE_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000000030ull) + ((offset) & 31) * 512)
00679 #endif
00680 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00681 static inline uint64_t CVMX_PKO_L1_SQX_SW_XOFF(unsigned long offset)
00682 {
00683 if (!(
00684 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00685 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00686 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00687 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00688 cvmx_warn("CVMX_PKO_L1_SQX_SW_XOFF(%lu) is invalid on this chip\n", offset);
00689 return CVMX_ADD_IO_SEG(0x00015400000000E0ull) + ((offset) & 31) * 512;
00690 }
00691 #else
00692 #define CVMX_PKO_L1_SQX_SW_XOFF(offset) (CVMX_ADD_IO_SEG(0x00015400000000E0ull) + ((offset) & 31) * 512)
00693 #endif
00694 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00695 static inline uint64_t CVMX_PKO_L1_SQX_TOPOLOGY(unsigned long offset)
00696 {
00697 if (!(
00698 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00699 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00700 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00701 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00702 cvmx_warn("CVMX_PKO_L1_SQX_TOPOLOGY(%lu) is invalid on this chip\n", offset);
00703 return CVMX_ADD_IO_SEG(0x0001540000080000ull) + ((offset) & 31) * 512;
00704 }
00705 #else
00706 #define CVMX_PKO_L1_SQX_TOPOLOGY(offset) (CVMX_ADD_IO_SEG(0x0001540000080000ull) + ((offset) & 31) * 512)
00707 #endif
00708 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00709 static inline uint64_t CVMX_PKO_L1_SQX_YELLOW(unsigned long offset)
00710 {
00711 if (!(
00712 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00713 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00714 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00715 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00716 cvmx_warn("CVMX_PKO_L1_SQX_YELLOW(%lu) is invalid on this chip\n", offset);
00717 return CVMX_ADD_IO_SEG(0x0001540000080060ull) + ((offset) & 31) * 512;
00718 }
00719 #else
00720 #define CVMX_PKO_L1_SQX_YELLOW(offset) (CVMX_ADD_IO_SEG(0x0001540000080060ull) + ((offset) & 31) * 512)
00721 #endif
00722 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00723 static inline uint64_t CVMX_PKO_L1_SQX_YELLOW_BYTES(unsigned long offset)
00724 {
00725 if (!(
00726 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00727 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00728 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00729 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00730 cvmx_warn("CVMX_PKO_L1_SQX_YELLOW_BYTES(%lu) is invalid on this chip\n", offset);
00731 return CVMX_ADD_IO_SEG(0x00015400000000A8ull) + ((offset) & 31) * 512;
00732 }
00733 #else
00734 #define CVMX_PKO_L1_SQX_YELLOW_BYTES(offset) (CVMX_ADD_IO_SEG(0x00015400000000A8ull) + ((offset) & 31) * 512)
00735 #endif
00736 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00737 static inline uint64_t CVMX_PKO_L1_SQX_YELLOW_PACKETS(unsigned long offset)
00738 {
00739 if (!(
00740 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
00741 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 31))) ||
00742 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 31))) ||
00743 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
00744 cvmx_warn("CVMX_PKO_L1_SQX_YELLOW_PACKETS(%lu) is invalid on this chip\n", offset);
00745 return CVMX_ADD_IO_SEG(0x00015400000000A0ull) + ((offset) & 31) * 512;
00746 }
00747 #else
00748 #define CVMX_PKO_L1_SQX_YELLOW_PACKETS(offset) (CVMX_ADD_IO_SEG(0x00015400000000A0ull) + ((offset) & 31) * 512)
00749 #endif
00750 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00751 #define CVMX_PKO_L1_SQ_CSR_BUS_DEBUG CVMX_PKO_L1_SQ_CSR_BUS_DEBUG_FUNC()
00752 static inline uint64_t CVMX_PKO_L1_SQ_CSR_BUS_DEBUG_FUNC(void)
00753 {
00754 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00755 cvmx_warn("CVMX_PKO_L1_SQ_CSR_BUS_DEBUG not supported on this chip\n");
00756 return CVMX_ADD_IO_SEG(0x00015400000801F8ull);
00757 }
00758 #else
00759 #define CVMX_PKO_L1_SQ_CSR_BUS_DEBUG (CVMX_ADD_IO_SEG(0x00015400000801F8ull))
00760 #endif
00761 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00762 #define CVMX_PKO_L2_SQA_DEBUG CVMX_PKO_L2_SQA_DEBUG_FUNC()
00763 static inline uint64_t CVMX_PKO_L2_SQA_DEBUG_FUNC(void)
00764 {
00765 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00766 cvmx_warn("CVMX_PKO_L2_SQA_DEBUG not supported on this chip\n");
00767 return CVMX_ADD_IO_SEG(0x0001540000100128ull);
00768 }
00769 #else
00770 #define CVMX_PKO_L2_SQA_DEBUG (CVMX_ADD_IO_SEG(0x0001540000100128ull))
00771 #endif
00772 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00773 #define CVMX_PKO_L2_SQB_DEBUG CVMX_PKO_L2_SQB_DEBUG_FUNC()
00774 static inline uint64_t CVMX_PKO_L2_SQB_DEBUG_FUNC(void)
00775 {
00776 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00777 cvmx_warn("CVMX_PKO_L2_SQB_DEBUG not supported on this chip\n");
00778 return CVMX_ADD_IO_SEG(0x0001540000100130ull);
00779 }
00780 #else
00781 #define CVMX_PKO_L2_SQB_DEBUG (CVMX_ADD_IO_SEG(0x0001540000100130ull))
00782 #endif
00783 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00784 static inline uint64_t CVMX_PKO_L2_SQX_CIR(unsigned long offset)
00785 {
00786 if (!(
00787 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00788 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00789 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00790 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00791 cvmx_warn("CVMX_PKO_L2_SQX_CIR(%lu) is invalid on this chip\n", offset);
00792 return CVMX_ADD_IO_SEG(0x0001540000080018ull) + ((offset) & 511) * 512;
00793 }
00794 #else
00795 #define CVMX_PKO_L2_SQX_CIR(offset) (CVMX_ADD_IO_SEG(0x0001540000080018ull) + ((offset) & 511) * 512)
00796 #endif
00797 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00798 static inline uint64_t CVMX_PKO_L2_SQX_GREEN(unsigned long offset)
00799 {
00800 if (!(
00801 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00802 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00803 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00804 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00805 cvmx_warn("CVMX_PKO_L2_SQX_GREEN(%lu) is invalid on this chip\n", offset);
00806 return CVMX_ADD_IO_SEG(0x0001540000100058ull) + ((offset) & 511) * 512;
00807 }
00808 #else
00809 #define CVMX_PKO_L2_SQX_GREEN(offset) (CVMX_ADD_IO_SEG(0x0001540000100058ull) + ((offset) & 511) * 512)
00810 #endif
00811 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00812 static inline uint64_t CVMX_PKO_L2_SQX_PICK(unsigned long offset)
00813 {
00814 if (!(
00815 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00816 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00817 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00818 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00819 cvmx_warn("CVMX_PKO_L2_SQX_PICK(%lu) is invalid on this chip\n", offset);
00820 return CVMX_ADD_IO_SEG(0x0001540000100070ull) + ((offset) & 511) * 512;
00821 }
00822 #else
00823 #define CVMX_PKO_L2_SQX_PICK(offset) (CVMX_ADD_IO_SEG(0x0001540000100070ull) + ((offset) & 511) * 512)
00824 #endif
00825 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00826 static inline uint64_t CVMX_PKO_L2_SQX_PIR(unsigned long offset)
00827 {
00828 if (!(
00829 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00830 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00831 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00832 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00833 cvmx_warn("CVMX_PKO_L2_SQX_PIR(%lu) is invalid on this chip\n", offset);
00834 return CVMX_ADD_IO_SEG(0x0001540000080020ull) + ((offset) & 511) * 512;
00835 }
00836 #else
00837 #define CVMX_PKO_L2_SQX_PIR(offset) (CVMX_ADD_IO_SEG(0x0001540000080020ull) + ((offset) & 511) * 512)
00838 #endif
00839 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00840 static inline uint64_t CVMX_PKO_L2_SQX_POINTERS(unsigned long offset)
00841 {
00842 if (!(
00843 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00844 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00845 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00846 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00847 cvmx_warn("CVMX_PKO_L2_SQX_POINTERS(%lu) is invalid on this chip\n", offset);
00848 return CVMX_ADD_IO_SEG(0x0001540000080078ull) + ((offset) & 511) * 512;
00849 }
00850 #else
00851 #define CVMX_PKO_L2_SQX_POINTERS(offset) (CVMX_ADD_IO_SEG(0x0001540000080078ull) + ((offset) & 511) * 512)
00852 #endif
00853 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00854 static inline uint64_t CVMX_PKO_L2_SQX_RED(unsigned long offset)
00855 {
00856 if (!(
00857 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00858 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00859 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00860 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00861 cvmx_warn("CVMX_PKO_L2_SQX_RED(%lu) is invalid on this chip\n", offset);
00862 return CVMX_ADD_IO_SEG(0x0001540000100068ull) + ((offset) & 511) * 512;
00863 }
00864 #else
00865 #define CVMX_PKO_L2_SQX_RED(offset) (CVMX_ADD_IO_SEG(0x0001540000100068ull) + ((offset) & 511) * 512)
00866 #endif
00867 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00868 static inline uint64_t CVMX_PKO_L2_SQX_SCHEDULE(unsigned long offset)
00869 {
00870 if (!(
00871 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00872 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00873 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00874 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00875 cvmx_warn("CVMX_PKO_L2_SQX_SCHEDULE(%lu) is invalid on this chip\n", offset);
00876 return CVMX_ADD_IO_SEG(0x0001540000080008ull) + ((offset) & 511) * 512;
00877 }
00878 #else
00879 #define CVMX_PKO_L2_SQX_SCHEDULE(offset) (CVMX_ADD_IO_SEG(0x0001540000080008ull) + ((offset) & 511) * 512)
00880 #endif
00881 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00882 static inline uint64_t CVMX_PKO_L2_SQX_SCHED_STATE(unsigned long offset)
00883 {
00884 if (!(
00885 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00886 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00887 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00888 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00889 cvmx_warn("CVMX_PKO_L2_SQX_SCHED_STATE(%lu) is invalid on this chip\n", offset);
00890 return CVMX_ADD_IO_SEG(0x0001540000080028ull) + ((offset) & 511) * 512;
00891 }
00892 #else
00893 #define CVMX_PKO_L2_SQX_SCHED_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000080028ull) + ((offset) & 511) * 512)
00894 #endif
00895 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00896 static inline uint64_t CVMX_PKO_L2_SQX_SHAPE(unsigned long offset)
00897 {
00898 if (!(
00899 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00900 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00901 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00902 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00903 cvmx_warn("CVMX_PKO_L2_SQX_SHAPE(%lu) is invalid on this chip\n", offset);
00904 return CVMX_ADD_IO_SEG(0x0001540000080010ull) + ((offset) & 511) * 512;
00905 }
00906 #else
00907 #define CVMX_PKO_L2_SQX_SHAPE(offset) (CVMX_ADD_IO_SEG(0x0001540000080010ull) + ((offset) & 511) * 512)
00908 #endif
00909 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00910 static inline uint64_t CVMX_PKO_L2_SQX_SHAPE_STATE(unsigned long offset)
00911 {
00912 if (!(
00913 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00914 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00915 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00916 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00917 cvmx_warn("CVMX_PKO_L2_SQX_SHAPE_STATE(%lu) is invalid on this chip\n", offset);
00918 return CVMX_ADD_IO_SEG(0x0001540000080030ull) + ((offset) & 511) * 512;
00919 }
00920 #else
00921 #define CVMX_PKO_L2_SQX_SHAPE_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000080030ull) + ((offset) & 511) * 512)
00922 #endif
00923 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00924 static inline uint64_t CVMX_PKO_L2_SQX_SW_XOFF(unsigned long offset)
00925 {
00926 if (!(
00927 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00928 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00929 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00930 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00931 cvmx_warn("CVMX_PKO_L2_SQX_SW_XOFF(%lu) is invalid on this chip\n", offset);
00932 return CVMX_ADD_IO_SEG(0x00015400000800E0ull) + ((offset) & 511) * 512;
00933 }
00934 #else
00935 #define CVMX_PKO_L2_SQX_SW_XOFF(offset) (CVMX_ADD_IO_SEG(0x00015400000800E0ull) + ((offset) & 511) * 512)
00936 #endif
00937 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00938 static inline uint64_t CVMX_PKO_L2_SQX_TOPOLOGY(unsigned long offset)
00939 {
00940 if (!(
00941 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00942 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00943 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00944 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00945 cvmx_warn("CVMX_PKO_L2_SQX_TOPOLOGY(%lu) is invalid on this chip\n", offset);
00946 return CVMX_ADD_IO_SEG(0x0001540000100000ull) + ((offset) & 511) * 512;
00947 }
00948 #else
00949 #define CVMX_PKO_L2_SQX_TOPOLOGY(offset) (CVMX_ADD_IO_SEG(0x0001540000100000ull) + ((offset) & 511) * 512)
00950 #endif
00951 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00952 static inline uint64_t CVMX_PKO_L2_SQX_YELLOW(unsigned long offset)
00953 {
00954 if (!(
00955 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00956 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00957 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00958 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00959 cvmx_warn("CVMX_PKO_L2_SQX_YELLOW(%lu) is invalid on this chip\n", offset);
00960 return CVMX_ADD_IO_SEG(0x0001540000100060ull) + ((offset) & 511) * 512;
00961 }
00962 #else
00963 #define CVMX_PKO_L2_SQX_YELLOW(offset) (CVMX_ADD_IO_SEG(0x0001540000100060ull) + ((offset) & 511) * 512)
00964 #endif
00965 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00966 #define CVMX_PKO_L2_SQ_CSR_BUS_DEBUG CVMX_PKO_L2_SQ_CSR_BUS_DEBUG_FUNC()
00967 static inline uint64_t CVMX_PKO_L2_SQ_CSR_BUS_DEBUG_FUNC(void)
00968 {
00969 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00970 cvmx_warn("CVMX_PKO_L2_SQ_CSR_BUS_DEBUG not supported on this chip\n");
00971 return CVMX_ADD_IO_SEG(0x00015400001001F8ull);
00972 }
00973 #else
00974 #define CVMX_PKO_L2_SQ_CSR_BUS_DEBUG (CVMX_ADD_IO_SEG(0x00015400001001F8ull))
00975 #endif
00976 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00977 static inline uint64_t CVMX_PKO_L3_L2_SQX_CHANNEL(unsigned long offset)
00978 {
00979 if (!(
00980 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
00981 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
00982 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
00983 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
00984 cvmx_warn("CVMX_PKO_L3_L2_SQX_CHANNEL(%lu) is invalid on this chip\n", offset);
00985 return CVMX_ADD_IO_SEG(0x0001540000080038ull) + ((offset) & 511) * 512;
00986 }
00987 #else
00988 #define CVMX_PKO_L3_L2_SQX_CHANNEL(offset) (CVMX_ADD_IO_SEG(0x0001540000080038ull) + ((offset) & 511) * 512)
00989 #endif
00990 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
00991 #define CVMX_PKO_L3_SQA_DEBUG CVMX_PKO_L3_SQA_DEBUG_FUNC()
00992 static inline uint64_t CVMX_PKO_L3_SQA_DEBUG_FUNC(void)
00993 {
00994 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
00995 cvmx_warn("CVMX_PKO_L3_SQA_DEBUG not supported on this chip\n");
00996 return CVMX_ADD_IO_SEG(0x0001540000180128ull);
00997 }
00998 #else
00999 #define CVMX_PKO_L3_SQA_DEBUG (CVMX_ADD_IO_SEG(0x0001540000180128ull))
01000 #endif
01001 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01002 #define CVMX_PKO_L3_SQB_DEBUG CVMX_PKO_L3_SQB_DEBUG_FUNC()
01003 static inline uint64_t CVMX_PKO_L3_SQB_DEBUG_FUNC(void)
01004 {
01005 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01006 cvmx_warn("CVMX_PKO_L3_SQB_DEBUG not supported on this chip\n");
01007 return CVMX_ADD_IO_SEG(0x0001540000180130ull);
01008 }
01009 #else
01010 #define CVMX_PKO_L3_SQB_DEBUG (CVMX_ADD_IO_SEG(0x0001540000180130ull))
01011 #endif
01012 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01013 static inline uint64_t CVMX_PKO_L3_SQX_CIR(unsigned long offset)
01014 {
01015 if (!(
01016 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01017 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01018 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01019 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01020 cvmx_warn("CVMX_PKO_L3_SQX_CIR(%lu) is invalid on this chip\n", offset);
01021 return CVMX_ADD_IO_SEG(0x0001540000100018ull) + ((offset) & 511) * 512;
01022 }
01023 #else
01024 #define CVMX_PKO_L3_SQX_CIR(offset) (CVMX_ADD_IO_SEG(0x0001540000100018ull) + ((offset) & 511) * 512)
01025 #endif
01026 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01027 static inline uint64_t CVMX_PKO_L3_SQX_GREEN(unsigned long offset)
01028 {
01029 if (!(
01030 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01031 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01032 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01033 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01034 cvmx_warn("CVMX_PKO_L3_SQX_GREEN(%lu) is invalid on this chip\n", offset);
01035 return CVMX_ADD_IO_SEG(0x0001540000180058ull) + ((offset) & 511) * 512;
01036 }
01037 #else
01038 #define CVMX_PKO_L3_SQX_GREEN(offset) (CVMX_ADD_IO_SEG(0x0001540000180058ull) + ((offset) & 511) * 512)
01039 #endif
01040 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01041 static inline uint64_t CVMX_PKO_L3_SQX_PICK(unsigned long offset)
01042 {
01043 if (!(
01044 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01045 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01046 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01047 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01048 cvmx_warn("CVMX_PKO_L3_SQX_PICK(%lu) is invalid on this chip\n", offset);
01049 return CVMX_ADD_IO_SEG(0x0001540000180070ull) + ((offset) & 511) * 512;
01050 }
01051 #else
01052 #define CVMX_PKO_L3_SQX_PICK(offset) (CVMX_ADD_IO_SEG(0x0001540000180070ull) + ((offset) & 511) * 512)
01053 #endif
01054 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01055 static inline uint64_t CVMX_PKO_L3_SQX_PIR(unsigned long offset)
01056 {
01057 if (!(
01058 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01059 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01060 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01061 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01062 cvmx_warn("CVMX_PKO_L3_SQX_PIR(%lu) is invalid on this chip\n", offset);
01063 return CVMX_ADD_IO_SEG(0x0001540000100020ull) + ((offset) & 511) * 512;
01064 }
01065 #else
01066 #define CVMX_PKO_L3_SQX_PIR(offset) (CVMX_ADD_IO_SEG(0x0001540000100020ull) + ((offset) & 511) * 512)
01067 #endif
01068 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01069 static inline uint64_t CVMX_PKO_L3_SQX_POINTERS(unsigned long offset)
01070 {
01071 if (!(
01072 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01073 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01074 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01075 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01076 cvmx_warn("CVMX_PKO_L3_SQX_POINTERS(%lu) is invalid on this chip\n", offset);
01077 return CVMX_ADD_IO_SEG(0x0001540000100078ull) + ((offset) & 511) * 512;
01078 }
01079 #else
01080 #define CVMX_PKO_L3_SQX_POINTERS(offset) (CVMX_ADD_IO_SEG(0x0001540000100078ull) + ((offset) & 511) * 512)
01081 #endif
01082 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01083 static inline uint64_t CVMX_PKO_L3_SQX_RED(unsigned long offset)
01084 {
01085 if (!(
01086 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01087 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01088 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01089 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01090 cvmx_warn("CVMX_PKO_L3_SQX_RED(%lu) is invalid on this chip\n", offset);
01091 return CVMX_ADD_IO_SEG(0x0001540000180068ull) + ((offset) & 511) * 512;
01092 }
01093 #else
01094 #define CVMX_PKO_L3_SQX_RED(offset) (CVMX_ADD_IO_SEG(0x0001540000180068ull) + ((offset) & 511) * 512)
01095 #endif
01096 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01097 static inline uint64_t CVMX_PKO_L3_SQX_SCHEDULE(unsigned long offset)
01098 {
01099 if (!(
01100 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01101 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01102 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01103 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01104 cvmx_warn("CVMX_PKO_L3_SQX_SCHEDULE(%lu) is invalid on this chip\n", offset);
01105 return CVMX_ADD_IO_SEG(0x0001540000100008ull) + ((offset) & 511) * 512;
01106 }
01107 #else
01108 #define CVMX_PKO_L3_SQX_SCHEDULE(offset) (CVMX_ADD_IO_SEG(0x0001540000100008ull) + ((offset) & 511) * 512)
01109 #endif
01110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01111 static inline uint64_t CVMX_PKO_L3_SQX_SCHED_STATE(unsigned long offset)
01112 {
01113 if (!(
01114 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01115 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01116 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01117 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01118 cvmx_warn("CVMX_PKO_L3_SQX_SCHED_STATE(%lu) is invalid on this chip\n", offset);
01119 return CVMX_ADD_IO_SEG(0x0001540000100028ull) + ((offset) & 511) * 512;
01120 }
01121 #else
01122 #define CVMX_PKO_L3_SQX_SCHED_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000100028ull) + ((offset) & 511) * 512)
01123 #endif
01124 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01125 static inline uint64_t CVMX_PKO_L3_SQX_SHAPE(unsigned long offset)
01126 {
01127 if (!(
01128 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01129 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01130 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01131 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01132 cvmx_warn("CVMX_PKO_L3_SQX_SHAPE(%lu) is invalid on this chip\n", offset);
01133 return CVMX_ADD_IO_SEG(0x0001540000100010ull) + ((offset) & 511) * 512;
01134 }
01135 #else
01136 #define CVMX_PKO_L3_SQX_SHAPE(offset) (CVMX_ADD_IO_SEG(0x0001540000100010ull) + ((offset) & 511) * 512)
01137 #endif
01138 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01139 static inline uint64_t CVMX_PKO_L3_SQX_SHAPE_STATE(unsigned long offset)
01140 {
01141 if (!(
01142 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01143 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01144 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01145 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01146 cvmx_warn("CVMX_PKO_L3_SQX_SHAPE_STATE(%lu) is invalid on this chip\n", offset);
01147 return CVMX_ADD_IO_SEG(0x0001540000100030ull) + ((offset) & 511) * 512;
01148 }
01149 #else
01150 #define CVMX_PKO_L3_SQX_SHAPE_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000100030ull) + ((offset) & 511) * 512)
01151 #endif
01152 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01153 static inline uint64_t CVMX_PKO_L3_SQX_SW_XOFF(unsigned long offset)
01154 {
01155 if (!(
01156 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01157 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01158 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01159 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01160 cvmx_warn("CVMX_PKO_L3_SQX_SW_XOFF(%lu) is invalid on this chip\n", offset);
01161 return CVMX_ADD_IO_SEG(0x00015400001000E0ull) + ((offset) & 511) * 512;
01162 }
01163 #else
01164 #define CVMX_PKO_L3_SQX_SW_XOFF(offset) (CVMX_ADD_IO_SEG(0x00015400001000E0ull) + ((offset) & 511) * 512)
01165 #endif
01166 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01167 static inline uint64_t CVMX_PKO_L3_SQX_TOPOLOGY(unsigned long offset)
01168 {
01169 if (!(
01170 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01171 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01172 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01173 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01174 cvmx_warn("CVMX_PKO_L3_SQX_TOPOLOGY(%lu) is invalid on this chip\n", offset);
01175 return CVMX_ADD_IO_SEG(0x0001540000180000ull) + ((offset) & 511) * 512;
01176 }
01177 #else
01178 #define CVMX_PKO_L3_SQX_TOPOLOGY(offset) (CVMX_ADD_IO_SEG(0x0001540000180000ull) + ((offset) & 511) * 512)
01179 #endif
01180 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01181 static inline uint64_t CVMX_PKO_L3_SQX_YELLOW(unsigned long offset)
01182 {
01183 if (!(
01184 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
01185 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01186 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511))) ||
01187 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
01188 cvmx_warn("CVMX_PKO_L3_SQX_YELLOW(%lu) is invalid on this chip\n", offset);
01189 return CVMX_ADD_IO_SEG(0x0001540000180060ull) + ((offset) & 511) * 512;
01190 }
01191 #else
01192 #define CVMX_PKO_L3_SQX_YELLOW(offset) (CVMX_ADD_IO_SEG(0x0001540000180060ull) + ((offset) & 511) * 512)
01193 #endif
01194 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01195 #define CVMX_PKO_L3_SQ_CSR_BUS_DEBUG CVMX_PKO_L3_SQ_CSR_BUS_DEBUG_FUNC()
01196 static inline uint64_t CVMX_PKO_L3_SQ_CSR_BUS_DEBUG_FUNC(void)
01197 {
01198 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01199 cvmx_warn("CVMX_PKO_L3_SQ_CSR_BUS_DEBUG not supported on this chip\n");
01200 return CVMX_ADD_IO_SEG(0x00015400001801F8ull);
01201 }
01202 #else
01203 #define CVMX_PKO_L3_SQ_CSR_BUS_DEBUG (CVMX_ADD_IO_SEG(0x00015400001801F8ull))
01204 #endif
01205 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01206 #define CVMX_PKO_L4_SQA_DEBUG CVMX_PKO_L4_SQA_DEBUG_FUNC()
01207 static inline uint64_t CVMX_PKO_L4_SQA_DEBUG_FUNC(void)
01208 {
01209 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
01210 cvmx_warn("CVMX_PKO_L4_SQA_DEBUG not supported on this chip\n");
01211 return CVMX_ADD_IO_SEG(0x0001540000200128ull);
01212 }
01213 #else
01214 #define CVMX_PKO_L4_SQA_DEBUG (CVMX_ADD_IO_SEG(0x0001540000200128ull))
01215 #endif
01216 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01217 #define CVMX_PKO_L4_SQB_DEBUG CVMX_PKO_L4_SQB_DEBUG_FUNC()
01218 static inline uint64_t CVMX_PKO_L4_SQB_DEBUG_FUNC(void)
01219 {
01220 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
01221 cvmx_warn("CVMX_PKO_L4_SQB_DEBUG not supported on this chip\n");
01222 return CVMX_ADD_IO_SEG(0x0001540000200130ull);
01223 }
01224 #else
01225 #define CVMX_PKO_L4_SQB_DEBUG (CVMX_ADD_IO_SEG(0x0001540000200130ull))
01226 #endif
01227 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01228 static inline uint64_t CVMX_PKO_L4_SQX_CIR(unsigned long offset)
01229 {
01230 if (!(
01231 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01232 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01233 cvmx_warn("CVMX_PKO_L4_SQX_CIR(%lu) is invalid on this chip\n", offset);
01234 return CVMX_ADD_IO_SEG(0x0001540000180018ull) + ((offset) & 1023) * 512;
01235 }
01236 #else
01237 #define CVMX_PKO_L4_SQX_CIR(offset) (CVMX_ADD_IO_SEG(0x0001540000180018ull) + ((offset) & 1023) * 512)
01238 #endif
01239 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01240 static inline uint64_t CVMX_PKO_L4_SQX_GREEN(unsigned long offset)
01241 {
01242 if (!(
01243 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01244 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01245 cvmx_warn("CVMX_PKO_L4_SQX_GREEN(%lu) is invalid on this chip\n", offset);
01246 return CVMX_ADD_IO_SEG(0x0001540000200058ull) + ((offset) & 1023) * 512;
01247 }
01248 #else
01249 #define CVMX_PKO_L4_SQX_GREEN(offset) (CVMX_ADD_IO_SEG(0x0001540000200058ull) + ((offset) & 1023) * 512)
01250 #endif
01251 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01252 static inline uint64_t CVMX_PKO_L4_SQX_PICK(unsigned long offset)
01253 {
01254 if (!(
01255 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01256 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01257 cvmx_warn("CVMX_PKO_L4_SQX_PICK(%lu) is invalid on this chip\n", offset);
01258 return CVMX_ADD_IO_SEG(0x0001540000200070ull) + ((offset) & 1023) * 512;
01259 }
01260 #else
01261 #define CVMX_PKO_L4_SQX_PICK(offset) (CVMX_ADD_IO_SEG(0x0001540000200070ull) + ((offset) & 1023) * 512)
01262 #endif
01263 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01264 static inline uint64_t CVMX_PKO_L4_SQX_PIR(unsigned long offset)
01265 {
01266 if (!(
01267 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01268 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01269 cvmx_warn("CVMX_PKO_L4_SQX_PIR(%lu) is invalid on this chip\n", offset);
01270 return CVMX_ADD_IO_SEG(0x0001540000180020ull) + ((offset) & 1023) * 512;
01271 }
01272 #else
01273 #define CVMX_PKO_L4_SQX_PIR(offset) (CVMX_ADD_IO_SEG(0x0001540000180020ull) + ((offset) & 1023) * 512)
01274 #endif
01275 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01276 static inline uint64_t CVMX_PKO_L4_SQX_POINTERS(unsigned long offset)
01277 {
01278 if (!(
01279 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01280 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01281 cvmx_warn("CVMX_PKO_L4_SQX_POINTERS(%lu) is invalid on this chip\n", offset);
01282 return CVMX_ADD_IO_SEG(0x0001540000180078ull) + ((offset) & 1023) * 512;
01283 }
01284 #else
01285 #define CVMX_PKO_L4_SQX_POINTERS(offset) (CVMX_ADD_IO_SEG(0x0001540000180078ull) + ((offset) & 1023) * 512)
01286 #endif
01287 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01288 static inline uint64_t CVMX_PKO_L4_SQX_RED(unsigned long offset)
01289 {
01290 if (!(
01291 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01292 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01293 cvmx_warn("CVMX_PKO_L4_SQX_RED(%lu) is invalid on this chip\n", offset);
01294 return CVMX_ADD_IO_SEG(0x0001540000200068ull) + ((offset) & 1023) * 512;
01295 }
01296 #else
01297 #define CVMX_PKO_L4_SQX_RED(offset) (CVMX_ADD_IO_SEG(0x0001540000200068ull) + ((offset) & 1023) * 512)
01298 #endif
01299 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01300 static inline uint64_t CVMX_PKO_L4_SQX_SCHEDULE(unsigned long offset)
01301 {
01302 if (!(
01303 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01304 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01305 cvmx_warn("CVMX_PKO_L4_SQX_SCHEDULE(%lu) is invalid on this chip\n", offset);
01306 return CVMX_ADD_IO_SEG(0x0001540000180008ull) + ((offset) & 1023) * 512;
01307 }
01308 #else
01309 #define CVMX_PKO_L4_SQX_SCHEDULE(offset) (CVMX_ADD_IO_SEG(0x0001540000180008ull) + ((offset) & 1023) * 512)
01310 #endif
01311 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01312 static inline uint64_t CVMX_PKO_L4_SQX_SCHED_STATE(unsigned long offset)
01313 {
01314 if (!(
01315 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 511))) ||
01316 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 511)))))
01317 cvmx_warn("CVMX_PKO_L4_SQX_SCHED_STATE(%lu) is invalid on this chip\n", offset);
01318 return CVMX_ADD_IO_SEG(0x0001540000180028ull) + ((offset) & 511) * 512;
01319 }
01320 #else
01321 #define CVMX_PKO_L4_SQX_SCHED_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000180028ull) + ((offset) & 511) * 512)
01322 #endif
01323 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01324 static inline uint64_t CVMX_PKO_L4_SQX_SHAPE(unsigned long offset)
01325 {
01326 if (!(
01327 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01328 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01329 cvmx_warn("CVMX_PKO_L4_SQX_SHAPE(%lu) is invalid on this chip\n", offset);
01330 return CVMX_ADD_IO_SEG(0x0001540000180010ull) + ((offset) & 1023) * 512;
01331 }
01332 #else
01333 #define CVMX_PKO_L4_SQX_SHAPE(offset) (CVMX_ADD_IO_SEG(0x0001540000180010ull) + ((offset) & 1023) * 512)
01334 #endif
01335 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01336 static inline uint64_t CVMX_PKO_L4_SQX_SHAPE_STATE(unsigned long offset)
01337 {
01338 if (!(
01339 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01340 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01341 cvmx_warn("CVMX_PKO_L4_SQX_SHAPE_STATE(%lu) is invalid on this chip\n", offset);
01342 return CVMX_ADD_IO_SEG(0x0001540000180030ull) + ((offset) & 1023) * 512;
01343 }
01344 #else
01345 #define CVMX_PKO_L4_SQX_SHAPE_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000180030ull) + ((offset) & 1023) * 512)
01346 #endif
01347 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01348 static inline uint64_t CVMX_PKO_L4_SQX_SW_XOFF(unsigned long offset)
01349 {
01350 if (!(
01351 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01352 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01353 cvmx_warn("CVMX_PKO_L4_SQX_SW_XOFF(%lu) is invalid on this chip\n", offset);
01354 return CVMX_ADD_IO_SEG(0x00015400001800E0ull) + ((offset) & 1023) * 512;
01355 }
01356 #else
01357 #define CVMX_PKO_L4_SQX_SW_XOFF(offset) (CVMX_ADD_IO_SEG(0x00015400001800E0ull) + ((offset) & 1023) * 512)
01358 #endif
01359 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01360 static inline uint64_t CVMX_PKO_L4_SQX_TOPOLOGY(unsigned long offset)
01361 {
01362 if (!(
01363 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01364 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01365 cvmx_warn("CVMX_PKO_L4_SQX_TOPOLOGY(%lu) is invalid on this chip\n", offset);
01366 return CVMX_ADD_IO_SEG(0x0001540000200000ull) + ((offset) & 1023) * 512;
01367 }
01368 #else
01369 #define CVMX_PKO_L4_SQX_TOPOLOGY(offset) (CVMX_ADD_IO_SEG(0x0001540000200000ull) + ((offset) & 1023) * 512)
01370 #endif
01371 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01372 static inline uint64_t CVMX_PKO_L4_SQX_YELLOW(unsigned long offset)
01373 {
01374 if (!(
01375 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01376 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01377 cvmx_warn("CVMX_PKO_L4_SQX_YELLOW(%lu) is invalid on this chip\n", offset);
01378 return CVMX_ADD_IO_SEG(0x0001540000200060ull) + ((offset) & 1023) * 512;
01379 }
01380 #else
01381 #define CVMX_PKO_L4_SQX_YELLOW(offset) (CVMX_ADD_IO_SEG(0x0001540000200060ull) + ((offset) & 1023) * 512)
01382 #endif
01383 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01384 #define CVMX_PKO_L4_SQ_CSR_BUS_DEBUG CVMX_PKO_L4_SQ_CSR_BUS_DEBUG_FUNC()
01385 static inline uint64_t CVMX_PKO_L4_SQ_CSR_BUS_DEBUG_FUNC(void)
01386 {
01387 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
01388 cvmx_warn("CVMX_PKO_L4_SQ_CSR_BUS_DEBUG not supported on this chip\n");
01389 return CVMX_ADD_IO_SEG(0x00015400002001F8ull);
01390 }
01391 #else
01392 #define CVMX_PKO_L4_SQ_CSR_BUS_DEBUG (CVMX_ADD_IO_SEG(0x00015400002001F8ull))
01393 #endif
01394 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01395 #define CVMX_PKO_L5_SQA_DEBUG CVMX_PKO_L5_SQA_DEBUG_FUNC()
01396 static inline uint64_t CVMX_PKO_L5_SQA_DEBUG_FUNC(void)
01397 {
01398 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
01399 cvmx_warn("CVMX_PKO_L5_SQA_DEBUG not supported on this chip\n");
01400 return CVMX_ADD_IO_SEG(0x0001540000280128ull);
01401 }
01402 #else
01403 #define CVMX_PKO_L5_SQA_DEBUG (CVMX_ADD_IO_SEG(0x0001540000280128ull))
01404 #endif
01405 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01406 #define CVMX_PKO_L5_SQB_DEBUG CVMX_PKO_L5_SQB_DEBUG_FUNC()
01407 static inline uint64_t CVMX_PKO_L5_SQB_DEBUG_FUNC(void)
01408 {
01409 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
01410 cvmx_warn("CVMX_PKO_L5_SQB_DEBUG not supported on this chip\n");
01411 return CVMX_ADD_IO_SEG(0x0001540000280130ull);
01412 }
01413 #else
01414 #define CVMX_PKO_L5_SQB_DEBUG (CVMX_ADD_IO_SEG(0x0001540000280130ull))
01415 #endif
01416 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01417 static inline uint64_t CVMX_PKO_L5_SQX_CIR(unsigned long offset)
01418 {
01419 if (!(
01420 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01421 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01422 cvmx_warn("CVMX_PKO_L5_SQX_CIR(%lu) is invalid on this chip\n", offset);
01423 return CVMX_ADD_IO_SEG(0x0001540000200018ull) + ((offset) & 1023) * 512;
01424 }
01425 #else
01426 #define CVMX_PKO_L5_SQX_CIR(offset) (CVMX_ADD_IO_SEG(0x0001540000200018ull) + ((offset) & 1023) * 512)
01427 #endif
01428 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01429 static inline uint64_t CVMX_PKO_L5_SQX_GREEN(unsigned long offset)
01430 {
01431 if (!(
01432 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01433 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01434 cvmx_warn("CVMX_PKO_L5_SQX_GREEN(%lu) is invalid on this chip\n", offset);
01435 return CVMX_ADD_IO_SEG(0x0001540000280058ull) + ((offset) & 1023) * 512;
01436 }
01437 #else
01438 #define CVMX_PKO_L5_SQX_GREEN(offset) (CVMX_ADD_IO_SEG(0x0001540000280058ull) + ((offset) & 1023) * 512)
01439 #endif
01440 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01441 static inline uint64_t CVMX_PKO_L5_SQX_PICK(unsigned long offset)
01442 {
01443 if (!(
01444 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01445 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01446 cvmx_warn("CVMX_PKO_L5_SQX_PICK(%lu) is invalid on this chip\n", offset);
01447 return CVMX_ADD_IO_SEG(0x0001540000280070ull) + ((offset) & 1023) * 512;
01448 }
01449 #else
01450 #define CVMX_PKO_L5_SQX_PICK(offset) (CVMX_ADD_IO_SEG(0x0001540000280070ull) + ((offset) & 1023) * 512)
01451 #endif
01452 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01453 static inline uint64_t CVMX_PKO_L5_SQX_PIR(unsigned long offset)
01454 {
01455 if (!(
01456 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01457 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01458 cvmx_warn("CVMX_PKO_L5_SQX_PIR(%lu) is invalid on this chip\n", offset);
01459 return CVMX_ADD_IO_SEG(0x0001540000200020ull) + ((offset) & 1023) * 512;
01460 }
01461 #else
01462 #define CVMX_PKO_L5_SQX_PIR(offset) (CVMX_ADD_IO_SEG(0x0001540000200020ull) + ((offset) & 1023) * 512)
01463 #endif
01464 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01465 static inline uint64_t CVMX_PKO_L5_SQX_POINTERS(unsigned long offset)
01466 {
01467 if (!(
01468 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01469 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01470 cvmx_warn("CVMX_PKO_L5_SQX_POINTERS(%lu) is invalid on this chip\n", offset);
01471 return CVMX_ADD_IO_SEG(0x0001540000200078ull) + ((offset) & 1023) * 512;
01472 }
01473 #else
01474 #define CVMX_PKO_L5_SQX_POINTERS(offset) (CVMX_ADD_IO_SEG(0x0001540000200078ull) + ((offset) & 1023) * 512)
01475 #endif
01476 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01477 static inline uint64_t CVMX_PKO_L5_SQX_RED(unsigned long offset)
01478 {
01479 if (!(
01480 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01481 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01482 cvmx_warn("CVMX_PKO_L5_SQX_RED(%lu) is invalid on this chip\n", offset);
01483 return CVMX_ADD_IO_SEG(0x0001540000280068ull) + ((offset) & 1023) * 512;
01484 }
01485 #else
01486 #define CVMX_PKO_L5_SQX_RED(offset) (CVMX_ADD_IO_SEG(0x0001540000280068ull) + ((offset) & 1023) * 512)
01487 #endif
01488 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01489 static inline uint64_t CVMX_PKO_L5_SQX_SCHEDULE(unsigned long offset)
01490 {
01491 if (!(
01492 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01493 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01494 cvmx_warn("CVMX_PKO_L5_SQX_SCHEDULE(%lu) is invalid on this chip\n", offset);
01495 return CVMX_ADD_IO_SEG(0x0001540000200008ull) + ((offset) & 1023) * 512;
01496 }
01497 #else
01498 #define CVMX_PKO_L5_SQX_SCHEDULE(offset) (CVMX_ADD_IO_SEG(0x0001540000200008ull) + ((offset) & 1023) * 512)
01499 #endif
01500 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01501 static inline uint64_t CVMX_PKO_L5_SQX_SCHED_STATE(unsigned long offset)
01502 {
01503 if (!(
01504 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01505 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01506 cvmx_warn("CVMX_PKO_L5_SQX_SCHED_STATE(%lu) is invalid on this chip\n", offset);
01507 return CVMX_ADD_IO_SEG(0x0001540000200028ull) + ((offset) & 1023) * 512;
01508 }
01509 #else
01510 #define CVMX_PKO_L5_SQX_SCHED_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000200028ull) + ((offset) & 1023) * 512)
01511 #endif
01512 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01513 static inline uint64_t CVMX_PKO_L5_SQX_SHAPE(unsigned long offset)
01514 {
01515 if (!(
01516 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01517 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01518 cvmx_warn("CVMX_PKO_L5_SQX_SHAPE(%lu) is invalid on this chip\n", offset);
01519 return CVMX_ADD_IO_SEG(0x0001540000200010ull) + ((offset) & 1023) * 512;
01520 }
01521 #else
01522 #define CVMX_PKO_L5_SQX_SHAPE(offset) (CVMX_ADD_IO_SEG(0x0001540000200010ull) + ((offset) & 1023) * 512)
01523 #endif
01524 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01525 static inline uint64_t CVMX_PKO_L5_SQX_SHAPE_STATE(unsigned long offset)
01526 {
01527 if (!(
01528 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01529 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01530 cvmx_warn("CVMX_PKO_L5_SQX_SHAPE_STATE(%lu) is invalid on this chip\n", offset);
01531 return CVMX_ADD_IO_SEG(0x0001540000200030ull) + ((offset) & 1023) * 512;
01532 }
01533 #else
01534 #define CVMX_PKO_L5_SQX_SHAPE_STATE(offset) (CVMX_ADD_IO_SEG(0x0001540000200030ull) + ((offset) & 1023) * 512)
01535 #endif
01536 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01537 static inline uint64_t CVMX_PKO_L5_SQX_SW_XOFF(unsigned long offset)
01538 {
01539 if (!(
01540 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01541 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01542 cvmx_warn("CVMX_PKO_L5_SQX_SW_XOFF(%lu) is invalid on this chip\n", offset);
01543 return CVMX_ADD_IO_SEG(0x00015400002000E0ull) + ((offset) & 1023) * 512;
01544 }
01545 #else
01546 #define CVMX_PKO_L5_SQX_SW_XOFF(offset) (CVMX_ADD_IO_SEG(0x00015400002000E0ull) + ((offset) & 1023) * 512)
01547 #endif
01548 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01549 static inline uint64_t CVMX_PKO_L5_SQX_TOPOLOGY(unsigned long offset)
01550 {
01551 if (!(
01552 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01553 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01554 cvmx_warn("CVMX_PKO_L5_SQX_TOPOLOGY(%lu) is invalid on this chip\n", offset);
01555 return CVMX_ADD_IO_SEG(0x0001540000280000ull) + ((offset) & 1023) * 512;
01556 }
01557 #else
01558 #define CVMX_PKO_L5_SQX_TOPOLOGY(offset) (CVMX_ADD_IO_SEG(0x0001540000280000ull) + ((offset) & 1023) * 512)
01559 #endif
01560 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01561 static inline uint64_t CVMX_PKO_L5_SQX_YELLOW(unsigned long offset)
01562 {
01563 if (!(
01564 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01565 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023)))))
01566 cvmx_warn("CVMX_PKO_L5_SQX_YELLOW(%lu) is invalid on this chip\n", offset);
01567 return CVMX_ADD_IO_SEG(0x0001540000280060ull) + ((offset) & 1023) * 512;
01568 }
01569 #else
01570 #define CVMX_PKO_L5_SQX_YELLOW(offset) (CVMX_ADD_IO_SEG(0x0001540000280060ull) + ((offset) & 1023) * 512)
01571 #endif
01572 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01573 #define CVMX_PKO_L5_SQ_CSR_BUS_DEBUG CVMX_PKO_L5_SQ_CSR_BUS_DEBUG_FUNC()
01574 static inline uint64_t CVMX_PKO_L5_SQ_CSR_BUS_DEBUG_FUNC(void)
01575 {
01576 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
01577 cvmx_warn("CVMX_PKO_L5_SQ_CSR_BUS_DEBUG not supported on this chip\n");
01578 return CVMX_ADD_IO_SEG(0x00015400002801F8ull);
01579 }
01580 #else
01581 #define CVMX_PKO_L5_SQ_CSR_BUS_DEBUG (CVMX_ADD_IO_SEG(0x00015400002801F8ull))
01582 #endif
01583 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01584 static inline uint64_t CVMX_PKO_LUTX(unsigned long offset)
01585 {
01586 if (!(
01587 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 383))) ||
01588 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
01589 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
01590 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 191)))))
01591 cvmx_warn("CVMX_PKO_LUTX(%lu) is invalid on this chip\n", offset);
01592 return CVMX_ADD_IO_SEG(0x0001540000B00000ull) + ((offset) & 1023) * 8;
01593 }
01594 #else
01595 #define CVMX_PKO_LUTX(offset) (CVMX_ADD_IO_SEG(0x0001540000B00000ull) + ((offset) & 1023) * 8)
01596 #endif
01597 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01598 #define CVMX_PKO_LUT_BIST_STATUS CVMX_PKO_LUT_BIST_STATUS_FUNC()
01599 static inline uint64_t CVMX_PKO_LUT_BIST_STATUS_FUNC(void)
01600 {
01601 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01602 cvmx_warn("CVMX_PKO_LUT_BIST_STATUS not supported on this chip\n");
01603 return CVMX_ADD_IO_SEG(0x0001540000B02018ull);
01604 }
01605 #else
01606 #define CVMX_PKO_LUT_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000B02018ull))
01607 #endif
01608 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01609 #define CVMX_PKO_LUT_ECC_CTL0 CVMX_PKO_LUT_ECC_CTL0_FUNC()
01610 static inline uint64_t CVMX_PKO_LUT_ECC_CTL0_FUNC(void)
01611 {
01612 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01613 cvmx_warn("CVMX_PKO_LUT_ECC_CTL0 not supported on this chip\n");
01614 return CVMX_ADD_IO_SEG(0x0001540000BFFFD0ull);
01615 }
01616 #else
01617 #define CVMX_PKO_LUT_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000BFFFD0ull))
01618 #endif
01619 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01620 #define CVMX_PKO_LUT_ECC_DBE_STS0 CVMX_PKO_LUT_ECC_DBE_STS0_FUNC()
01621 static inline uint64_t CVMX_PKO_LUT_ECC_DBE_STS0_FUNC(void)
01622 {
01623 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01624 cvmx_warn("CVMX_PKO_LUT_ECC_DBE_STS0 not supported on this chip\n");
01625 return CVMX_ADD_IO_SEG(0x0001540000BFFFF0ull);
01626 }
01627 #else
01628 #define CVMX_PKO_LUT_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000BFFFF0ull))
01629 #endif
01630 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01631 #define CVMX_PKO_LUT_ECC_DBE_STS_CMB0 CVMX_PKO_LUT_ECC_DBE_STS_CMB0_FUNC()
01632 static inline uint64_t CVMX_PKO_LUT_ECC_DBE_STS_CMB0_FUNC(void)
01633 {
01634 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01635 cvmx_warn("CVMX_PKO_LUT_ECC_DBE_STS_CMB0 not supported on this chip\n");
01636 return CVMX_ADD_IO_SEG(0x0001540000BFFFD8ull);
01637 }
01638 #else
01639 #define CVMX_PKO_LUT_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000BFFFD8ull))
01640 #endif
01641 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01642 #define CVMX_PKO_LUT_ECC_SBE_STS0 CVMX_PKO_LUT_ECC_SBE_STS0_FUNC()
01643 static inline uint64_t CVMX_PKO_LUT_ECC_SBE_STS0_FUNC(void)
01644 {
01645 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01646 cvmx_warn("CVMX_PKO_LUT_ECC_SBE_STS0 not supported on this chip\n");
01647 return CVMX_ADD_IO_SEG(0x0001540000BFFFF8ull);
01648 }
01649 #else
01650 #define CVMX_PKO_LUT_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000BFFFF8ull))
01651 #endif
01652 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01653 #define CVMX_PKO_LUT_ECC_SBE_STS_CMB0 CVMX_PKO_LUT_ECC_SBE_STS_CMB0_FUNC()
01654 static inline uint64_t CVMX_PKO_LUT_ECC_SBE_STS_CMB0_FUNC(void)
01655 {
01656 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01657 cvmx_warn("CVMX_PKO_LUT_ECC_SBE_STS_CMB0 not supported on this chip\n");
01658 return CVMX_ADD_IO_SEG(0x0001540000BFFFE8ull);
01659 }
01660 #else
01661 #define CVMX_PKO_LUT_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000BFFFE8ull))
01662 #endif
01663 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01664 static inline uint64_t CVMX_PKO_MACX_CFG(unsigned long offset)
01665 {
01666 if (!(
01667 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 13))) ||
01668 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 27))) ||
01669 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 27))) ||
01670 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 9)))))
01671 cvmx_warn("CVMX_PKO_MACX_CFG(%lu) is invalid on this chip\n", offset);
01672 return CVMX_ADD_IO_SEG(0x0001540000900000ull) + ((offset) & 31) * 8;
01673 }
01674 #else
01675 #define CVMX_PKO_MACX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001540000900000ull) + ((offset) & 31) * 8)
01676 #endif
01677 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01678 static inline uint64_t CVMX_PKO_MCI0_CRED_CNTX(unsigned long offset)
01679 {
01680 if (!(
01681 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 27))) ||
01682 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 27)))))
01683 cvmx_warn("CVMX_PKO_MCI0_CRED_CNTX(%lu) is invalid on this chip\n", offset);
01684 return CVMX_ADD_IO_SEG(0x0001540000A40000ull) + ((offset) & 31) * 8;
01685 }
01686 #else
01687 #define CVMX_PKO_MCI0_CRED_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001540000A40000ull) + ((offset) & 31) * 8)
01688 #endif
01689 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01690 static inline uint64_t CVMX_PKO_MCI0_MAX_CREDX(unsigned long offset)
01691 {
01692 if (!(
01693 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 27))) ||
01694 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 27)))))
01695 cvmx_warn("CVMX_PKO_MCI0_MAX_CREDX(%lu) is invalid on this chip\n", offset);
01696 return CVMX_ADD_IO_SEG(0x0001540000A00000ull) + ((offset) & 31) * 8;
01697 }
01698 #else
01699 #define CVMX_PKO_MCI0_MAX_CREDX(offset) (CVMX_ADD_IO_SEG(0x0001540000A00000ull) + ((offset) & 31) * 8)
01700 #endif
01701 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01702 static inline uint64_t CVMX_PKO_MCI1_CRED_CNTX(unsigned long offset)
01703 {
01704 if (!(
01705 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 13))) ||
01706 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 27))) ||
01707 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 27))) ||
01708 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 9)))))
01709 cvmx_warn("CVMX_PKO_MCI1_CRED_CNTX(%lu) is invalid on this chip\n", offset);
01710 return CVMX_ADD_IO_SEG(0x0001540000A80100ull) + ((offset) & 31) * 8;
01711 }
01712 #else
01713 #define CVMX_PKO_MCI1_CRED_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001540000A80100ull) + ((offset) & 31) * 8)
01714 #endif
01715 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01716 static inline uint64_t CVMX_PKO_MCI1_MAX_CREDX(unsigned long offset)
01717 {
01718 if (!(
01719 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 13))) ||
01720 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 27))) ||
01721 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 27))) ||
01722 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 9)))))
01723 cvmx_warn("CVMX_PKO_MCI1_MAX_CREDX(%lu) is invalid on this chip\n", offset);
01724 return CVMX_ADD_IO_SEG(0x0001540000A80000ull) + ((offset) & 31) * 8;
01725 }
01726 #else
01727 #define CVMX_PKO_MCI1_MAX_CREDX(offset) (CVMX_ADD_IO_SEG(0x0001540000A80000ull) + ((offset) & 31) * 8)
01728 #endif
01729 #define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
01730 #define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
01731 #define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
01732 #define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
01733 #define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
01734 #define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
01735 #define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
01736 #define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
01737 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01738 #define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
01739 static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
01740 {
01741 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
01742 cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
01743 return CVMX_ADD_IO_SEG(0x0001180050001170ull);
01744 }
01745 #else
01746 #define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
01747 #endif
01748 #define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
01749 #define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
01750 #define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
01751 #define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
01752 #define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
01753 #define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
01754 #define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
01755 #define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
01756 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01757 #define CVMX_PKO_MEM_IPORT_PTRS CVMX_PKO_MEM_IPORT_PTRS_FUNC()
01758 static inline uint64_t CVMX_PKO_MEM_IPORT_PTRS_FUNC(void)
01759 {
01760 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
01761 cvmx_warn("CVMX_PKO_MEM_IPORT_PTRS not supported on this chip\n");
01762 return CVMX_ADD_IO_SEG(0x0001180050001030ull);
01763 }
01764 #else
01765 #define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull))
01766 #endif
01767 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01768 #define CVMX_PKO_MEM_IPORT_QOS CVMX_PKO_MEM_IPORT_QOS_FUNC()
01769 static inline uint64_t CVMX_PKO_MEM_IPORT_QOS_FUNC(void)
01770 {
01771 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
01772 cvmx_warn("CVMX_PKO_MEM_IPORT_QOS not supported on this chip\n");
01773 return CVMX_ADD_IO_SEG(0x0001180050001038ull);
01774 }
01775 #else
01776 #define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull))
01777 #endif
01778 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01779 #define CVMX_PKO_MEM_IQUEUE_PTRS CVMX_PKO_MEM_IQUEUE_PTRS_FUNC()
01780 static inline uint64_t CVMX_PKO_MEM_IQUEUE_PTRS_FUNC(void)
01781 {
01782 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
01783 cvmx_warn("CVMX_PKO_MEM_IQUEUE_PTRS not supported on this chip\n");
01784 return CVMX_ADD_IO_SEG(0x0001180050001040ull);
01785 }
01786 #else
01787 #define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull))
01788 #endif
01789 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01790 #define CVMX_PKO_MEM_IQUEUE_QOS CVMX_PKO_MEM_IQUEUE_QOS_FUNC()
01791 static inline uint64_t CVMX_PKO_MEM_IQUEUE_QOS_FUNC(void)
01792 {
01793 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
01794 cvmx_warn("CVMX_PKO_MEM_IQUEUE_QOS not supported on this chip\n");
01795 return CVMX_ADD_IO_SEG(0x0001180050001048ull);
01796 }
01797 #else
01798 #define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull))
01799 #endif
01800 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01801 #define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
01802 static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
01803 {
01804 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
01805 cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
01806 return CVMX_ADD_IO_SEG(0x0001180050001010ull);
01807 }
01808 #else
01809 #define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
01810 #endif
01811 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01812 #define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
01813 static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
01814 {
01815 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
01816 cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
01817 return CVMX_ADD_IO_SEG(0x0001180050001018ull);
01818 }
01819 #else
01820 #define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
01821 #endif
01822 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01823 #define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
01824 static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
01825 {
01826 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
01827 cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
01828 return CVMX_ADD_IO_SEG(0x0001180050001020ull);
01829 }
01830 #else
01831 #define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
01832 #endif
01833 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01834 #define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
01835 static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
01836 {
01837 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
01838 cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
01839 return CVMX_ADD_IO_SEG(0x0001180050001028ull);
01840 }
01841 #else
01842 #define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
01843 #endif
01844 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01845 #define CVMX_PKO_MEM_QUEUE_PTRS CVMX_PKO_MEM_QUEUE_PTRS_FUNC()
01846 static inline uint64_t CVMX_PKO_MEM_QUEUE_PTRS_FUNC(void)
01847 {
01848 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
01849 cvmx_warn("CVMX_PKO_MEM_QUEUE_PTRS not supported on this chip\n");
01850 return CVMX_ADD_IO_SEG(0x0001180050001000ull);
01851 }
01852 #else
01853 #define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
01854 #endif
01855 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01856 #define CVMX_PKO_MEM_QUEUE_QOS CVMX_PKO_MEM_QUEUE_QOS_FUNC()
01857 static inline uint64_t CVMX_PKO_MEM_QUEUE_QOS_FUNC(void)
01858 {
01859 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
01860 cvmx_warn("CVMX_PKO_MEM_QUEUE_QOS not supported on this chip\n");
01861 return CVMX_ADD_IO_SEG(0x0001180050001008ull);
01862 }
01863 #else
01864 #define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
01865 #endif
01866 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01867 #define CVMX_PKO_MEM_THROTTLE_INT CVMX_PKO_MEM_THROTTLE_INT_FUNC()
01868 static inline uint64_t CVMX_PKO_MEM_THROTTLE_INT_FUNC(void)
01869 {
01870 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
01871 cvmx_warn("CVMX_PKO_MEM_THROTTLE_INT not supported on this chip\n");
01872 return CVMX_ADD_IO_SEG(0x0001180050001058ull);
01873 }
01874 #else
01875 #define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull))
01876 #endif
01877 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01878 #define CVMX_PKO_MEM_THROTTLE_PIPE CVMX_PKO_MEM_THROTTLE_PIPE_FUNC()
01879 static inline uint64_t CVMX_PKO_MEM_THROTTLE_PIPE_FUNC(void)
01880 {
01881 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
01882 cvmx_warn("CVMX_PKO_MEM_THROTTLE_PIPE not supported on this chip\n");
01883 return CVMX_ADD_IO_SEG(0x0001180050001050ull);
01884 }
01885 #else
01886 #define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull))
01887 #endif
01888 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01889 #define CVMX_PKO_NCB_BIST_STATUS CVMX_PKO_NCB_BIST_STATUS_FUNC()
01890 static inline uint64_t CVMX_PKO_NCB_BIST_STATUS_FUNC(void)
01891 {
01892 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01893 cvmx_warn("CVMX_PKO_NCB_BIST_STATUS not supported on this chip\n");
01894 return CVMX_ADD_IO_SEG(0x0001540000EFFF00ull);
01895 }
01896 #else
01897 #define CVMX_PKO_NCB_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000EFFF00ull))
01898 #endif
01899 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01900 #define CVMX_PKO_NCB_ECC_CTL0 CVMX_PKO_NCB_ECC_CTL0_FUNC()
01901 static inline uint64_t CVMX_PKO_NCB_ECC_CTL0_FUNC(void)
01902 {
01903 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01904 cvmx_warn("CVMX_PKO_NCB_ECC_CTL0 not supported on this chip\n");
01905 return CVMX_ADD_IO_SEG(0x0001540000EFFFD0ull);
01906 }
01907 #else
01908 #define CVMX_PKO_NCB_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000EFFFD0ull))
01909 #endif
01910 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01911 #define CVMX_PKO_NCB_ECC_DBE_STS0 CVMX_PKO_NCB_ECC_DBE_STS0_FUNC()
01912 static inline uint64_t CVMX_PKO_NCB_ECC_DBE_STS0_FUNC(void)
01913 {
01914 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01915 cvmx_warn("CVMX_PKO_NCB_ECC_DBE_STS0 not supported on this chip\n");
01916 return CVMX_ADD_IO_SEG(0x0001540000EFFFF0ull);
01917 }
01918 #else
01919 #define CVMX_PKO_NCB_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000EFFFF0ull))
01920 #endif
01921 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01922 #define CVMX_PKO_NCB_ECC_DBE_STS_CMB0 CVMX_PKO_NCB_ECC_DBE_STS_CMB0_FUNC()
01923 static inline uint64_t CVMX_PKO_NCB_ECC_DBE_STS_CMB0_FUNC(void)
01924 {
01925 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01926 cvmx_warn("CVMX_PKO_NCB_ECC_DBE_STS_CMB0 not supported on this chip\n");
01927 return CVMX_ADD_IO_SEG(0x0001540000EFFFD8ull);
01928 }
01929 #else
01930 #define CVMX_PKO_NCB_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000EFFFD8ull))
01931 #endif
01932 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01933 #define CVMX_PKO_NCB_ECC_SBE_STS0 CVMX_PKO_NCB_ECC_SBE_STS0_FUNC()
01934 static inline uint64_t CVMX_PKO_NCB_ECC_SBE_STS0_FUNC(void)
01935 {
01936 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01937 cvmx_warn("CVMX_PKO_NCB_ECC_SBE_STS0 not supported on this chip\n");
01938 return CVMX_ADD_IO_SEG(0x0001540000EFFFF8ull);
01939 }
01940 #else
01941 #define CVMX_PKO_NCB_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000EFFFF8ull))
01942 #endif
01943 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01944 #define CVMX_PKO_NCB_ECC_SBE_STS_CMB0 CVMX_PKO_NCB_ECC_SBE_STS_CMB0_FUNC()
01945 static inline uint64_t CVMX_PKO_NCB_ECC_SBE_STS_CMB0_FUNC(void)
01946 {
01947 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01948 cvmx_warn("CVMX_PKO_NCB_ECC_SBE_STS_CMB0 not supported on this chip\n");
01949 return CVMX_ADD_IO_SEG(0x0001540000EFFFE8ull);
01950 }
01951 #else
01952 #define CVMX_PKO_NCB_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000EFFFE8ull))
01953 #endif
01954 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01955 #define CVMX_PKO_NCB_INT CVMX_PKO_NCB_INT_FUNC()
01956 static inline uint64_t CVMX_PKO_NCB_INT_FUNC(void)
01957 {
01958 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01959 cvmx_warn("CVMX_PKO_NCB_INT not supported on this chip\n");
01960 return CVMX_ADD_IO_SEG(0x0001540000E00010ull);
01961 }
01962 #else
01963 #define CVMX_PKO_NCB_INT (CVMX_ADD_IO_SEG(0x0001540000E00010ull))
01964 #endif
01965 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01966 #define CVMX_PKO_NCB_TX_ERR_INFO CVMX_PKO_NCB_TX_ERR_INFO_FUNC()
01967 static inline uint64_t CVMX_PKO_NCB_TX_ERR_INFO_FUNC(void)
01968 {
01969 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01970 cvmx_warn("CVMX_PKO_NCB_TX_ERR_INFO not supported on this chip\n");
01971 return CVMX_ADD_IO_SEG(0x0001540000E00008ull);
01972 }
01973 #else
01974 #define CVMX_PKO_NCB_TX_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000E00008ull))
01975 #endif
01976 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01977 #define CVMX_PKO_NCB_TX_ERR_WORD CVMX_PKO_NCB_TX_ERR_WORD_FUNC()
01978 static inline uint64_t CVMX_PKO_NCB_TX_ERR_WORD_FUNC(void)
01979 {
01980 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01981 cvmx_warn("CVMX_PKO_NCB_TX_ERR_WORD not supported on this chip\n");
01982 return CVMX_ADD_IO_SEG(0x0001540000E00000ull);
01983 }
01984 #else
01985 #define CVMX_PKO_NCB_TX_ERR_WORD (CVMX_ADD_IO_SEG(0x0001540000E00000ull))
01986 #endif
01987 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01988 #define CVMX_PKO_PDM_BIST_STATUS CVMX_PKO_PDM_BIST_STATUS_FUNC()
01989 static inline uint64_t CVMX_PKO_PDM_BIST_STATUS_FUNC(void)
01990 {
01991 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
01992 cvmx_warn("CVMX_PKO_PDM_BIST_STATUS not supported on this chip\n");
01993 return CVMX_ADD_IO_SEG(0x00015400008FFF00ull);
01994 }
01995 #else
01996 #define CVMX_PKO_PDM_BIST_STATUS (CVMX_ADD_IO_SEG(0x00015400008FFF00ull))
01997 #endif
01998 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
01999 #define CVMX_PKO_PDM_CFG CVMX_PKO_PDM_CFG_FUNC()
02000 static inline uint64_t CVMX_PKO_PDM_CFG_FUNC(void)
02001 {
02002 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02003 cvmx_warn("CVMX_PKO_PDM_CFG not supported on this chip\n");
02004 return CVMX_ADD_IO_SEG(0x0001540000800000ull);
02005 }
02006 #else
02007 #define CVMX_PKO_PDM_CFG (CVMX_ADD_IO_SEG(0x0001540000800000ull))
02008 #endif
02009 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02010 #define CVMX_PKO_PDM_CFG_DBG CVMX_PKO_PDM_CFG_DBG_FUNC()
02011 static inline uint64_t CVMX_PKO_PDM_CFG_DBG_FUNC(void)
02012 {
02013 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02014 cvmx_warn("CVMX_PKO_PDM_CFG_DBG not supported on this chip\n");
02015 return CVMX_ADD_IO_SEG(0x0001540000800FF8ull);
02016 }
02017 #else
02018 #define CVMX_PKO_PDM_CFG_DBG (CVMX_ADD_IO_SEG(0x0001540000800FF8ull))
02019 #endif
02020 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02021 #define CVMX_PKO_PDM_CP_DBG CVMX_PKO_PDM_CP_DBG_FUNC()
02022 static inline uint64_t CVMX_PKO_PDM_CP_DBG_FUNC(void)
02023 {
02024 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02025 cvmx_warn("CVMX_PKO_PDM_CP_DBG not supported on this chip\n");
02026 return CVMX_ADD_IO_SEG(0x0001540000800190ull);
02027 }
02028 #else
02029 #define CVMX_PKO_PDM_CP_DBG (CVMX_ADD_IO_SEG(0x0001540000800190ull))
02030 #endif
02031 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02032 static inline uint64_t CVMX_PKO_PDM_DQX_MINPAD(unsigned long offset)
02033 {
02034 if (!(
02035 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 255))) ||
02036 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 1023))) ||
02037 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 1023))) ||
02038 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 255)))))
02039 cvmx_warn("CVMX_PKO_PDM_DQX_MINPAD(%lu) is invalid on this chip\n", offset);
02040 return CVMX_ADD_IO_SEG(0x00015400008F0000ull) + ((offset) & 1023) * 8;
02041 }
02042 #else
02043 #define CVMX_PKO_PDM_DQX_MINPAD(offset) (CVMX_ADD_IO_SEG(0x00015400008F0000ull) + ((offset) & 1023) * 8)
02044 #endif
02045 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02046 #define CVMX_PKO_PDM_DRPBUF_DBG CVMX_PKO_PDM_DRPBUF_DBG_FUNC()
02047 static inline uint64_t CVMX_PKO_PDM_DRPBUF_DBG_FUNC(void)
02048 {
02049 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02050 cvmx_warn("CVMX_PKO_PDM_DRPBUF_DBG not supported on this chip\n");
02051 return CVMX_ADD_IO_SEG(0x00015400008000B0ull);
02052 }
02053 #else
02054 #define CVMX_PKO_PDM_DRPBUF_DBG (CVMX_ADD_IO_SEG(0x00015400008000B0ull))
02055 #endif
02056 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02057 #define CVMX_PKO_PDM_DWPBUF_DBG CVMX_PKO_PDM_DWPBUF_DBG_FUNC()
02058 static inline uint64_t CVMX_PKO_PDM_DWPBUF_DBG_FUNC(void)
02059 {
02060 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02061 cvmx_warn("CVMX_PKO_PDM_DWPBUF_DBG not supported on this chip\n");
02062 return CVMX_ADD_IO_SEG(0x00015400008000A8ull);
02063 }
02064 #else
02065 #define CVMX_PKO_PDM_DWPBUF_DBG (CVMX_ADD_IO_SEG(0x00015400008000A8ull))
02066 #endif
02067 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02068 #define CVMX_PKO_PDM_ECC_CTL0 CVMX_PKO_PDM_ECC_CTL0_FUNC()
02069 static inline uint64_t CVMX_PKO_PDM_ECC_CTL0_FUNC(void)
02070 {
02071 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02072 cvmx_warn("CVMX_PKO_PDM_ECC_CTL0 not supported on this chip\n");
02073 return CVMX_ADD_IO_SEG(0x00015400008FFFD0ull);
02074 }
02075 #else
02076 #define CVMX_PKO_PDM_ECC_CTL0 (CVMX_ADD_IO_SEG(0x00015400008FFFD0ull))
02077 #endif
02078 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02079 #define CVMX_PKO_PDM_ECC_CTL1 CVMX_PKO_PDM_ECC_CTL1_FUNC()
02080 static inline uint64_t CVMX_PKO_PDM_ECC_CTL1_FUNC(void)
02081 {
02082 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02083 cvmx_warn("CVMX_PKO_PDM_ECC_CTL1 not supported on this chip\n");
02084 return CVMX_ADD_IO_SEG(0x00015400008FFFD8ull);
02085 }
02086 #else
02087 #define CVMX_PKO_PDM_ECC_CTL1 (CVMX_ADD_IO_SEG(0x00015400008FFFD8ull))
02088 #endif
02089 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02090 #define CVMX_PKO_PDM_ECC_DBE_STS0 CVMX_PKO_PDM_ECC_DBE_STS0_FUNC()
02091 static inline uint64_t CVMX_PKO_PDM_ECC_DBE_STS0_FUNC(void)
02092 {
02093 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02094 cvmx_warn("CVMX_PKO_PDM_ECC_DBE_STS0 not supported on this chip\n");
02095 return CVMX_ADD_IO_SEG(0x00015400008FFFF0ull);
02096 }
02097 #else
02098 #define CVMX_PKO_PDM_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x00015400008FFFF0ull))
02099 #endif
02100 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02101 #define CVMX_PKO_PDM_ECC_DBE_STS_CMB0 CVMX_PKO_PDM_ECC_DBE_STS_CMB0_FUNC()
02102 static inline uint64_t CVMX_PKO_PDM_ECC_DBE_STS_CMB0_FUNC(void)
02103 {
02104 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02105 cvmx_warn("CVMX_PKO_PDM_ECC_DBE_STS_CMB0 not supported on this chip\n");
02106 return CVMX_ADD_IO_SEG(0x00015400008FFFE0ull);
02107 }
02108 #else
02109 #define CVMX_PKO_PDM_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x00015400008FFFE0ull))
02110 #endif
02111 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02112 #define CVMX_PKO_PDM_ECC_SBE_STS0 CVMX_PKO_PDM_ECC_SBE_STS0_FUNC()
02113 static inline uint64_t CVMX_PKO_PDM_ECC_SBE_STS0_FUNC(void)
02114 {
02115 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02116 cvmx_warn("CVMX_PKO_PDM_ECC_SBE_STS0 not supported on this chip\n");
02117 return CVMX_ADD_IO_SEG(0x00015400008FFFF8ull);
02118 }
02119 #else
02120 #define CVMX_PKO_PDM_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x00015400008FFFF8ull))
02121 #endif
02122 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02123 #define CVMX_PKO_PDM_ECC_SBE_STS_CMB0 CVMX_PKO_PDM_ECC_SBE_STS_CMB0_FUNC()
02124 static inline uint64_t CVMX_PKO_PDM_ECC_SBE_STS_CMB0_FUNC(void)
02125 {
02126 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02127 cvmx_warn("CVMX_PKO_PDM_ECC_SBE_STS_CMB0 not supported on this chip\n");
02128 return CVMX_ADD_IO_SEG(0x00015400008FFFE8ull);
02129 }
02130 #else
02131 #define CVMX_PKO_PDM_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x00015400008FFFE8ull))
02132 #endif
02133 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02134 #define CVMX_PKO_PDM_FILLB_DBG0 CVMX_PKO_PDM_FILLB_DBG0_FUNC()
02135 static inline uint64_t CVMX_PKO_PDM_FILLB_DBG0_FUNC(void)
02136 {
02137 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02138 cvmx_warn("CVMX_PKO_PDM_FILLB_DBG0 not supported on this chip\n");
02139 return CVMX_ADD_IO_SEG(0x00015400008002A0ull);
02140 }
02141 #else
02142 #define CVMX_PKO_PDM_FILLB_DBG0 (CVMX_ADD_IO_SEG(0x00015400008002A0ull))
02143 #endif
02144 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02145 #define CVMX_PKO_PDM_FILLB_DBG1 CVMX_PKO_PDM_FILLB_DBG1_FUNC()
02146 static inline uint64_t CVMX_PKO_PDM_FILLB_DBG1_FUNC(void)
02147 {
02148 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02149 cvmx_warn("CVMX_PKO_PDM_FILLB_DBG1 not supported on this chip\n");
02150 return CVMX_ADD_IO_SEG(0x00015400008002A8ull);
02151 }
02152 #else
02153 #define CVMX_PKO_PDM_FILLB_DBG1 (CVMX_ADD_IO_SEG(0x00015400008002A8ull))
02154 #endif
02155 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02156 #define CVMX_PKO_PDM_FILLB_DBG2 CVMX_PKO_PDM_FILLB_DBG2_FUNC()
02157 static inline uint64_t CVMX_PKO_PDM_FILLB_DBG2_FUNC(void)
02158 {
02159 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02160 cvmx_warn("CVMX_PKO_PDM_FILLB_DBG2 not supported on this chip\n");
02161 return CVMX_ADD_IO_SEG(0x00015400008002B0ull);
02162 }
02163 #else
02164 #define CVMX_PKO_PDM_FILLB_DBG2 (CVMX_ADD_IO_SEG(0x00015400008002B0ull))
02165 #endif
02166 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02167 #define CVMX_PKO_PDM_FLSHB_DBG0 CVMX_PKO_PDM_FLSHB_DBG0_FUNC()
02168 static inline uint64_t CVMX_PKO_PDM_FLSHB_DBG0_FUNC(void)
02169 {
02170 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02171 cvmx_warn("CVMX_PKO_PDM_FLSHB_DBG0 not supported on this chip\n");
02172 return CVMX_ADD_IO_SEG(0x00015400008002B8ull);
02173 }
02174 #else
02175 #define CVMX_PKO_PDM_FLSHB_DBG0 (CVMX_ADD_IO_SEG(0x00015400008002B8ull))
02176 #endif
02177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02178 #define CVMX_PKO_PDM_FLSHB_DBG1 CVMX_PKO_PDM_FLSHB_DBG1_FUNC()
02179 static inline uint64_t CVMX_PKO_PDM_FLSHB_DBG1_FUNC(void)
02180 {
02181 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02182 cvmx_warn("CVMX_PKO_PDM_FLSHB_DBG1 not supported on this chip\n");
02183 return CVMX_ADD_IO_SEG(0x00015400008002C0ull);
02184 }
02185 #else
02186 #define CVMX_PKO_PDM_FLSHB_DBG1 (CVMX_ADD_IO_SEG(0x00015400008002C0ull))
02187 #endif
02188 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02189 #define CVMX_PKO_PDM_INTF_DBG_RD CVMX_PKO_PDM_INTF_DBG_RD_FUNC()
02190 static inline uint64_t CVMX_PKO_PDM_INTF_DBG_RD_FUNC(void)
02191 {
02192 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02193 cvmx_warn("CVMX_PKO_PDM_INTF_DBG_RD not supported on this chip\n");
02194 return CVMX_ADD_IO_SEG(0x0001540000900F20ull);
02195 }
02196 #else
02197 #define CVMX_PKO_PDM_INTF_DBG_RD (CVMX_ADD_IO_SEG(0x0001540000900F20ull))
02198 #endif
02199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02200 #define CVMX_PKO_PDM_ISRD_DBG CVMX_PKO_PDM_ISRD_DBG_FUNC()
02201 static inline uint64_t CVMX_PKO_PDM_ISRD_DBG_FUNC(void)
02202 {
02203 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02204 cvmx_warn("CVMX_PKO_PDM_ISRD_DBG not supported on this chip\n");
02205 return CVMX_ADD_IO_SEG(0x0001540000800090ull);
02206 }
02207 #else
02208 #define CVMX_PKO_PDM_ISRD_DBG (CVMX_ADD_IO_SEG(0x0001540000800090ull))
02209 #endif
02210 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02211 #define CVMX_PKO_PDM_ISRD_DBG_DQ CVMX_PKO_PDM_ISRD_DBG_DQ_FUNC()
02212 static inline uint64_t CVMX_PKO_PDM_ISRD_DBG_DQ_FUNC(void)
02213 {
02214 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02215 cvmx_warn("CVMX_PKO_PDM_ISRD_DBG_DQ not supported on this chip\n");
02216 return CVMX_ADD_IO_SEG(0x0001540000800290ull);
02217 }
02218 #else
02219 #define CVMX_PKO_PDM_ISRD_DBG_DQ (CVMX_ADD_IO_SEG(0x0001540000800290ull))
02220 #endif
02221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02222 #define CVMX_PKO_PDM_ISRM_DBG CVMX_PKO_PDM_ISRM_DBG_FUNC()
02223 static inline uint64_t CVMX_PKO_PDM_ISRM_DBG_FUNC(void)
02224 {
02225 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02226 cvmx_warn("CVMX_PKO_PDM_ISRM_DBG not supported on this chip\n");
02227 return CVMX_ADD_IO_SEG(0x0001540000800098ull);
02228 }
02229 #else
02230 #define CVMX_PKO_PDM_ISRM_DBG (CVMX_ADD_IO_SEG(0x0001540000800098ull))
02231 #endif
02232 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02233 #define CVMX_PKO_PDM_ISRM_DBG_DQ CVMX_PKO_PDM_ISRM_DBG_DQ_FUNC()
02234 static inline uint64_t CVMX_PKO_PDM_ISRM_DBG_DQ_FUNC(void)
02235 {
02236 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02237 cvmx_warn("CVMX_PKO_PDM_ISRM_DBG_DQ not supported on this chip\n");
02238 return CVMX_ADD_IO_SEG(0x0001540000800298ull);
02239 }
02240 #else
02241 #define CVMX_PKO_PDM_ISRM_DBG_DQ (CVMX_ADD_IO_SEG(0x0001540000800298ull))
02242 #endif
02243 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02244 #define CVMX_PKO_PDM_MEM_ADDR CVMX_PKO_PDM_MEM_ADDR_FUNC()
02245 static inline uint64_t CVMX_PKO_PDM_MEM_ADDR_FUNC(void)
02246 {
02247 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02248 cvmx_warn("CVMX_PKO_PDM_MEM_ADDR not supported on this chip\n");
02249 return CVMX_ADD_IO_SEG(0x0001540000800018ull);
02250 }
02251 #else
02252 #define CVMX_PKO_PDM_MEM_ADDR (CVMX_ADD_IO_SEG(0x0001540000800018ull))
02253 #endif
02254 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02255 #define CVMX_PKO_PDM_MEM_DATA CVMX_PKO_PDM_MEM_DATA_FUNC()
02256 static inline uint64_t CVMX_PKO_PDM_MEM_DATA_FUNC(void)
02257 {
02258 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02259 cvmx_warn("CVMX_PKO_PDM_MEM_DATA not supported on this chip\n");
02260 return CVMX_ADD_IO_SEG(0x0001540000800010ull);
02261 }
02262 #else
02263 #define CVMX_PKO_PDM_MEM_DATA (CVMX_ADD_IO_SEG(0x0001540000800010ull))
02264 #endif
02265 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02266 #define CVMX_PKO_PDM_MEM_RW_CTL CVMX_PKO_PDM_MEM_RW_CTL_FUNC()
02267 static inline uint64_t CVMX_PKO_PDM_MEM_RW_CTL_FUNC(void)
02268 {
02269 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02270 cvmx_warn("CVMX_PKO_PDM_MEM_RW_CTL not supported on this chip\n");
02271 return CVMX_ADD_IO_SEG(0x0001540000800020ull);
02272 }
02273 #else
02274 #define CVMX_PKO_PDM_MEM_RW_CTL (CVMX_ADD_IO_SEG(0x0001540000800020ull))
02275 #endif
02276 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02277 #define CVMX_PKO_PDM_MEM_RW_STS CVMX_PKO_PDM_MEM_RW_STS_FUNC()
02278 static inline uint64_t CVMX_PKO_PDM_MEM_RW_STS_FUNC(void)
02279 {
02280 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02281 cvmx_warn("CVMX_PKO_PDM_MEM_RW_STS not supported on this chip\n");
02282 return CVMX_ADD_IO_SEG(0x0001540000800028ull);
02283 }
02284 #else
02285 #define CVMX_PKO_PDM_MEM_RW_STS (CVMX_ADD_IO_SEG(0x0001540000800028ull))
02286 #endif
02287 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02288 #define CVMX_PKO_PDM_MWPBUF_DBG CVMX_PKO_PDM_MWPBUF_DBG_FUNC()
02289 static inline uint64_t CVMX_PKO_PDM_MWPBUF_DBG_FUNC(void)
02290 {
02291 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02292 cvmx_warn("CVMX_PKO_PDM_MWPBUF_DBG not supported on this chip\n");
02293 return CVMX_ADD_IO_SEG(0x00015400008000A0ull);
02294 }
02295 #else
02296 #define CVMX_PKO_PDM_MWPBUF_DBG (CVMX_ADD_IO_SEG(0x00015400008000A0ull))
02297 #endif
02298 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02299 #define CVMX_PKO_PDM_STS CVMX_PKO_PDM_STS_FUNC()
02300 static inline uint64_t CVMX_PKO_PDM_STS_FUNC(void)
02301 {
02302 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02303 cvmx_warn("CVMX_PKO_PDM_STS not supported on this chip\n");
02304 return CVMX_ADD_IO_SEG(0x0001540000800008ull);
02305 }
02306 #else
02307 #define CVMX_PKO_PDM_STS (CVMX_ADD_IO_SEG(0x0001540000800008ull))
02308 #endif
02309 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02310 #define CVMX_PKO_PEB_BIST_STATUS CVMX_PKO_PEB_BIST_STATUS_FUNC()
02311 static inline uint64_t CVMX_PKO_PEB_BIST_STATUS_FUNC(void)
02312 {
02313 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02314 cvmx_warn("CVMX_PKO_PEB_BIST_STATUS not supported on this chip\n");
02315 return CVMX_ADD_IO_SEG(0x0001540000900D00ull);
02316 }
02317 #else
02318 #define CVMX_PKO_PEB_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000900D00ull))
02319 #endif
02320 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02321 #define CVMX_PKO_PEB_ECC_CTL0 CVMX_PKO_PEB_ECC_CTL0_FUNC()
02322 static inline uint64_t CVMX_PKO_PEB_ECC_CTL0_FUNC(void)
02323 {
02324 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02325 cvmx_warn("CVMX_PKO_PEB_ECC_CTL0 not supported on this chip\n");
02326 return CVMX_ADD_IO_SEG(0x00015400009FFFD0ull);
02327 }
02328 #else
02329 #define CVMX_PKO_PEB_ECC_CTL0 (CVMX_ADD_IO_SEG(0x00015400009FFFD0ull))
02330 #endif
02331 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02332 #define CVMX_PKO_PEB_ECC_CTL1 CVMX_PKO_PEB_ECC_CTL1_FUNC()
02333 static inline uint64_t CVMX_PKO_PEB_ECC_CTL1_FUNC(void)
02334 {
02335 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02336 cvmx_warn("CVMX_PKO_PEB_ECC_CTL1 not supported on this chip\n");
02337 return CVMX_ADD_IO_SEG(0x00015400009FFFA8ull);
02338 }
02339 #else
02340 #define CVMX_PKO_PEB_ECC_CTL1 (CVMX_ADD_IO_SEG(0x00015400009FFFA8ull))
02341 #endif
02342 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02343 #define CVMX_PKO_PEB_ECC_DBE_STS0 CVMX_PKO_PEB_ECC_DBE_STS0_FUNC()
02344 static inline uint64_t CVMX_PKO_PEB_ECC_DBE_STS0_FUNC(void)
02345 {
02346 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02347 cvmx_warn("CVMX_PKO_PEB_ECC_DBE_STS0 not supported on this chip\n");
02348 return CVMX_ADD_IO_SEG(0x00015400009FFFF0ull);
02349 }
02350 #else
02351 #define CVMX_PKO_PEB_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x00015400009FFFF0ull))
02352 #endif
02353 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02354 #define CVMX_PKO_PEB_ECC_DBE_STS_CMB0 CVMX_PKO_PEB_ECC_DBE_STS_CMB0_FUNC()
02355 static inline uint64_t CVMX_PKO_PEB_ECC_DBE_STS_CMB0_FUNC(void)
02356 {
02357 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02358 cvmx_warn("CVMX_PKO_PEB_ECC_DBE_STS_CMB0 not supported on this chip\n");
02359 return CVMX_ADD_IO_SEG(0x00015400009FFFD8ull);
02360 }
02361 #else
02362 #define CVMX_PKO_PEB_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x00015400009FFFD8ull))
02363 #endif
02364 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02365 #define CVMX_PKO_PEB_ECC_SBE_STS0 CVMX_PKO_PEB_ECC_SBE_STS0_FUNC()
02366 static inline uint64_t CVMX_PKO_PEB_ECC_SBE_STS0_FUNC(void)
02367 {
02368 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02369 cvmx_warn("CVMX_PKO_PEB_ECC_SBE_STS0 not supported on this chip\n");
02370 return CVMX_ADD_IO_SEG(0x00015400009FFFF8ull);
02371 }
02372 #else
02373 #define CVMX_PKO_PEB_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x00015400009FFFF8ull))
02374 #endif
02375 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02376 #define CVMX_PKO_PEB_ECC_SBE_STS_CMB0 CVMX_PKO_PEB_ECC_SBE_STS_CMB0_FUNC()
02377 static inline uint64_t CVMX_PKO_PEB_ECC_SBE_STS_CMB0_FUNC(void)
02378 {
02379 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02380 cvmx_warn("CVMX_PKO_PEB_ECC_SBE_STS_CMB0 not supported on this chip\n");
02381 return CVMX_ADD_IO_SEG(0x00015400009FFFE8ull);
02382 }
02383 #else
02384 #define CVMX_PKO_PEB_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x00015400009FFFE8ull))
02385 #endif
02386 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02387 #define CVMX_PKO_PEB_ECO CVMX_PKO_PEB_ECO_FUNC()
02388 static inline uint64_t CVMX_PKO_PEB_ECO_FUNC(void)
02389 {
02390 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02391 cvmx_warn("CVMX_PKO_PEB_ECO not supported on this chip\n");
02392 return CVMX_ADD_IO_SEG(0x0001540000901000ull);
02393 }
02394 #else
02395 #define CVMX_PKO_PEB_ECO (CVMX_ADD_IO_SEG(0x0001540000901000ull))
02396 #endif
02397 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02398 #define CVMX_PKO_PEB_ERR_INT CVMX_PKO_PEB_ERR_INT_FUNC()
02399 static inline uint64_t CVMX_PKO_PEB_ERR_INT_FUNC(void)
02400 {
02401 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02402 cvmx_warn("CVMX_PKO_PEB_ERR_INT not supported on this chip\n");
02403 return CVMX_ADD_IO_SEG(0x0001540000900C00ull);
02404 }
02405 #else
02406 #define CVMX_PKO_PEB_ERR_INT (CVMX_ADD_IO_SEG(0x0001540000900C00ull))
02407 #endif
02408 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02409 #define CVMX_PKO_PEB_EXT_HDR_DEF_ERR_INFO CVMX_PKO_PEB_EXT_HDR_DEF_ERR_INFO_FUNC()
02410 static inline uint64_t CVMX_PKO_PEB_EXT_HDR_DEF_ERR_INFO_FUNC(void)
02411 {
02412 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02413 cvmx_warn("CVMX_PKO_PEB_EXT_HDR_DEF_ERR_INFO not supported on this chip\n");
02414 return CVMX_ADD_IO_SEG(0x0001540000900C08ull);
02415 }
02416 #else
02417 #define CVMX_PKO_PEB_EXT_HDR_DEF_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C08ull))
02418 #endif
02419 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02420 #define CVMX_PKO_PEB_FCS_SOP_ERR_INFO CVMX_PKO_PEB_FCS_SOP_ERR_INFO_FUNC()
02421 static inline uint64_t CVMX_PKO_PEB_FCS_SOP_ERR_INFO_FUNC(void)
02422 {
02423 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02424 cvmx_warn("CVMX_PKO_PEB_FCS_SOP_ERR_INFO not supported on this chip\n");
02425 return CVMX_ADD_IO_SEG(0x0001540000900C18ull);
02426 }
02427 #else
02428 #define CVMX_PKO_PEB_FCS_SOP_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C18ull))
02429 #endif
02430 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02431 #define CVMX_PKO_PEB_JUMP_DEF_ERR_INFO CVMX_PKO_PEB_JUMP_DEF_ERR_INFO_FUNC()
02432 static inline uint64_t CVMX_PKO_PEB_JUMP_DEF_ERR_INFO_FUNC(void)
02433 {
02434 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02435 cvmx_warn("CVMX_PKO_PEB_JUMP_DEF_ERR_INFO not supported on this chip\n");
02436 return CVMX_ADD_IO_SEG(0x0001540000900C10ull);
02437 }
02438 #else
02439 #define CVMX_PKO_PEB_JUMP_DEF_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C10ull))
02440 #endif
02441 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02442 #define CVMX_PKO_PEB_MACX_CFG_WR_ERR_INFO CVMX_PKO_PEB_MACX_CFG_WR_ERR_INFO_FUNC()
02443 static inline uint64_t CVMX_PKO_PEB_MACX_CFG_WR_ERR_INFO_FUNC(void)
02444 {
02445 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02446 cvmx_warn("CVMX_PKO_PEB_MACX_CFG_WR_ERR_INFO not supported on this chip\n");
02447 return CVMX_ADD_IO_SEG(0x0001540000900C50ull);
02448 }
02449 #else
02450 #define CVMX_PKO_PEB_MACX_CFG_WR_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C50ull))
02451 #endif
02452 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02453 #define CVMX_PKO_PEB_MAX_LINK_ERR_INFO CVMX_PKO_PEB_MAX_LINK_ERR_INFO_FUNC()
02454 static inline uint64_t CVMX_PKO_PEB_MAX_LINK_ERR_INFO_FUNC(void)
02455 {
02456 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02457 cvmx_warn("CVMX_PKO_PEB_MAX_LINK_ERR_INFO not supported on this chip\n");
02458 return CVMX_ADD_IO_SEG(0x0001540000900C48ull);
02459 }
02460 #else
02461 #define CVMX_PKO_PEB_MAX_LINK_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C48ull))
02462 #endif
02463 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02464 #define CVMX_PKO_PEB_NCB_CFG CVMX_PKO_PEB_NCB_CFG_FUNC()
02465 static inline uint64_t CVMX_PKO_PEB_NCB_CFG_FUNC(void)
02466 {
02467 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02468 cvmx_warn("CVMX_PKO_PEB_NCB_CFG not supported on this chip\n");
02469 return CVMX_ADD_IO_SEG(0x0001540000900308ull);
02470 }
02471 #else
02472 #define CVMX_PKO_PEB_NCB_CFG (CVMX_ADD_IO_SEG(0x0001540000900308ull))
02473 #endif
02474 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02475 #define CVMX_PKO_PEB_PAD_ERR_INFO CVMX_PKO_PEB_PAD_ERR_INFO_FUNC()
02476 static inline uint64_t CVMX_PKO_PEB_PAD_ERR_INFO_FUNC(void)
02477 {
02478 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02479 cvmx_warn("CVMX_PKO_PEB_PAD_ERR_INFO not supported on this chip\n");
02480 return CVMX_ADD_IO_SEG(0x0001540000900C28ull);
02481 }
02482 #else
02483 #define CVMX_PKO_PEB_PAD_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C28ull))
02484 #endif
02485 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02486 #define CVMX_PKO_PEB_PSE_FIFO_ERR_INFO CVMX_PKO_PEB_PSE_FIFO_ERR_INFO_FUNC()
02487 static inline uint64_t CVMX_PKO_PEB_PSE_FIFO_ERR_INFO_FUNC(void)
02488 {
02489 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02490 cvmx_warn("CVMX_PKO_PEB_PSE_FIFO_ERR_INFO not supported on this chip\n");
02491 return CVMX_ADD_IO_SEG(0x0001540000900C20ull);
02492 }
02493 #else
02494 #define CVMX_PKO_PEB_PSE_FIFO_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C20ull))
02495 #endif
02496 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02497 #define CVMX_PKO_PEB_SUBD_ADDR_ERR_INFO CVMX_PKO_PEB_SUBD_ADDR_ERR_INFO_FUNC()
02498 static inline uint64_t CVMX_PKO_PEB_SUBD_ADDR_ERR_INFO_FUNC(void)
02499 {
02500 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02501 cvmx_warn("CVMX_PKO_PEB_SUBD_ADDR_ERR_INFO not supported on this chip\n");
02502 return CVMX_ADD_IO_SEG(0x0001540000900C38ull);
02503 }
02504 #else
02505 #define CVMX_PKO_PEB_SUBD_ADDR_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C38ull))
02506 #endif
02507 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02508 #define CVMX_PKO_PEB_SUBD_SIZE_ERR_INFO CVMX_PKO_PEB_SUBD_SIZE_ERR_INFO_FUNC()
02509 static inline uint64_t CVMX_PKO_PEB_SUBD_SIZE_ERR_INFO_FUNC(void)
02510 {
02511 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02512 cvmx_warn("CVMX_PKO_PEB_SUBD_SIZE_ERR_INFO not supported on this chip\n");
02513 return CVMX_ADD_IO_SEG(0x0001540000900C40ull);
02514 }
02515 #else
02516 #define CVMX_PKO_PEB_SUBD_SIZE_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C40ull))
02517 #endif
02518 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02519 #define CVMX_PKO_PEB_TRUNC_ERR_INFO CVMX_PKO_PEB_TRUNC_ERR_INFO_FUNC()
02520 static inline uint64_t CVMX_PKO_PEB_TRUNC_ERR_INFO_FUNC(void)
02521 {
02522 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02523 cvmx_warn("CVMX_PKO_PEB_TRUNC_ERR_INFO not supported on this chip\n");
02524 return CVMX_ADD_IO_SEG(0x0001540000900C30ull);
02525 }
02526 #else
02527 #define CVMX_PKO_PEB_TRUNC_ERR_INFO (CVMX_ADD_IO_SEG(0x0001540000900C30ull))
02528 #endif
02529 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02530 #define CVMX_PKO_PEB_TSO_CFG CVMX_PKO_PEB_TSO_CFG_FUNC()
02531 static inline uint64_t CVMX_PKO_PEB_TSO_CFG_FUNC(void)
02532 {
02533 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02534 cvmx_warn("CVMX_PKO_PEB_TSO_CFG not supported on this chip\n");
02535 return CVMX_ADD_IO_SEG(0x0001540000900310ull);
02536 }
02537 #else
02538 #define CVMX_PKO_PEB_TSO_CFG (CVMX_ADD_IO_SEG(0x0001540000900310ull))
02539 #endif
02540 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02541 #define CVMX_PKO_PQA_DEBUG CVMX_PKO_PQA_DEBUG_FUNC()
02542 static inline uint64_t CVMX_PKO_PQA_DEBUG_FUNC(void)
02543 {
02544 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02545 cvmx_warn("CVMX_PKO_PQA_DEBUG not supported on this chip\n");
02546 return CVMX_ADD_IO_SEG(0x0001540000000128ull);
02547 }
02548 #else
02549 #define CVMX_PKO_PQA_DEBUG (CVMX_ADD_IO_SEG(0x0001540000000128ull))
02550 #endif
02551 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02552 #define CVMX_PKO_PQB_DEBUG CVMX_PKO_PQB_DEBUG_FUNC()
02553 static inline uint64_t CVMX_PKO_PQB_DEBUG_FUNC(void)
02554 {
02555 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02556 cvmx_warn("CVMX_PKO_PQB_DEBUG not supported on this chip\n");
02557 return CVMX_ADD_IO_SEG(0x0001540000000130ull);
02558 }
02559 #else
02560 #define CVMX_PKO_PQB_DEBUG (CVMX_ADD_IO_SEG(0x0001540000000130ull))
02561 #endif
02562 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02563 #define CVMX_PKO_PQ_CSR_BUS_DEBUG CVMX_PKO_PQ_CSR_BUS_DEBUG_FUNC()
02564 static inline uint64_t CVMX_PKO_PQ_CSR_BUS_DEBUG_FUNC(void)
02565 {
02566 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02567 cvmx_warn("CVMX_PKO_PQ_CSR_BUS_DEBUG not supported on this chip\n");
02568 return CVMX_ADD_IO_SEG(0x00015400000001F8ull);
02569 }
02570 #else
02571 #define CVMX_PKO_PQ_CSR_BUS_DEBUG (CVMX_ADD_IO_SEG(0x00015400000001F8ull))
02572 #endif
02573 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02574 #define CVMX_PKO_PQ_DEBUG_GREEN CVMX_PKO_PQ_DEBUG_GREEN_FUNC()
02575 static inline uint64_t CVMX_PKO_PQ_DEBUG_GREEN_FUNC(void)
02576 {
02577 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02578 cvmx_warn("CVMX_PKO_PQ_DEBUG_GREEN not supported on this chip\n");
02579 return CVMX_ADD_IO_SEG(0x0001540000000058ull);
02580 }
02581 #else
02582 #define CVMX_PKO_PQ_DEBUG_GREEN (CVMX_ADD_IO_SEG(0x0001540000000058ull))
02583 #endif
02584 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02585 #define CVMX_PKO_PQ_DEBUG_LINKS CVMX_PKO_PQ_DEBUG_LINKS_FUNC()
02586 static inline uint64_t CVMX_PKO_PQ_DEBUG_LINKS_FUNC(void)
02587 {
02588 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02589 cvmx_warn("CVMX_PKO_PQ_DEBUG_LINKS not supported on this chip\n");
02590 return CVMX_ADD_IO_SEG(0x0001540000000068ull);
02591 }
02592 #else
02593 #define CVMX_PKO_PQ_DEBUG_LINKS (CVMX_ADD_IO_SEG(0x0001540000000068ull))
02594 #endif
02595 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02596 #define CVMX_PKO_PQ_DEBUG_YELLOW CVMX_PKO_PQ_DEBUG_YELLOW_FUNC()
02597 static inline uint64_t CVMX_PKO_PQ_DEBUG_YELLOW_FUNC(void)
02598 {
02599 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02600 cvmx_warn("CVMX_PKO_PQ_DEBUG_YELLOW not supported on this chip\n");
02601 return CVMX_ADD_IO_SEG(0x0001540000000060ull);
02602 }
02603 #else
02604 #define CVMX_PKO_PQ_DEBUG_YELLOW (CVMX_ADD_IO_SEG(0x0001540000000060ull))
02605 #endif
02606 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02607 #define CVMX_PKO_PSE_DQ_BIST_STATUS CVMX_PKO_PSE_DQ_BIST_STATUS_FUNC()
02608 static inline uint64_t CVMX_PKO_PSE_DQ_BIST_STATUS_FUNC(void)
02609 {
02610 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02611 cvmx_warn("CVMX_PKO_PSE_DQ_BIST_STATUS not supported on this chip\n");
02612 return CVMX_ADD_IO_SEG(0x0001540000300138ull);
02613 }
02614 #else
02615 #define CVMX_PKO_PSE_DQ_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000300138ull))
02616 #endif
02617 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02618 #define CVMX_PKO_PSE_DQ_ECC_CTL0 CVMX_PKO_PSE_DQ_ECC_CTL0_FUNC()
02619 static inline uint64_t CVMX_PKO_PSE_DQ_ECC_CTL0_FUNC(void)
02620 {
02621 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02622 cvmx_warn("CVMX_PKO_PSE_DQ_ECC_CTL0 not supported on this chip\n");
02623 return CVMX_ADD_IO_SEG(0x0001540000300100ull);
02624 }
02625 #else
02626 #define CVMX_PKO_PSE_DQ_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000300100ull))
02627 #endif
02628 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02629 #define CVMX_PKO_PSE_DQ_ECC_DBE_STS0 CVMX_PKO_PSE_DQ_ECC_DBE_STS0_FUNC()
02630 static inline uint64_t CVMX_PKO_PSE_DQ_ECC_DBE_STS0_FUNC(void)
02631 {
02632 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02633 cvmx_warn("CVMX_PKO_PSE_DQ_ECC_DBE_STS0 not supported on this chip\n");
02634 return CVMX_ADD_IO_SEG(0x0001540000300118ull);
02635 }
02636 #else
02637 #define CVMX_PKO_PSE_DQ_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000300118ull))
02638 #endif
02639 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02640 #define CVMX_PKO_PSE_DQ_ECC_DBE_STS_CMB0 CVMX_PKO_PSE_DQ_ECC_DBE_STS_CMB0_FUNC()
02641 static inline uint64_t CVMX_PKO_PSE_DQ_ECC_DBE_STS_CMB0_FUNC(void)
02642 {
02643 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02644 cvmx_warn("CVMX_PKO_PSE_DQ_ECC_DBE_STS_CMB0 not supported on this chip\n");
02645 return CVMX_ADD_IO_SEG(0x0001540000300120ull);
02646 }
02647 #else
02648 #define CVMX_PKO_PSE_DQ_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000300120ull))
02649 #endif
02650 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02651 #define CVMX_PKO_PSE_DQ_ECC_SBE_STS0 CVMX_PKO_PSE_DQ_ECC_SBE_STS0_FUNC()
02652 static inline uint64_t CVMX_PKO_PSE_DQ_ECC_SBE_STS0_FUNC(void)
02653 {
02654 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02655 cvmx_warn("CVMX_PKO_PSE_DQ_ECC_SBE_STS0 not supported on this chip\n");
02656 return CVMX_ADD_IO_SEG(0x0001540000300108ull);
02657 }
02658 #else
02659 #define CVMX_PKO_PSE_DQ_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000300108ull))
02660 #endif
02661 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02662 #define CVMX_PKO_PSE_DQ_ECC_SBE_STS_CMB0 CVMX_PKO_PSE_DQ_ECC_SBE_STS_CMB0_FUNC()
02663 static inline uint64_t CVMX_PKO_PSE_DQ_ECC_SBE_STS_CMB0_FUNC(void)
02664 {
02665 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02666 cvmx_warn("CVMX_PKO_PSE_DQ_ECC_SBE_STS_CMB0 not supported on this chip\n");
02667 return CVMX_ADD_IO_SEG(0x0001540000300110ull);
02668 }
02669 #else
02670 #define CVMX_PKO_PSE_DQ_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000300110ull))
02671 #endif
02672 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02673 #define CVMX_PKO_PSE_PQ_BIST_STATUS CVMX_PKO_PSE_PQ_BIST_STATUS_FUNC()
02674 static inline uint64_t CVMX_PKO_PSE_PQ_BIST_STATUS_FUNC(void)
02675 {
02676 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02677 cvmx_warn("CVMX_PKO_PSE_PQ_BIST_STATUS not supported on this chip\n");
02678 return CVMX_ADD_IO_SEG(0x0001540000000138ull);
02679 }
02680 #else
02681 #define CVMX_PKO_PSE_PQ_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000000138ull))
02682 #endif
02683 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02684 #define CVMX_PKO_PSE_PQ_ECC_CTL0 CVMX_PKO_PSE_PQ_ECC_CTL0_FUNC()
02685 static inline uint64_t CVMX_PKO_PSE_PQ_ECC_CTL0_FUNC(void)
02686 {
02687 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02688 cvmx_warn("CVMX_PKO_PSE_PQ_ECC_CTL0 not supported on this chip\n");
02689 return CVMX_ADD_IO_SEG(0x0001540000000100ull);
02690 }
02691 #else
02692 #define CVMX_PKO_PSE_PQ_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000000100ull))
02693 #endif
02694 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02695 #define CVMX_PKO_PSE_PQ_ECC_DBE_STS0 CVMX_PKO_PSE_PQ_ECC_DBE_STS0_FUNC()
02696 static inline uint64_t CVMX_PKO_PSE_PQ_ECC_DBE_STS0_FUNC(void)
02697 {
02698 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02699 cvmx_warn("CVMX_PKO_PSE_PQ_ECC_DBE_STS0 not supported on this chip\n");
02700 return CVMX_ADD_IO_SEG(0x0001540000000118ull);
02701 }
02702 #else
02703 #define CVMX_PKO_PSE_PQ_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000000118ull))
02704 #endif
02705 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02706 #define CVMX_PKO_PSE_PQ_ECC_DBE_STS_CMB0 CVMX_PKO_PSE_PQ_ECC_DBE_STS_CMB0_FUNC()
02707 static inline uint64_t CVMX_PKO_PSE_PQ_ECC_DBE_STS_CMB0_FUNC(void)
02708 {
02709 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02710 cvmx_warn("CVMX_PKO_PSE_PQ_ECC_DBE_STS_CMB0 not supported on this chip\n");
02711 return CVMX_ADD_IO_SEG(0x0001540000000120ull);
02712 }
02713 #else
02714 #define CVMX_PKO_PSE_PQ_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000000120ull))
02715 #endif
02716 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02717 #define CVMX_PKO_PSE_PQ_ECC_SBE_STS0 CVMX_PKO_PSE_PQ_ECC_SBE_STS0_FUNC()
02718 static inline uint64_t CVMX_PKO_PSE_PQ_ECC_SBE_STS0_FUNC(void)
02719 {
02720 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02721 cvmx_warn("CVMX_PKO_PSE_PQ_ECC_SBE_STS0 not supported on this chip\n");
02722 return CVMX_ADD_IO_SEG(0x0001540000000108ull);
02723 }
02724 #else
02725 #define CVMX_PKO_PSE_PQ_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000000108ull))
02726 #endif
02727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02728 #define CVMX_PKO_PSE_PQ_ECC_SBE_STS_CMB0 CVMX_PKO_PSE_PQ_ECC_SBE_STS_CMB0_FUNC()
02729 static inline uint64_t CVMX_PKO_PSE_PQ_ECC_SBE_STS_CMB0_FUNC(void)
02730 {
02731 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02732 cvmx_warn("CVMX_PKO_PSE_PQ_ECC_SBE_STS_CMB0 not supported on this chip\n");
02733 return CVMX_ADD_IO_SEG(0x0001540000000110ull);
02734 }
02735 #else
02736 #define CVMX_PKO_PSE_PQ_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000000110ull))
02737 #endif
02738 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02739 #define CVMX_PKO_PSE_SQ1_BIST_STATUS CVMX_PKO_PSE_SQ1_BIST_STATUS_FUNC()
02740 static inline uint64_t CVMX_PKO_PSE_SQ1_BIST_STATUS_FUNC(void)
02741 {
02742 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02743 cvmx_warn("CVMX_PKO_PSE_SQ1_BIST_STATUS not supported on this chip\n");
02744 return CVMX_ADD_IO_SEG(0x0001540000080138ull);
02745 }
02746 #else
02747 #define CVMX_PKO_PSE_SQ1_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000080138ull))
02748 #endif
02749 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02750 #define CVMX_PKO_PSE_SQ1_ECC_CTL0 CVMX_PKO_PSE_SQ1_ECC_CTL0_FUNC()
02751 static inline uint64_t CVMX_PKO_PSE_SQ1_ECC_CTL0_FUNC(void)
02752 {
02753 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02754 cvmx_warn("CVMX_PKO_PSE_SQ1_ECC_CTL0 not supported on this chip\n");
02755 return CVMX_ADD_IO_SEG(0x0001540000080100ull);
02756 }
02757 #else
02758 #define CVMX_PKO_PSE_SQ1_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000080100ull))
02759 #endif
02760 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02761 #define CVMX_PKO_PSE_SQ1_ECC_DBE_STS0 CVMX_PKO_PSE_SQ1_ECC_DBE_STS0_FUNC()
02762 static inline uint64_t CVMX_PKO_PSE_SQ1_ECC_DBE_STS0_FUNC(void)
02763 {
02764 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02765 cvmx_warn("CVMX_PKO_PSE_SQ1_ECC_DBE_STS0 not supported on this chip\n");
02766 return CVMX_ADD_IO_SEG(0x0001540000080118ull);
02767 }
02768 #else
02769 #define CVMX_PKO_PSE_SQ1_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000080118ull))
02770 #endif
02771 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02772 #define CVMX_PKO_PSE_SQ1_ECC_DBE_STS_CMB0 CVMX_PKO_PSE_SQ1_ECC_DBE_STS_CMB0_FUNC()
02773 static inline uint64_t CVMX_PKO_PSE_SQ1_ECC_DBE_STS_CMB0_FUNC(void)
02774 {
02775 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02776 cvmx_warn("CVMX_PKO_PSE_SQ1_ECC_DBE_STS_CMB0 not supported on this chip\n");
02777 return CVMX_ADD_IO_SEG(0x0001540000080120ull);
02778 }
02779 #else
02780 #define CVMX_PKO_PSE_SQ1_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000080120ull))
02781 #endif
02782 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02783 #define CVMX_PKO_PSE_SQ1_ECC_SBE_STS0 CVMX_PKO_PSE_SQ1_ECC_SBE_STS0_FUNC()
02784 static inline uint64_t CVMX_PKO_PSE_SQ1_ECC_SBE_STS0_FUNC(void)
02785 {
02786 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02787 cvmx_warn("CVMX_PKO_PSE_SQ1_ECC_SBE_STS0 not supported on this chip\n");
02788 return CVMX_ADD_IO_SEG(0x0001540000080108ull);
02789 }
02790 #else
02791 #define CVMX_PKO_PSE_SQ1_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000080108ull))
02792 #endif
02793 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02794 #define CVMX_PKO_PSE_SQ1_ECC_SBE_STS_CMB0 CVMX_PKO_PSE_SQ1_ECC_SBE_STS_CMB0_FUNC()
02795 static inline uint64_t CVMX_PKO_PSE_SQ1_ECC_SBE_STS_CMB0_FUNC(void)
02796 {
02797 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02798 cvmx_warn("CVMX_PKO_PSE_SQ1_ECC_SBE_STS_CMB0 not supported on this chip\n");
02799 return CVMX_ADD_IO_SEG(0x0001540000080110ull);
02800 }
02801 #else
02802 #define CVMX_PKO_PSE_SQ1_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000080110ull))
02803 #endif
02804 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02805 #define CVMX_PKO_PSE_SQ2_BIST_STATUS CVMX_PKO_PSE_SQ2_BIST_STATUS_FUNC()
02806 static inline uint64_t CVMX_PKO_PSE_SQ2_BIST_STATUS_FUNC(void)
02807 {
02808 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02809 cvmx_warn("CVMX_PKO_PSE_SQ2_BIST_STATUS not supported on this chip\n");
02810 return CVMX_ADD_IO_SEG(0x0001540000100138ull);
02811 }
02812 #else
02813 #define CVMX_PKO_PSE_SQ2_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000100138ull))
02814 #endif
02815 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02816 #define CVMX_PKO_PSE_SQ2_ECC_CTL0 CVMX_PKO_PSE_SQ2_ECC_CTL0_FUNC()
02817 static inline uint64_t CVMX_PKO_PSE_SQ2_ECC_CTL0_FUNC(void)
02818 {
02819 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02820 cvmx_warn("CVMX_PKO_PSE_SQ2_ECC_CTL0 not supported on this chip\n");
02821 return CVMX_ADD_IO_SEG(0x0001540000100100ull);
02822 }
02823 #else
02824 #define CVMX_PKO_PSE_SQ2_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000100100ull))
02825 #endif
02826 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02827 #define CVMX_PKO_PSE_SQ2_ECC_DBE_STS0 CVMX_PKO_PSE_SQ2_ECC_DBE_STS0_FUNC()
02828 static inline uint64_t CVMX_PKO_PSE_SQ2_ECC_DBE_STS0_FUNC(void)
02829 {
02830 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02831 cvmx_warn("CVMX_PKO_PSE_SQ2_ECC_DBE_STS0 not supported on this chip\n");
02832 return CVMX_ADD_IO_SEG(0x0001540000100118ull);
02833 }
02834 #else
02835 #define CVMX_PKO_PSE_SQ2_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000100118ull))
02836 #endif
02837 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02838 #define CVMX_PKO_PSE_SQ2_ECC_DBE_STS_CMB0 CVMX_PKO_PSE_SQ2_ECC_DBE_STS_CMB0_FUNC()
02839 static inline uint64_t CVMX_PKO_PSE_SQ2_ECC_DBE_STS_CMB0_FUNC(void)
02840 {
02841 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02842 cvmx_warn("CVMX_PKO_PSE_SQ2_ECC_DBE_STS_CMB0 not supported on this chip\n");
02843 return CVMX_ADD_IO_SEG(0x0001540000100120ull);
02844 }
02845 #else
02846 #define CVMX_PKO_PSE_SQ2_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000100120ull))
02847 #endif
02848 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02849 #define CVMX_PKO_PSE_SQ2_ECC_SBE_STS0 CVMX_PKO_PSE_SQ2_ECC_SBE_STS0_FUNC()
02850 static inline uint64_t CVMX_PKO_PSE_SQ2_ECC_SBE_STS0_FUNC(void)
02851 {
02852 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02853 cvmx_warn("CVMX_PKO_PSE_SQ2_ECC_SBE_STS0 not supported on this chip\n");
02854 return CVMX_ADD_IO_SEG(0x0001540000100108ull);
02855 }
02856 #else
02857 #define CVMX_PKO_PSE_SQ2_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000100108ull))
02858 #endif
02859 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02860 #define CVMX_PKO_PSE_SQ2_ECC_SBE_STS_CMB0 CVMX_PKO_PSE_SQ2_ECC_SBE_STS_CMB0_FUNC()
02861 static inline uint64_t CVMX_PKO_PSE_SQ2_ECC_SBE_STS_CMB0_FUNC(void)
02862 {
02863 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02864 cvmx_warn("CVMX_PKO_PSE_SQ2_ECC_SBE_STS_CMB0 not supported on this chip\n");
02865 return CVMX_ADD_IO_SEG(0x0001540000100110ull);
02866 }
02867 #else
02868 #define CVMX_PKO_PSE_SQ2_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000100110ull))
02869 #endif
02870 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02871 #define CVMX_PKO_PSE_SQ3_BIST_STATUS CVMX_PKO_PSE_SQ3_BIST_STATUS_FUNC()
02872 static inline uint64_t CVMX_PKO_PSE_SQ3_BIST_STATUS_FUNC(void)
02873 {
02874 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02875 cvmx_warn("CVMX_PKO_PSE_SQ3_BIST_STATUS not supported on this chip\n");
02876 return CVMX_ADD_IO_SEG(0x0001540000180138ull);
02877 }
02878 #else
02879 #define CVMX_PKO_PSE_SQ3_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000180138ull))
02880 #endif
02881 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02882 #define CVMX_PKO_PSE_SQ3_ECC_CTL0 CVMX_PKO_PSE_SQ3_ECC_CTL0_FUNC()
02883 static inline uint64_t CVMX_PKO_PSE_SQ3_ECC_CTL0_FUNC(void)
02884 {
02885 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02886 cvmx_warn("CVMX_PKO_PSE_SQ3_ECC_CTL0 not supported on this chip\n");
02887 return CVMX_ADD_IO_SEG(0x0001540000180100ull);
02888 }
02889 #else
02890 #define CVMX_PKO_PSE_SQ3_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000180100ull))
02891 #endif
02892 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02893 #define CVMX_PKO_PSE_SQ3_ECC_DBE_STS0 CVMX_PKO_PSE_SQ3_ECC_DBE_STS0_FUNC()
02894 static inline uint64_t CVMX_PKO_PSE_SQ3_ECC_DBE_STS0_FUNC(void)
02895 {
02896 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02897 cvmx_warn("CVMX_PKO_PSE_SQ3_ECC_DBE_STS0 not supported on this chip\n");
02898 return CVMX_ADD_IO_SEG(0x0001540000180118ull);
02899 }
02900 #else
02901 #define CVMX_PKO_PSE_SQ3_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000180118ull))
02902 #endif
02903 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02904 #define CVMX_PKO_PSE_SQ3_ECC_DBE_STS_CMB0 CVMX_PKO_PSE_SQ3_ECC_DBE_STS_CMB0_FUNC()
02905 static inline uint64_t CVMX_PKO_PSE_SQ3_ECC_DBE_STS_CMB0_FUNC(void)
02906 {
02907 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02908 cvmx_warn("CVMX_PKO_PSE_SQ3_ECC_DBE_STS_CMB0 not supported on this chip\n");
02909 return CVMX_ADD_IO_SEG(0x0001540000180120ull);
02910 }
02911 #else
02912 #define CVMX_PKO_PSE_SQ3_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000180120ull))
02913 #endif
02914 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02915 #define CVMX_PKO_PSE_SQ3_ECC_SBE_STS0 CVMX_PKO_PSE_SQ3_ECC_SBE_STS0_FUNC()
02916 static inline uint64_t CVMX_PKO_PSE_SQ3_ECC_SBE_STS0_FUNC(void)
02917 {
02918 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02919 cvmx_warn("CVMX_PKO_PSE_SQ3_ECC_SBE_STS0 not supported on this chip\n");
02920 return CVMX_ADD_IO_SEG(0x0001540000180108ull);
02921 }
02922 #else
02923 #define CVMX_PKO_PSE_SQ3_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000180108ull))
02924 #endif
02925 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02926 #define CVMX_PKO_PSE_SQ3_ECC_SBE_STS_CMB0 CVMX_PKO_PSE_SQ3_ECC_SBE_STS_CMB0_FUNC()
02927 static inline uint64_t CVMX_PKO_PSE_SQ3_ECC_SBE_STS_CMB0_FUNC(void)
02928 {
02929 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
02930 cvmx_warn("CVMX_PKO_PSE_SQ3_ECC_SBE_STS_CMB0 not supported on this chip\n");
02931 return CVMX_ADD_IO_SEG(0x0001540000180110ull);
02932 }
02933 #else
02934 #define CVMX_PKO_PSE_SQ3_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000180110ull))
02935 #endif
02936 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02937 #define CVMX_PKO_PSE_SQ4_BIST_STATUS CVMX_PKO_PSE_SQ4_BIST_STATUS_FUNC()
02938 static inline uint64_t CVMX_PKO_PSE_SQ4_BIST_STATUS_FUNC(void)
02939 {
02940 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
02941 cvmx_warn("CVMX_PKO_PSE_SQ4_BIST_STATUS not supported on this chip\n");
02942 return CVMX_ADD_IO_SEG(0x0001540000200138ull);
02943 }
02944 #else
02945 #define CVMX_PKO_PSE_SQ4_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000200138ull))
02946 #endif
02947 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02948 #define CVMX_PKO_PSE_SQ4_ECC_CTL0 CVMX_PKO_PSE_SQ4_ECC_CTL0_FUNC()
02949 static inline uint64_t CVMX_PKO_PSE_SQ4_ECC_CTL0_FUNC(void)
02950 {
02951 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
02952 cvmx_warn("CVMX_PKO_PSE_SQ4_ECC_CTL0 not supported on this chip\n");
02953 return CVMX_ADD_IO_SEG(0x0001540000200100ull);
02954 }
02955 #else
02956 #define CVMX_PKO_PSE_SQ4_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000200100ull))
02957 #endif
02958 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02959 #define CVMX_PKO_PSE_SQ4_ECC_DBE_STS0 CVMX_PKO_PSE_SQ4_ECC_DBE_STS0_FUNC()
02960 static inline uint64_t CVMX_PKO_PSE_SQ4_ECC_DBE_STS0_FUNC(void)
02961 {
02962 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
02963 cvmx_warn("CVMX_PKO_PSE_SQ4_ECC_DBE_STS0 not supported on this chip\n");
02964 return CVMX_ADD_IO_SEG(0x0001540000200118ull);
02965 }
02966 #else
02967 #define CVMX_PKO_PSE_SQ4_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000200118ull))
02968 #endif
02969 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02970 #define CVMX_PKO_PSE_SQ4_ECC_DBE_STS_CMB0 CVMX_PKO_PSE_SQ4_ECC_DBE_STS_CMB0_FUNC()
02971 static inline uint64_t CVMX_PKO_PSE_SQ4_ECC_DBE_STS_CMB0_FUNC(void)
02972 {
02973 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
02974 cvmx_warn("CVMX_PKO_PSE_SQ4_ECC_DBE_STS_CMB0 not supported on this chip\n");
02975 return CVMX_ADD_IO_SEG(0x0001540000200120ull);
02976 }
02977 #else
02978 #define CVMX_PKO_PSE_SQ4_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000200120ull))
02979 #endif
02980 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02981 #define CVMX_PKO_PSE_SQ4_ECC_SBE_STS0 CVMX_PKO_PSE_SQ4_ECC_SBE_STS0_FUNC()
02982 static inline uint64_t CVMX_PKO_PSE_SQ4_ECC_SBE_STS0_FUNC(void)
02983 {
02984 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
02985 cvmx_warn("CVMX_PKO_PSE_SQ4_ECC_SBE_STS0 not supported on this chip\n");
02986 return CVMX_ADD_IO_SEG(0x0001540000200108ull);
02987 }
02988 #else
02989 #define CVMX_PKO_PSE_SQ4_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000200108ull))
02990 #endif
02991 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
02992 #define CVMX_PKO_PSE_SQ4_ECC_SBE_STS_CMB0 CVMX_PKO_PSE_SQ4_ECC_SBE_STS_CMB0_FUNC()
02993 static inline uint64_t CVMX_PKO_PSE_SQ4_ECC_SBE_STS_CMB0_FUNC(void)
02994 {
02995 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
02996 cvmx_warn("CVMX_PKO_PSE_SQ4_ECC_SBE_STS_CMB0 not supported on this chip\n");
02997 return CVMX_ADD_IO_SEG(0x0001540000200110ull);
02998 }
02999 #else
03000 #define CVMX_PKO_PSE_SQ4_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000200110ull))
03001 #endif
03002 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03003 #define CVMX_PKO_PSE_SQ5_BIST_STATUS CVMX_PKO_PSE_SQ5_BIST_STATUS_FUNC()
03004 static inline uint64_t CVMX_PKO_PSE_SQ5_BIST_STATUS_FUNC(void)
03005 {
03006 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
03007 cvmx_warn("CVMX_PKO_PSE_SQ5_BIST_STATUS not supported on this chip\n");
03008 return CVMX_ADD_IO_SEG(0x0001540000280138ull);
03009 }
03010 #else
03011 #define CVMX_PKO_PSE_SQ5_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001540000280138ull))
03012 #endif
03013 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03014 #define CVMX_PKO_PSE_SQ5_ECC_CTL0 CVMX_PKO_PSE_SQ5_ECC_CTL0_FUNC()
03015 static inline uint64_t CVMX_PKO_PSE_SQ5_ECC_CTL0_FUNC(void)
03016 {
03017 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
03018 cvmx_warn("CVMX_PKO_PSE_SQ5_ECC_CTL0 not supported on this chip\n");
03019 return CVMX_ADD_IO_SEG(0x0001540000280100ull);
03020 }
03021 #else
03022 #define CVMX_PKO_PSE_SQ5_ECC_CTL0 (CVMX_ADD_IO_SEG(0x0001540000280100ull))
03023 #endif
03024 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03025 #define CVMX_PKO_PSE_SQ5_ECC_DBE_STS0 CVMX_PKO_PSE_SQ5_ECC_DBE_STS0_FUNC()
03026 static inline uint64_t CVMX_PKO_PSE_SQ5_ECC_DBE_STS0_FUNC(void)
03027 {
03028 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
03029 cvmx_warn("CVMX_PKO_PSE_SQ5_ECC_DBE_STS0 not supported on this chip\n");
03030 return CVMX_ADD_IO_SEG(0x0001540000280118ull);
03031 }
03032 #else
03033 #define CVMX_PKO_PSE_SQ5_ECC_DBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000280118ull))
03034 #endif
03035 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03036 #define CVMX_PKO_PSE_SQ5_ECC_DBE_STS_CMB0 CVMX_PKO_PSE_SQ5_ECC_DBE_STS_CMB0_FUNC()
03037 static inline uint64_t CVMX_PKO_PSE_SQ5_ECC_DBE_STS_CMB0_FUNC(void)
03038 {
03039 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
03040 cvmx_warn("CVMX_PKO_PSE_SQ5_ECC_DBE_STS_CMB0 not supported on this chip\n");
03041 return CVMX_ADD_IO_SEG(0x0001540000280120ull);
03042 }
03043 #else
03044 #define CVMX_PKO_PSE_SQ5_ECC_DBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000280120ull))
03045 #endif
03046 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03047 #define CVMX_PKO_PSE_SQ5_ECC_SBE_STS0 CVMX_PKO_PSE_SQ5_ECC_SBE_STS0_FUNC()
03048 static inline uint64_t CVMX_PKO_PSE_SQ5_ECC_SBE_STS0_FUNC(void)
03049 {
03050 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
03051 cvmx_warn("CVMX_PKO_PSE_SQ5_ECC_SBE_STS0 not supported on this chip\n");
03052 return CVMX_ADD_IO_SEG(0x0001540000280108ull);
03053 }
03054 #else
03055 #define CVMX_PKO_PSE_SQ5_ECC_SBE_STS0 (CVMX_ADD_IO_SEG(0x0001540000280108ull))
03056 #endif
03057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03058 #define CVMX_PKO_PSE_SQ5_ECC_SBE_STS_CMB0 CVMX_PKO_PSE_SQ5_ECC_SBE_STS_CMB0_FUNC()
03059 static inline uint64_t CVMX_PKO_PSE_SQ5_ECC_SBE_STS_CMB0_FUNC(void)
03060 {
03061 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)))
03062 cvmx_warn("CVMX_PKO_PSE_SQ5_ECC_SBE_STS_CMB0 not supported on this chip\n");
03063 return CVMX_ADD_IO_SEG(0x0001540000280110ull);
03064 }
03065 #else
03066 #define CVMX_PKO_PSE_SQ5_ECC_SBE_STS_CMB0 (CVMX_ADD_IO_SEG(0x0001540000280110ull))
03067 #endif
03068 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03069 static inline uint64_t CVMX_PKO_PTFX_STATUS(unsigned long offset)
03070 {
03071 if (!(
03072 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
03073 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 27))) ||
03074 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 27))) ||
03075 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
03076 cvmx_warn("CVMX_PKO_PTFX_STATUS(%lu) is invalid on this chip\n", offset);
03077 return CVMX_ADD_IO_SEG(0x0001540000900100ull) + ((offset) & 31) * 8;
03078 }
03079 #else
03080 #define CVMX_PKO_PTFX_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001540000900100ull) + ((offset) & 31) * 8)
03081 #endif
03082 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03083 #define CVMX_PKO_PTF_IOBP_CFG CVMX_PKO_PTF_IOBP_CFG_FUNC()
03084 static inline uint64_t CVMX_PKO_PTF_IOBP_CFG_FUNC(void)
03085 {
03086 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
03087 cvmx_warn("CVMX_PKO_PTF_IOBP_CFG not supported on this chip\n");
03088 return CVMX_ADD_IO_SEG(0x0001540000900300ull);
03089 }
03090 #else
03091 #define CVMX_PKO_PTF_IOBP_CFG (CVMX_ADD_IO_SEG(0x0001540000900300ull))
03092 #endif
03093 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03094 static inline uint64_t CVMX_PKO_PTGFX_CFG(unsigned long offset)
03095 {
03096 if (!(
03097 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 4))) ||
03098 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 7))) ||
03099 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 7))) ||
03100 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 4)))))
03101 cvmx_warn("CVMX_PKO_PTGFX_CFG(%lu) is invalid on this chip\n", offset);
03102 return CVMX_ADD_IO_SEG(0x0001540000900200ull) + ((offset) & 7) * 8;
03103 }
03104 #else
03105 #define CVMX_PKO_PTGFX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001540000900200ull) + ((offset) & 7) * 8)
03106 #endif
03107 #define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
03108 #define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
03109 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03110 static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset)
03111 {
03112 if (!(
03113 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
03114 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
03115 cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset);
03116 return CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8;
03117 }
03118 #else
03119 #define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
03120 #endif
03121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03122 #define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC()
03123 static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void)
03124 {
03125 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
03126 cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n");
03127 return CVMX_ADD_IO_SEG(0x0001180050000020ull);
03128 }
03129 #else
03130 #define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
03131 #endif
03132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03133 static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
03134 {
03135 if (!(
03136 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
03137 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
03138 cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset);
03139 return CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8;
03140 }
03141 #else
03142 #define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
03143 #endif
03144 #define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
03145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03146 #define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
03147 static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
03148 {
03149 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03150 cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
03151 return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
03152 }
03153 #else
03154 #define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
03155 #endif
03156 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03157 #define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
03158 static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
03159 {
03160 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03161 cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
03162 return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
03163 }
03164 #else
03165 #define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
03166 #endif
03167 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03168 #define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
03169 static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
03170 {
03171 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03172 cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
03173 return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
03174 }
03175 #else
03176 #define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
03177 #endif
03178 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03179 #define CVMX_PKO_REG_DEBUG4 CVMX_PKO_REG_DEBUG4_FUNC()
03180 static inline uint64_t CVMX_PKO_REG_DEBUG4_FUNC(void)
03181 {
03182 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
03183 cvmx_warn("CVMX_PKO_REG_DEBUG4 not supported on this chip\n");
03184 return CVMX_ADD_IO_SEG(0x00011800500000B8ull);
03185 }
03186 #else
03187 #define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull))
03188 #endif
03189 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03190 #define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
03191 static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
03192 {
03193 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03194 cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
03195 return CVMX_ADD_IO_SEG(0x0001180050000050ull);
03196 }
03197 #else
03198 #define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
03199 #endif
03200 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03201 #define CVMX_PKO_REG_ENGINE_INFLIGHT1 CVMX_PKO_REG_ENGINE_INFLIGHT1_FUNC()
03202 static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT1_FUNC(void)
03203 {
03204 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
03205 cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT1 not supported on this chip\n");
03206 return CVMX_ADD_IO_SEG(0x0001180050000318ull);
03207 }
03208 #else
03209 #define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull))
03210 #endif
03211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03212 static inline uint64_t CVMX_PKO_REG_ENGINE_STORAGEX(unsigned long offset)
03213 {
03214 if (!(
03215 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
03216 cvmx_warn("CVMX_PKO_REG_ENGINE_STORAGEX(%lu) is invalid on this chip\n", offset);
03217 return CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8;
03218 }
03219 #else
03220 #define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8)
03221 #endif
03222 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03223 #define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
03224 static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
03225 {
03226 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03227 cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
03228 return CVMX_ADD_IO_SEG(0x0001180050000058ull);
03229 }
03230 #else
03231 #define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
03232 #endif
03233 #define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
03234 #define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
03235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03236 #define CVMX_PKO_REG_GMX_PORT_MODE CVMX_PKO_REG_GMX_PORT_MODE_FUNC()
03237 static inline uint64_t CVMX_PKO_REG_GMX_PORT_MODE_FUNC(void)
03238 {
03239 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03240 cvmx_warn("CVMX_PKO_REG_GMX_PORT_MODE not supported on this chip\n");
03241 return CVMX_ADD_IO_SEG(0x0001180050000018ull);
03242 }
03243 #else
03244 #define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
03245 #endif
03246 #define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
03247 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03248 #define CVMX_PKO_REG_LOOPBACK_BPID CVMX_PKO_REG_LOOPBACK_BPID_FUNC()
03249 static inline uint64_t CVMX_PKO_REG_LOOPBACK_BPID_FUNC(void)
03250 {
03251 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
03252 cvmx_warn("CVMX_PKO_REG_LOOPBACK_BPID not supported on this chip\n");
03253 return CVMX_ADD_IO_SEG(0x0001180050000118ull);
03254 }
03255 #else
03256 #define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull))
03257 #endif
03258 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03259 #define CVMX_PKO_REG_LOOPBACK_PKIND CVMX_PKO_REG_LOOPBACK_PKIND_FUNC()
03260 static inline uint64_t CVMX_PKO_REG_LOOPBACK_PKIND_FUNC(void)
03261 {
03262 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
03263 cvmx_warn("CVMX_PKO_REG_LOOPBACK_PKIND not supported on this chip\n");
03264 return CVMX_ADD_IO_SEG(0x0001180050000068ull);
03265 }
03266 #else
03267 #define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull))
03268 #endif
03269 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03270 #define CVMX_PKO_REG_MIN_PKT CVMX_PKO_REG_MIN_PKT_FUNC()
03271 static inline uint64_t CVMX_PKO_REG_MIN_PKT_FUNC(void)
03272 {
03273 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
03274 cvmx_warn("CVMX_PKO_REG_MIN_PKT not supported on this chip\n");
03275 return CVMX_ADD_IO_SEG(0x0001180050000070ull);
03276 }
03277 #else
03278 #define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull))
03279 #endif
03280 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03281 #define CVMX_PKO_REG_PREEMPT CVMX_PKO_REG_PREEMPT_FUNC()
03282 static inline uint64_t CVMX_PKO_REG_PREEMPT_FUNC(void)
03283 {
03284 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03285 cvmx_warn("CVMX_PKO_REG_PREEMPT not supported on this chip\n");
03286 return CVMX_ADD_IO_SEG(0x0001180050000110ull);
03287 }
03288 #else
03289 #define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull))
03290 #endif
03291 #define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
03292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03293 #define CVMX_PKO_REG_QUEUE_PREEMPT CVMX_PKO_REG_QUEUE_PREEMPT_FUNC()
03294 static inline uint64_t CVMX_PKO_REG_QUEUE_PREEMPT_FUNC(void)
03295 {
03296 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03297 cvmx_warn("CVMX_PKO_REG_QUEUE_PREEMPT not supported on this chip\n");
03298 return CVMX_ADD_IO_SEG(0x0001180050000108ull);
03299 }
03300 #else
03301 #define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull))
03302 #endif
03303 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03304 #define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
03305 static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
03306 {
03307 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03308 cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
03309 return CVMX_ADD_IO_SEG(0x0001180050000100ull);
03310 }
03311 #else
03312 #define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
03313 #endif
03314 #define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
03315 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03316 #define CVMX_PKO_REG_THROTTLE CVMX_PKO_REG_THROTTLE_FUNC()
03317 static inline uint64_t CVMX_PKO_REG_THROTTLE_FUNC(void)
03318 {
03319 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
03320 cvmx_warn("CVMX_PKO_REG_THROTTLE not supported on this chip\n");
03321 return CVMX_ADD_IO_SEG(0x0001180050000078ull);
03322 }
03323 #else
03324 #define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull))
03325 #endif
03326 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03327 #define CVMX_PKO_REG_TIMESTAMP CVMX_PKO_REG_TIMESTAMP_FUNC()
03328 static inline uint64_t CVMX_PKO_REG_TIMESTAMP_FUNC(void)
03329 {
03330 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CN70XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
03331 cvmx_warn("CVMX_PKO_REG_TIMESTAMP not supported on this chip\n");
03332 return CVMX_ADD_IO_SEG(0x0001180050000060ull);
03333 }
03334 #else
03335 #define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
03336 #endif
03337 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03338 #define CVMX_PKO_SHAPER_CFG CVMX_PKO_SHAPER_CFG_FUNC()
03339 static inline uint64_t CVMX_PKO_SHAPER_CFG_FUNC(void)
03340 {
03341 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
03342 cvmx_warn("CVMX_PKO_SHAPER_CFG not supported on this chip\n");
03343 return CVMX_ADD_IO_SEG(0x00015400000800F8ull);
03344 }
03345 #else
03346 #define CVMX_PKO_SHAPER_CFG (CVMX_ADD_IO_SEG(0x00015400000800F8ull))
03347 #endif
03348 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03349 static inline uint64_t CVMX_PKO_STATE_UID_IN_USEX_RD(unsigned long offset)
03350 {
03351 if (!(
03352 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 1))) ||
03353 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 2))) ||
03354 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 2))) ||
03355 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 1)))))
03356 cvmx_warn("CVMX_PKO_STATE_UID_IN_USEX_RD(%lu) is invalid on this chip\n", offset);
03357 return CVMX_ADD_IO_SEG(0x0001540000900F00ull) + ((offset) & 3) * 8;
03358 }
03359 #else
03360 #define CVMX_PKO_STATE_UID_IN_USEX_RD(offset) (CVMX_ADD_IO_SEG(0x0001540000900F00ull) + ((offset) & 3) * 8)
03361 #endif
03362 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03363 #define CVMX_PKO_STATUS CVMX_PKO_STATUS_FUNC()
03364 static inline uint64_t CVMX_PKO_STATUS_FUNC(void)
03365 {
03366 if (!(OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CNF75XX)))
03367 cvmx_warn("CVMX_PKO_STATUS not supported on this chip\n");
03368 return CVMX_ADD_IO_SEG(0x0001540000D00000ull);
03369 }
03370 #else
03371 #define CVMX_PKO_STATUS (CVMX_ADD_IO_SEG(0x0001540000D00000ull))
03372 #endif
03373 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
03374 static inline uint64_t CVMX_PKO_TXFX_PKT_CNT_RD(unsigned long offset)
03375 {
03376 if (!(
03377 (OCTEON_IS_MODEL(OCTEON_CN73XX) && ((offset <= 15))) ||
03378 (OCTEON_IS_MODEL(OCTEON_CN78XX) && ((offset <= 27))) ||
03379 (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X) && ((offset <= 27))) ||
03380 (OCTEON_IS_MODEL(OCTEON_CNF75XX) && ((offset <= 15)))))
03381 cvmx_warn("CVMX_PKO_TXFX_PKT_CNT_RD(%lu) is invalid on this chip\n", offset);
03382 return CVMX_ADD_IO_SEG(0x0001540000900E00ull) + ((offset) & 31) * 8;
03383 }
03384 #else
03385 #define CVMX_PKO_TXFX_PKT_CNT_RD(offset) (CVMX_ADD_IO_SEG(0x0001540000900E00ull) + ((offset) & 31) * 8)
03386 #endif
03387
03388
03389
03390
03391 union cvmx_pko_channel_level {
03392 uint64_t u64;
03393 struct cvmx_pko_channel_level_s {
03394 #ifdef __BIG_ENDIAN_BITFIELD
03395 uint64_t reserved_1_63 : 63;
03396 uint64_t cc_level : 1;
03397
03398
03399
03400
03401 #else
03402 uint64_t cc_level : 1;
03403 uint64_t reserved_1_63 : 63;
03404 #endif
03405 } s;
03406 struct cvmx_pko_channel_level_s cn73xx;
03407 struct cvmx_pko_channel_level_s cn78xx;
03408 struct cvmx_pko_channel_level_s cn78xxp1;
03409 struct cvmx_pko_channel_level_s cnf75xx;
03410 };
03411 typedef union cvmx_pko_channel_level cvmx_pko_channel_level_t;
03412
03413
03414
03415
03416 union cvmx_pko_dpfi_ena {
03417 uint64_t u64;
03418 struct cvmx_pko_dpfi_ena_s {
03419 #ifdef __BIG_ENDIAN_BITFIELD
03420 uint64_t reserved_1_63 : 63;
03421 uint64_t enable : 1;
03422
03423
03424 #else
03425 uint64_t enable : 1;
03426 uint64_t reserved_1_63 : 63;
03427 #endif
03428 } s;
03429 struct cvmx_pko_dpfi_ena_s cn73xx;
03430 struct cvmx_pko_dpfi_ena_s cn78xx;
03431 struct cvmx_pko_dpfi_ena_s cn78xxp1;
03432 struct cvmx_pko_dpfi_ena_s cnf75xx;
03433 };
03434 typedef union cvmx_pko_dpfi_ena cvmx_pko_dpfi_ena_t;
03435
03436
03437
03438
03439 union cvmx_pko_dpfi_flush {
03440 uint64_t u64;
03441 struct cvmx_pko_dpfi_flush_s {
03442 #ifdef __BIG_ENDIAN_BITFIELD
03443 uint64_t reserved_1_63 : 63;
03444 uint64_t flush_en : 1;
03445
03446
03447
03448
03449 #else
03450 uint64_t flush_en : 1;
03451 uint64_t reserved_1_63 : 63;
03452 #endif
03453 } s;
03454 struct cvmx_pko_dpfi_flush_s cn73xx;
03455 struct cvmx_pko_dpfi_flush_s cn78xx;
03456 struct cvmx_pko_dpfi_flush_s cn78xxp1;
03457 struct cvmx_pko_dpfi_flush_s cnf75xx;
03458 };
03459 typedef union cvmx_pko_dpfi_flush cvmx_pko_dpfi_flush_t;
03460
03461
03462
03463
03464 union cvmx_pko_dpfi_fpa_aura {
03465 uint64_t u64;
03466 struct cvmx_pko_dpfi_fpa_aura_s {
03467 #ifdef __BIG_ENDIAN_BITFIELD
03468 uint64_t reserved_12_63 : 52;
03469 uint64_t node : 2;
03470 uint64_t laura : 10;
03471
03472
03473 #else
03474 uint64_t laura : 10;
03475 uint64_t node : 2;
03476 uint64_t reserved_12_63 : 52;
03477 #endif
03478 } s;
03479 struct cvmx_pko_dpfi_fpa_aura_s cn73xx;
03480 struct cvmx_pko_dpfi_fpa_aura_s cn78xx;
03481 struct cvmx_pko_dpfi_fpa_aura_s cn78xxp1;
03482 struct cvmx_pko_dpfi_fpa_aura_s cnf75xx;
03483 };
03484 typedef union cvmx_pko_dpfi_fpa_aura cvmx_pko_dpfi_fpa_aura_t;
03485
03486
03487
03488
03489 union cvmx_pko_dpfi_status {
03490 uint64_t u64;
03491 struct cvmx_pko_dpfi_status_s {
03492 #ifdef __BIG_ENDIAN_BITFIELD
03493 uint64_t ptr_cnt : 32;
03494
03495 uint64_t reserved_27_31 : 5;
03496 uint64_t xpd_fif_cnt : 4;
03497
03498
03499
03500 uint64_t dalc_fif_cnt : 4;
03501
03502
03503
03504
03505
03506
03507
03508
03509
03510 uint64_t alc_fif_cnt : 5;
03511
03512
03513
03514
03515
03516
03517
03518
03519
03520
03521
03522
03523 uint64_t reserved_13_13 : 1;
03524 uint64_t isrd_ptr1_rtn_full : 1;
03525 uint64_t isrd_ptr0_rtn_full : 1;
03526 uint64_t isrm_ptr1_rtn_full : 1;
03527 uint64_t isrm_ptr0_rtn_full : 1;
03528 uint64_t isrd_ptr1_val : 1;
03529 uint64_t isrd_ptr0_val : 1;
03530 uint64_t isrm_ptr1_val : 1;
03531 uint64_t isrm_ptr0_val : 1;
03532 uint64_t ptr_req_pend : 1;
03533 uint64_t ptr_rtn_pend : 1;
03534 uint64_t fpa_empty : 1;
03535
03536
03537 uint64_t dpfi_empty : 1;
03538 uint64_t cache_flushed : 1;
03539
03540
03541
03542 #else
03543 uint64_t cache_flushed : 1;
03544 uint64_t dpfi_empty : 1;
03545 uint64_t fpa_empty : 1;
03546 uint64_t ptr_rtn_pend : 1;
03547 uint64_t ptr_req_pend : 1;
03548 uint64_t isrm_ptr0_val : 1;
03549 uint64_t isrm_ptr1_val : 1;
03550 uint64_t isrd_ptr0_val : 1;
03551 uint64_t isrd_ptr1_val : 1;
03552 uint64_t isrm_ptr0_rtn_full : 1;
03553 uint64_t isrm_ptr1_rtn_full : 1;
03554 uint64_t isrd_ptr0_rtn_full : 1;
03555 uint64_t isrd_ptr1_rtn_full : 1;
03556 uint64_t reserved_13_13 : 1;
03557 uint64_t alc_fif_cnt : 5;
03558 uint64_t dalc_fif_cnt : 4;
03559 uint64_t xpd_fif_cnt : 4;
03560 uint64_t reserved_27_31 : 5;
03561 uint64_t ptr_cnt : 32;
03562 #endif
03563 } s;
03564 struct cvmx_pko_dpfi_status_s cn73xx;
03565 struct cvmx_pko_dpfi_status_s cn78xx;
03566 struct cvmx_pko_dpfi_status_cn78xxp1 {
03567 #ifdef __BIG_ENDIAN_BITFIELD
03568 uint64_t ptr_cnt : 32;
03569
03570 uint64_t reserved_13_31 : 19;
03571 uint64_t isrd_ptr1_rtn_full : 1;
03572 uint64_t isrd_ptr0_rtn_full : 1;
03573 uint64_t isrm_ptr1_rtn_full : 1;
03574 uint64_t isrm_ptr0_rtn_full : 1;
03575 uint64_t isrd_ptr1_val : 1;
03576 uint64_t isrd_ptr0_val : 1;
03577 uint64_t isrm_ptr1_val : 1;
03578 uint64_t isrm_ptr0_val : 1;
03579 uint64_t ptr_req_pend : 1;
03580 uint64_t ptr_rtn_pend : 1;
03581 uint64_t fpa_empty : 1;
03582
03583
03584 uint64_t dpfi_empty : 1;
03585 uint64_t cache_flushed : 1;
03586
03587
03588
03589 #else
03590 uint64_t cache_flushed : 1;
03591 uint64_t dpfi_empty : 1;
03592 uint64_t fpa_empty : 1;
03593 uint64_t ptr_rtn_pend : 1;
03594 uint64_t ptr_req_pend : 1;
03595 uint64_t isrm_ptr0_val : 1;
03596 uint64_t isrm_ptr1_val : 1;
03597 uint64_t isrd_ptr0_val : 1;
03598 uint64_t isrd_ptr1_val : 1;
03599 uint64_t isrm_ptr0_rtn_full : 1;
03600 uint64_t isrm_ptr1_rtn_full : 1;
03601 uint64_t isrd_ptr0_rtn_full : 1;
03602 uint64_t isrd_ptr1_rtn_full : 1;
03603 uint64_t reserved_13_31 : 19;
03604 uint64_t ptr_cnt : 32;
03605 #endif
03606 } cn78xxp1;
03607 struct cvmx_pko_dpfi_status_s cnf75xx;
03608 };
03609 typedef union cvmx_pko_dpfi_status cvmx_pko_dpfi_status_t;
03610
03611
03612
03613
03614
03615
03616
03617 union cvmx_pko_dqx_bytes {
03618 uint64_t u64;
03619 struct cvmx_pko_dqx_bytes_s {
03620 #ifdef __BIG_ENDIAN_BITFIELD
03621 uint64_t reserved_48_63 : 16;
03622 uint64_t count : 48;
03623 #else
03624 uint64_t count : 48;
03625 uint64_t reserved_48_63 : 16;
03626 #endif
03627 } s;
03628 struct cvmx_pko_dqx_bytes_s cn73xx;
03629 struct cvmx_pko_dqx_bytes_s cn78xx;
03630 struct cvmx_pko_dqx_bytes_s cn78xxp1;
03631 struct cvmx_pko_dqx_bytes_s cnf75xx;
03632 };
03633 typedef union cvmx_pko_dqx_bytes cvmx_pko_dqx_bytes_t;
03634
03635
03636
03637
03638
03639
03640
03641 union cvmx_pko_dqx_cir {
03642 uint64_t u64;
03643 struct cvmx_pko_dqx_cir_s {
03644 #ifdef __BIG_ENDIAN_BITFIELD
03645 uint64_t reserved_41_63 : 23;
03646 uint64_t burst_exponent : 4;
03647
03648
03649 uint64_t burst_mantissa : 8;
03650
03651
03652 uint64_t reserved_17_28 : 12;
03653 uint64_t rate_divider_exponent : 4;
03654
03655
03656
03657
03658
03659
03660
03661
03662
03663
03664
03665
03666
03667 uint64_t rate_exponent : 4;
03668
03669
03670 uint64_t rate_mantissa : 8;
03671 uint64_t enable : 1;
03672 #else
03673 uint64_t enable : 1;
03674 uint64_t rate_mantissa : 8;
03675 uint64_t rate_exponent : 4;
03676 uint64_t rate_divider_exponent : 4;
03677 uint64_t reserved_17_28 : 12;
03678 uint64_t burst_mantissa : 8;
03679 uint64_t burst_exponent : 4;
03680 uint64_t reserved_41_63 : 23;
03681 #endif
03682 } s;
03683 struct cvmx_pko_dqx_cir_s cn73xx;
03684 struct cvmx_pko_dqx_cir_s cn78xx;
03685 struct cvmx_pko_dqx_cir_s cn78xxp1;
03686 struct cvmx_pko_dqx_cir_s cnf75xx;
03687 };
03688 typedef union cvmx_pko_dqx_cir cvmx_pko_dqx_cir_t;
03689
03690
03691
03692
03693
03694
03695
03696 union cvmx_pko_dqx_dropped_bytes {
03697 uint64_t u64;
03698 struct cvmx_pko_dqx_dropped_bytes_s {
03699 #ifdef __BIG_ENDIAN_BITFIELD
03700 uint64_t reserved_48_63 : 16;
03701 uint64_t count : 48;
03702 #else
03703 uint64_t count : 48;
03704 uint64_t reserved_48_63 : 16;
03705 #endif
03706 } s;
03707 struct cvmx_pko_dqx_dropped_bytes_s cn73xx;
03708 struct cvmx_pko_dqx_dropped_bytes_s cn78xx;
03709 struct cvmx_pko_dqx_dropped_bytes_s cn78xxp1;
03710 struct cvmx_pko_dqx_dropped_bytes_s cnf75xx;
03711 };
03712 typedef union cvmx_pko_dqx_dropped_bytes cvmx_pko_dqx_dropped_bytes_t;
03713
03714
03715
03716
03717
03718
03719
03720 union cvmx_pko_dqx_dropped_packets {
03721 uint64_t u64;
03722 struct cvmx_pko_dqx_dropped_packets_s {
03723 #ifdef __BIG_ENDIAN_BITFIELD
03724 uint64_t reserved_40_63 : 24;
03725 uint64_t count : 40;
03726 #else
03727 uint64_t count : 40;
03728 uint64_t reserved_40_63 : 24;
03729 #endif
03730 } s;
03731 struct cvmx_pko_dqx_dropped_packets_s cn73xx;
03732 struct cvmx_pko_dqx_dropped_packets_s cn78xx;
03733 struct cvmx_pko_dqx_dropped_packets_s cn78xxp1;
03734 struct cvmx_pko_dqx_dropped_packets_s cnf75xx;
03735 };
03736 typedef union cvmx_pko_dqx_dropped_packets cvmx_pko_dqx_dropped_packets_t;
03737
03738
03739
03740
03741 union cvmx_pko_dqx_fifo {
03742 uint64_t u64;
03743 struct cvmx_pko_dqx_fifo_s {
03744 #ifdef __BIG_ENDIAN_BITFIELD
03745 uint64_t reserved_15_63 : 49;
03746 uint64_t p_con : 1;
03747 uint64_t head : 7;
03748 uint64_t tail : 7;
03749 #else
03750 uint64_t tail : 7;
03751 uint64_t head : 7;
03752 uint64_t p_con : 1;
03753 uint64_t reserved_15_63 : 49;
03754 #endif
03755 } s;
03756 struct cvmx_pko_dqx_fifo_s cn73xx;
03757 struct cvmx_pko_dqx_fifo_s cn78xx;
03758 struct cvmx_pko_dqx_fifo_s cn78xxp1;
03759 struct cvmx_pko_dqx_fifo_s cnf75xx;
03760 };
03761 typedef union cvmx_pko_dqx_fifo cvmx_pko_dqx_fifo_t;
03762
03763
03764
03765
03766
03767
03768
03769 union cvmx_pko_dqx_packets {
03770 uint64_t u64;
03771 struct cvmx_pko_dqx_packets_s {
03772 #ifdef __BIG_ENDIAN_BITFIELD
03773 uint64_t reserved_40_63 : 24;
03774 uint64_t count : 40;
03775 #else
03776 uint64_t count : 40;
03777 uint64_t reserved_40_63 : 24;
03778 #endif
03779 } s;
03780 struct cvmx_pko_dqx_packets_s cn73xx;
03781 struct cvmx_pko_dqx_packets_s cn78xx;
03782 struct cvmx_pko_dqx_packets_s cn78xxp1;
03783 struct cvmx_pko_dqx_packets_s cnf75xx;
03784 };
03785 typedef union cvmx_pko_dqx_packets cvmx_pko_dqx_packets_t;
03786
03787
03788
03789
03790
03791
03792
03793 union cvmx_pko_dqx_pick {
03794 uint64_t u64;
03795 struct cvmx_pko_dqx_pick_s {
03796 #ifdef __BIG_ENDIAN_BITFIELD
03797 uint64_t dq : 10;
03798 uint64_t color : 2;
03799 uint64_t child : 10;
03800
03801
03802 uint64_t bubble : 1;
03803 uint64_t p_con : 1;
03804 uint64_t c_con : 1;
03805 uint64_t uid : 7;
03806 uint64_t jump : 1;
03807
03808 uint64_t fpd : 1;
03809
03810 uint64_t ds : 1;
03811
03812 uint64_t adjust : 9;
03813
03814
03815
03816
03817 uint64_t pir_dis : 1;
03818
03819
03820
03821 uint64_t cir_dis : 1;
03822
03823
03824
03825
03826 uint64_t red_algo_override : 2;
03827
03828
03829
03830 uint64_t length : 16;
03831
03832
03833
03834
03835
03836
03837
03838
03839
03840
03841
03842 #else
03843 uint64_t length : 16;
03844 uint64_t red_algo_override : 2;
03845 uint64_t cir_dis : 1;
03846 uint64_t pir_dis : 1;
03847 uint64_t adjust : 9;
03848 uint64_t ds : 1;
03849 uint64_t fpd : 1;
03850 uint64_t jump : 1;
03851 uint64_t uid : 7;
03852 uint64_t c_con : 1;
03853 uint64_t p_con : 1;
03854 uint64_t bubble : 1;
03855 uint64_t child : 10;
03856 uint64_t color : 2;
03857 uint64_t dq : 10;
03858 #endif
03859 } s;
03860 struct cvmx_pko_dqx_pick_s cn73xx;
03861 struct cvmx_pko_dqx_pick_s cn78xx;
03862 struct cvmx_pko_dqx_pick_s cn78xxp1;
03863 struct cvmx_pko_dqx_pick_s cnf75xx;
03864 };
03865 typedef union cvmx_pko_dqx_pick cvmx_pko_dqx_pick_t;
03866
03867
03868
03869
03870
03871
03872
03873 union cvmx_pko_dqx_pir {
03874 uint64_t u64;
03875 struct cvmx_pko_dqx_pir_s {
03876 #ifdef __BIG_ENDIAN_BITFIELD
03877 uint64_t reserved_41_63 : 23;
03878 uint64_t burst_exponent : 4;
03879
03880
03881 uint64_t burst_mantissa : 8;
03882
03883
03884 uint64_t reserved_17_28 : 12;
03885 uint64_t rate_divider_exponent : 4;
03886
03887
03888
03889
03890
03891
03892
03893
03894
03895
03896
03897
03898
03899 uint64_t rate_exponent : 4;
03900
03901
03902 uint64_t rate_mantissa : 8;
03903 uint64_t enable : 1;
03904 #else
03905 uint64_t enable : 1;
03906 uint64_t rate_mantissa : 8;
03907 uint64_t rate_exponent : 4;
03908 uint64_t rate_divider_exponent : 4;
03909 uint64_t reserved_17_28 : 12;
03910 uint64_t burst_mantissa : 8;
03911 uint64_t burst_exponent : 4;
03912 uint64_t reserved_41_63 : 23;
03913 #endif
03914 } s;
03915 struct cvmx_pko_dqx_pir_s cn73xx;
03916 struct cvmx_pko_dqx_pir_s cn78xx;
03917 struct cvmx_pko_dqx_pir_s cn78xxp1;
03918 struct cvmx_pko_dqx_pir_s cnf75xx;
03919 };
03920 typedef union cvmx_pko_dqx_pir cvmx_pko_dqx_pir_t;
03921
03922
03923
03924
03925
03926
03927
03928 union cvmx_pko_dqx_pointers {
03929 uint64_t u64;
03930 struct cvmx_pko_dqx_pointers_s {
03931 #ifdef __BIG_ENDIAN_BITFIELD
03932 uint64_t reserved_26_63 : 38;
03933 uint64_t prev : 10;
03934 uint64_t reserved_10_15 : 6;
03935 uint64_t next : 10;
03936 #else
03937 uint64_t next : 10;
03938 uint64_t reserved_10_15 : 6;
03939 uint64_t prev : 10;
03940 uint64_t reserved_26_63 : 38;
03941 #endif
03942 } s;
03943 struct cvmx_pko_dqx_pointers_cn73xx {
03944 #ifdef __BIG_ENDIAN_BITFIELD
03945 uint64_t reserved_24_63 : 40;
03946 uint64_t prev : 8;
03947 uint64_t reserved_8_15 : 8;
03948 uint64_t next : 8;
03949 #else
03950 uint64_t next : 8;
03951 uint64_t reserved_8_15 : 8;
03952 uint64_t prev : 8;
03953 uint64_t reserved_24_63 : 40;
03954 #endif
03955 } cn73xx;
03956 struct cvmx_pko_dqx_pointers_s cn78xx;
03957 struct cvmx_pko_dqx_pointers_s cn78xxp1;
03958 struct cvmx_pko_dqx_pointers_cn73xx cnf75xx;
03959 };
03960 typedef union cvmx_pko_dqx_pointers cvmx_pko_dqx_pointers_t;
03961
03962
03963
03964
03965
03966
03967
03968 union cvmx_pko_dqx_sched_state {
03969 uint64_t u64;
03970 struct cvmx_pko_dqx_sched_state_s {
03971 #ifdef __BIG_ENDIAN_BITFIELD
03972 uint64_t reserved_25_63 : 39;
03973 uint64_t rr_count : 25;
03974 #else
03975 uint64_t rr_count : 25;
03976 uint64_t reserved_25_63 : 39;
03977 #endif
03978 } s;
03979 struct cvmx_pko_dqx_sched_state_s cn73xx;
03980 struct cvmx_pko_dqx_sched_state_s cn78xx;
03981 struct cvmx_pko_dqx_sched_state_s cn78xxp1;
03982 struct cvmx_pko_dqx_sched_state_s cnf75xx;
03983 };
03984 typedef union cvmx_pko_dqx_sched_state cvmx_pko_dqx_sched_state_t;
03985
03986
03987
03988
03989
03990
03991
03992 union cvmx_pko_dqx_schedule {
03993 uint64_t u64;
03994 struct cvmx_pko_dqx_schedule_s {
03995 #ifdef __BIG_ENDIAN_BITFIELD
03996 uint64_t reserved_28_63 : 36;
03997 uint64_t prio : 4;
03998
03999
04000
04001
04002
04003 uint64_t rr_quantum : 24;
04004
04005
04006
04007
04008
04009
04010 #else
04011 uint64_t rr_quantum : 24;
04012 uint64_t prio : 4;
04013 uint64_t reserved_28_63 : 36;
04014 #endif
04015 } s;
04016 struct cvmx_pko_dqx_schedule_s cn73xx;
04017 struct cvmx_pko_dqx_schedule_s cn78xx;
04018 struct cvmx_pko_dqx_schedule_s cn78xxp1;
04019 struct cvmx_pko_dqx_schedule_s cnf75xx;
04020 };
04021 typedef union cvmx_pko_dqx_schedule cvmx_pko_dqx_schedule_t;
04022
04023
04024
04025
04026
04027
04028
04029 union cvmx_pko_dqx_shape {
04030 uint64_t u64;
04031 struct cvmx_pko_dqx_shape_s {
04032 #ifdef __BIG_ENDIAN_BITFIELD
04033 uint64_t reserved_27_63 : 37;
04034 uint64_t schedule_list : 2;
04035
04036
04037
04038
04039 uint64_t length_disable : 1;
04040
04041 uint64_t reserved_13_23 : 11;
04042 uint64_t yellow_disable : 1;
04043 uint64_t red_disable : 1;
04044 uint64_t red_algo : 2;
04045 uint64_t adjust : 9;
04046 #else
04047 uint64_t adjust : 9;
04048 uint64_t red_algo : 2;
04049 uint64_t red_disable : 1;
04050 uint64_t yellow_disable : 1;
04051 uint64_t reserved_13_23 : 11;
04052 uint64_t length_disable : 1;
04053 uint64_t schedule_list : 2;
04054 uint64_t reserved_27_63 : 37;
04055 #endif
04056 } s;
04057 struct cvmx_pko_dqx_shape_s cn73xx;
04058 struct cvmx_pko_dqx_shape_cn78xx {
04059 #ifdef __BIG_ENDIAN_BITFIELD
04060 uint64_t reserved_25_63 : 39;
04061 uint64_t length_disable : 1;
04062
04063 uint64_t reserved_13_23 : 11;
04064 uint64_t yellow_disable : 1;
04065 uint64_t red_disable : 1;
04066 uint64_t red_algo : 2;
04067 uint64_t adjust : 9;
04068 #else
04069 uint64_t adjust : 9;
04070 uint64_t red_algo : 2;
04071 uint64_t red_disable : 1;
04072 uint64_t yellow_disable : 1;
04073 uint64_t reserved_13_23 : 11;
04074 uint64_t length_disable : 1;
04075 uint64_t reserved_25_63 : 39;
04076 #endif
04077 } cn78xx;
04078 struct cvmx_pko_dqx_shape_cn78xx cn78xxp1;
04079 struct cvmx_pko_dqx_shape_s cnf75xx;
04080 };
04081 typedef union cvmx_pko_dqx_shape cvmx_pko_dqx_shape_t;
04082
04083
04084
04085
04086
04087
04088
04089 union cvmx_pko_dqx_shape_state {
04090 uint64_t u64;
04091 struct cvmx_pko_dqx_shape_state_s {
04092 #ifdef __BIG_ENDIAN_BITFIELD
04093 uint64_t reserved_60_63 : 4;
04094 uint64_t tw_timestamp : 6;
04095 uint64_t color : 2;
04096
04097
04098
04099
04100 uint64_t pir_accum : 26;
04101 uint64_t cir_accum : 26;
04102 #else
04103 uint64_t cir_accum : 26;
04104 uint64_t pir_accum : 26;
04105 uint64_t color : 2;
04106 uint64_t tw_timestamp : 6;
04107 uint64_t reserved_60_63 : 4;
04108 #endif
04109 } s;
04110 struct cvmx_pko_dqx_shape_state_s cn73xx;
04111 struct cvmx_pko_dqx_shape_state_s cn78xx;
04112 struct cvmx_pko_dqx_shape_state_s cn78xxp1;
04113 struct cvmx_pko_dqx_shape_state_s cnf75xx;
04114 };
04115 typedef union cvmx_pko_dqx_shape_state cvmx_pko_dqx_shape_state_t;
04116
04117
04118
04119
04120
04121
04122
04123 union cvmx_pko_dqx_sw_xoff {
04124 uint64_t u64;
04125 struct cvmx_pko_dqx_sw_xoff_s {
04126 #ifdef __BIG_ENDIAN_BITFIELD
04127 uint64_t reserved_4_63 : 60;
04128 uint64_t drain_irq : 1;
04129
04130
04131 uint64_t drain_null_link : 1;
04132
04133
04134
04135
04136
04137 uint64_t drain : 1;
04138
04139
04140
04141
04142
04143
04144
04145
04146
04147 uint64_t xoff : 1;
04148
04149
04150
04151
04152
04153
04154 #else
04155 uint64_t xoff : 1;
04156 uint64_t drain : 1;
04157 uint64_t drain_null_link : 1;
04158 uint64_t drain_irq : 1;
04159 uint64_t reserved_4_63 : 60;
04160 #endif
04161 } s;
04162 struct cvmx_pko_dqx_sw_xoff_s cn73xx;
04163 struct cvmx_pko_dqx_sw_xoff_s cn78xx;
04164 struct cvmx_pko_dqx_sw_xoff_s cn78xxp1;
04165 struct cvmx_pko_dqx_sw_xoff_s cnf75xx;
04166 };
04167 typedef union cvmx_pko_dqx_sw_xoff cvmx_pko_dqx_sw_xoff_t;
04168
04169
04170
04171
04172 union cvmx_pko_dqx_topology {
04173 uint64_t u64;
04174 struct cvmx_pko_dqx_topology_s {
04175 #ifdef __BIG_ENDIAN_BITFIELD
04176 uint64_t reserved_26_63 : 38;
04177 uint64_t parent : 10;
04178 uint64_t reserved_0_15 : 16;
04179 #else
04180 uint64_t reserved_0_15 : 16;
04181 uint64_t parent : 10;
04182 uint64_t reserved_26_63 : 38;
04183 #endif
04184 } s;
04185 struct cvmx_pko_dqx_topology_cn73xx {
04186 #ifdef __BIG_ENDIAN_BITFIELD
04187 uint64_t reserved_24_63 : 40;
04188 uint64_t parent : 8;
04189 uint64_t reserved_0_15 : 16;
04190 #else
04191 uint64_t reserved_0_15 : 16;
04192 uint64_t parent : 8;
04193 uint64_t reserved_24_63 : 40;
04194 #endif
04195 } cn73xx;
04196 struct cvmx_pko_dqx_topology_s cn78xx;
04197 struct cvmx_pko_dqx_topology_s cn78xxp1;
04198 struct cvmx_pko_dqx_topology_cn73xx cnf75xx;
04199 };
04200 typedef union cvmx_pko_dqx_topology cvmx_pko_dqx_topology_t;
04201
04202
04203
04204
04205 union cvmx_pko_dqx_wm_buf_cnt {
04206 uint64_t u64;
04207 struct cvmx_pko_dqx_wm_buf_cnt_s {
04208 #ifdef __BIG_ENDIAN_BITFIELD
04209 uint64_t reserved_36_63 : 28;
04210 uint64_t count : 36;
04211
04212
04213
04214
04215
04216
04217
04218
04219 #else
04220 uint64_t count : 36;
04221 uint64_t reserved_36_63 : 28;
04222 #endif
04223 } s;
04224 struct cvmx_pko_dqx_wm_buf_cnt_s cn73xx;
04225 struct cvmx_pko_dqx_wm_buf_cnt_s cn78xx;
04226 struct cvmx_pko_dqx_wm_buf_cnt_s cn78xxp1;
04227 struct cvmx_pko_dqx_wm_buf_cnt_s cnf75xx;
04228 };
04229 typedef union cvmx_pko_dqx_wm_buf_cnt cvmx_pko_dqx_wm_buf_cnt_t;
04230
04231
04232
04233
04234 union cvmx_pko_dqx_wm_buf_ctl {
04235 uint64_t u64;
04236 struct cvmx_pko_dqx_wm_buf_ctl_s {
04237 #ifdef __BIG_ENDIAN_BITFIELD
04238 uint64_t reserved_51_63 : 13;
04239 uint64_t enable : 1;
04240
04241 uint64_t reserved_49_49 : 1;
04242 uint64_t intr : 1;
04243
04244
04245 uint64_t reserved_36_47 : 12;
04246 uint64_t threshold : 36;
04247
04248 #else
04249 uint64_t threshold : 36;
04250 uint64_t reserved_36_47 : 12;
04251 uint64_t intr : 1;
04252 uint64_t reserved_49_49 : 1;
04253 uint64_t enable : 1;
04254 uint64_t reserved_51_63 : 13;
04255 #endif
04256 } s;
04257 struct cvmx_pko_dqx_wm_buf_ctl_s cn73xx;
04258 struct cvmx_pko_dqx_wm_buf_ctl_s cn78xx;
04259 struct cvmx_pko_dqx_wm_buf_ctl_s cn78xxp1;
04260 struct cvmx_pko_dqx_wm_buf_ctl_s cnf75xx;
04261 };
04262 typedef union cvmx_pko_dqx_wm_buf_ctl cvmx_pko_dqx_wm_buf_ctl_t;
04263
04264
04265
04266
04267 union cvmx_pko_dqx_wm_buf_ctl_w1c {
04268 uint64_t u64;
04269 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s {
04270 #ifdef __BIG_ENDIAN_BITFIELD
04271 uint64_t reserved_49_63 : 15;
04272 uint64_t intr : 1;
04273
04274 uint64_t reserved_0_47 : 48;
04275 #else
04276 uint64_t reserved_0_47 : 48;
04277 uint64_t intr : 1;
04278 uint64_t reserved_49_63 : 15;
04279 #endif
04280 } s;
04281 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn73xx;
04282 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn78xx;
04283 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn78xxp1;
04284 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cnf75xx;
04285 };
04286 typedef union cvmx_pko_dqx_wm_buf_ctl_w1c cvmx_pko_dqx_wm_buf_ctl_w1c_t;
04287
04288
04289
04290
04291 union cvmx_pko_dqx_wm_cnt {
04292 uint64_t u64;
04293 struct cvmx_pko_dqx_wm_cnt_s {
04294 #ifdef __BIG_ENDIAN_BITFIELD
04295 uint64_t reserved_48_63 : 16;
04296 uint64_t count : 48;
04297
04298
04299
04300
04301
04302
04303 #else
04304 uint64_t count : 48;
04305 uint64_t reserved_48_63 : 16;
04306 #endif
04307 } s;
04308 struct cvmx_pko_dqx_wm_cnt_s cn73xx;
04309 struct cvmx_pko_dqx_wm_cnt_s cn78xx;
04310 struct cvmx_pko_dqx_wm_cnt_s cn78xxp1;
04311 struct cvmx_pko_dqx_wm_cnt_s cnf75xx;
04312 };
04313 typedef union cvmx_pko_dqx_wm_cnt cvmx_pko_dqx_wm_cnt_t;
04314
04315
04316
04317
04318 union cvmx_pko_dqx_wm_ctl {
04319 uint64_t u64;
04320 struct cvmx_pko_dqx_wm_ctl_s {
04321 #ifdef __BIG_ENDIAN_BITFIELD
04322 uint64_t reserved_52_63 : 12;
04323 uint64_t ncb_query_rsp : 1;
04324
04325
04326
04327 uint64_t enable : 1;
04328 uint64_t kind : 1;
04329
04330
04331
04332
04333 uint64_t intr : 1;
04334 uint64_t threshold : 48;
04335 #else
04336 uint64_t threshold : 48;
04337 uint64_t intr : 1;
04338 uint64_t kind : 1;
04339 uint64_t enable : 1;
04340 uint64_t ncb_query_rsp : 1;
04341 uint64_t reserved_52_63 : 12;
04342 #endif
04343 } s;
04344 struct cvmx_pko_dqx_wm_ctl_s cn73xx;
04345 struct cvmx_pko_dqx_wm_ctl_s cn78xx;
04346 struct cvmx_pko_dqx_wm_ctl_s cn78xxp1;
04347 struct cvmx_pko_dqx_wm_ctl_s cnf75xx;
04348 };
04349 typedef union cvmx_pko_dqx_wm_ctl cvmx_pko_dqx_wm_ctl_t;
04350
04351
04352
04353
04354 union cvmx_pko_dqx_wm_ctl_w1c {
04355 uint64_t u64;
04356 struct cvmx_pko_dqx_wm_ctl_w1c_s {
04357 #ifdef __BIG_ENDIAN_BITFIELD
04358 uint64_t reserved_49_63 : 15;
04359 uint64_t intr : 1;
04360 uint64_t reserved_0_47 : 48;
04361 #else
04362 uint64_t reserved_0_47 : 48;
04363 uint64_t intr : 1;
04364 uint64_t reserved_49_63 : 15;
04365 #endif
04366 } s;
04367 struct cvmx_pko_dqx_wm_ctl_w1c_s cn73xx;
04368 struct cvmx_pko_dqx_wm_ctl_w1c_s cn78xx;
04369 struct cvmx_pko_dqx_wm_ctl_w1c_s cn78xxp1;
04370 struct cvmx_pko_dqx_wm_ctl_w1c_s cnf75xx;
04371 };
04372 typedef union cvmx_pko_dqx_wm_ctl_w1c cvmx_pko_dqx_wm_ctl_w1c_t;
04373
04374
04375
04376
04377 union cvmx_pko_dq_csr_bus_debug {
04378 uint64_t u64;
04379 struct cvmx_pko_dq_csr_bus_debug_s {
04380 #ifdef __BIG_ENDIAN_BITFIELD
04381 uint64_t csr_bus_debug : 64;
04382 #else
04383 uint64_t csr_bus_debug : 64;
04384 #endif
04385 } s;
04386 struct cvmx_pko_dq_csr_bus_debug_s cn73xx;
04387 struct cvmx_pko_dq_csr_bus_debug_s cn78xx;
04388 struct cvmx_pko_dq_csr_bus_debug_s cn78xxp1;
04389 struct cvmx_pko_dq_csr_bus_debug_s cnf75xx;
04390 };
04391 typedef union cvmx_pko_dq_csr_bus_debug cvmx_pko_dq_csr_bus_debug_t;
04392
04393
04394
04395
04396 union cvmx_pko_dq_debug {
04397 uint64_t u64;
04398 struct cvmx_pko_dq_debug_s {
04399 #ifdef __BIG_ENDIAN_BITFIELD
04400 uint64_t dbg_vec : 64;
04401 #else
04402 uint64_t dbg_vec : 64;
04403 #endif
04404 } s;
04405 struct cvmx_pko_dq_debug_s cn73xx;
04406 struct cvmx_pko_dq_debug_s cn78xx;
04407 struct cvmx_pko_dq_debug_s cn78xxp1;
04408 struct cvmx_pko_dq_debug_s cnf75xx;
04409 };
04410 typedef union cvmx_pko_dq_debug cvmx_pko_dq_debug_t;
04411
04412
04413
04414
04415 union cvmx_pko_drain_irq {
04416 uint64_t u64;
04417 struct cvmx_pko_drain_irq_s {
04418 #ifdef __BIG_ENDIAN_BITFIELD
04419 uint64_t reserved_1_63 : 63;
04420 uint64_t intr : 1;
04421
04422
04423
04424 #else
04425 uint64_t intr : 1;
04426 uint64_t reserved_1_63 : 63;
04427 #endif
04428 } s;
04429 struct cvmx_pko_drain_irq_s cn73xx;
04430 struct cvmx_pko_drain_irq_s cn78xx;
04431 struct cvmx_pko_drain_irq_s cn78xxp1;
04432 struct cvmx_pko_drain_irq_s cnf75xx;
04433 };
04434 typedef union cvmx_pko_drain_irq cvmx_pko_drain_irq_t;
04435
04436
04437
04438
04439 union cvmx_pko_enable {
04440 uint64_t u64;
04441 struct cvmx_pko_enable_s {
04442 #ifdef __BIG_ENDIAN_BITFIELD
04443 uint64_t reserved_1_63 : 63;
04444 uint64_t enable : 1;
04445 #else
04446 uint64_t enable : 1;
04447 uint64_t reserved_1_63 : 63;
04448 #endif
04449 } s;
04450 struct cvmx_pko_enable_s cn73xx;
04451 struct cvmx_pko_enable_s cn78xx;
04452 struct cvmx_pko_enable_s cn78xxp1;
04453 struct cvmx_pko_enable_s cnf75xx;
04454 };
04455 typedef union cvmx_pko_enable cvmx_pko_enable_t;
04456
04457
04458
04459
04460
04461
04462
04463
04464
04465
04466
04467
04468
04469
04470
04471
04472
04473
04474
04475
04476
04477
04478
04479
04480 union cvmx_pko_formatx_ctl {
04481 uint64_t u64;
04482 struct cvmx_pko_formatx_ctl_s {
04483 #ifdef __BIG_ENDIAN_BITFIELD
04484 uint64_t reserved_27_63 : 37;
04485 uint64_t offset : 11;
04486
04487
04488 uint64_t y_mask : 4;
04489
04490 uint64_t y_val : 4;
04491
04492 uint64_t r_mask : 4;
04493
04494 uint64_t r_val : 4;
04495
04496 #else
04497 uint64_t r_val : 4;
04498 uint64_t r_mask : 4;
04499 uint64_t y_val : 4;
04500 uint64_t y_mask : 4;
04501 uint64_t offset : 11;
04502 uint64_t reserved_27_63 : 37;
04503 #endif
04504 } s;
04505 struct cvmx_pko_formatx_ctl_s cn73xx;
04506 struct cvmx_pko_formatx_ctl_s cn78xx;
04507 struct cvmx_pko_formatx_ctl_s cn78xxp1;
04508 struct cvmx_pko_formatx_ctl_s cnf75xx;
04509 };
04510 typedef union cvmx_pko_formatx_ctl cvmx_pko_formatx_ctl_t;
04511
04512
04513
04514
04515 union cvmx_pko_l1_sqx_cir {
04516 uint64_t u64;
04517 struct cvmx_pko_l1_sqx_cir_s {
04518 #ifdef __BIG_ENDIAN_BITFIELD
04519 uint64_t reserved_41_63 : 23;
04520 uint64_t burst_exponent : 4;
04521
04522
04523 uint64_t burst_mantissa : 8;
04524
04525
04526 uint64_t reserved_17_28 : 12;
04527 uint64_t rate_divider_exponent : 4;
04528
04529
04530
04531
04532
04533
04534
04535
04536
04537
04538
04539
04540
04541 uint64_t rate_exponent : 4;
04542
04543
04544 uint64_t rate_mantissa : 8;
04545 uint64_t enable : 1;
04546 #else
04547 uint64_t enable : 1;
04548 uint64_t rate_mantissa : 8;
04549 uint64_t rate_exponent : 4;
04550 uint64_t rate_divider_exponent : 4;
04551 uint64_t reserved_17_28 : 12;
04552 uint64_t burst_mantissa : 8;
04553 uint64_t burst_exponent : 4;
04554 uint64_t reserved_41_63 : 23;
04555 #endif
04556 } s;
04557 struct cvmx_pko_l1_sqx_cir_s cn73xx;
04558 struct cvmx_pko_l1_sqx_cir_s cn78xx;
04559 struct cvmx_pko_l1_sqx_cir_s cn78xxp1;
04560 struct cvmx_pko_l1_sqx_cir_s cnf75xx;
04561 };
04562 typedef union cvmx_pko_l1_sqx_cir cvmx_pko_l1_sqx_cir_t;
04563
04564
04565
04566
04567
04568
04569
04570 union cvmx_pko_l1_sqx_dropped_bytes {
04571 uint64_t u64;
04572 struct cvmx_pko_l1_sqx_dropped_bytes_s {
04573 #ifdef __BIG_ENDIAN_BITFIELD
04574 uint64_t reserved_48_63 : 16;
04575 uint64_t count : 48;
04576 #else
04577 uint64_t count : 48;
04578 uint64_t reserved_48_63 : 16;
04579 #endif
04580 } s;
04581 struct cvmx_pko_l1_sqx_dropped_bytes_s cn73xx;
04582 struct cvmx_pko_l1_sqx_dropped_bytes_s cn78xx;
04583 struct cvmx_pko_l1_sqx_dropped_bytes_s cn78xxp1;
04584 struct cvmx_pko_l1_sqx_dropped_bytes_s cnf75xx;
04585 };
04586 typedef union cvmx_pko_l1_sqx_dropped_bytes cvmx_pko_l1_sqx_dropped_bytes_t;
04587
04588
04589
04590
04591
04592
04593
04594 union cvmx_pko_l1_sqx_dropped_packets {
04595 uint64_t u64;
04596 struct cvmx_pko_l1_sqx_dropped_packets_s {
04597 #ifdef __BIG_ENDIAN_BITFIELD
04598 uint64_t reserved_40_63 : 24;
04599 uint64_t count : 40;
04600 #else
04601 uint64_t count : 40;
04602 uint64_t reserved_40_63 : 24;
04603 #endif
04604 } s;
04605 struct cvmx_pko_l1_sqx_dropped_packets_s cn73xx;
04606 struct cvmx_pko_l1_sqx_dropped_packets_s cn78xx;
04607 struct cvmx_pko_l1_sqx_dropped_packets_s cn78xxp1;
04608 struct cvmx_pko_l1_sqx_dropped_packets_s cnf75xx;
04609 };
04610 typedef union cvmx_pko_l1_sqx_dropped_packets cvmx_pko_l1_sqx_dropped_packets_t;
04611
04612
04613
04614
04615 union cvmx_pko_l1_sqx_green {
04616 uint64_t u64;
04617 struct cvmx_pko_l1_sqx_green_s {
04618 #ifdef __BIG_ENDIAN_BITFIELD
04619 uint64_t reserved_41_63 : 23;
04620 uint64_t rr_active : 1;
04621
04622 uint64_t active_vec : 20;
04623
04624
04625
04626
04627 uint64_t reserved_19_19 : 1;
04628 uint64_t head : 9;
04629 uint64_t reserved_9_9 : 1;
04630 uint64_t tail : 9;
04631 #else
04632 uint64_t tail : 9;
04633 uint64_t reserved_9_9 : 1;
04634 uint64_t head : 9;
04635 uint64_t reserved_19_19 : 1;
04636 uint64_t active_vec : 20;
04637 uint64_t rr_active : 1;
04638 uint64_t reserved_41_63 : 23;
04639 #endif
04640 } s;
04641 struct cvmx_pko_l1_sqx_green_s cn73xx;
04642 struct cvmx_pko_l1_sqx_green_s cn78xx;
04643 struct cvmx_pko_l1_sqx_green_s cn78xxp1;
04644 struct cvmx_pko_l1_sqx_green_s cnf75xx;
04645 };
04646 typedef union cvmx_pko_l1_sqx_green cvmx_pko_l1_sqx_green_t;
04647
04648
04649
04650
04651 union cvmx_pko_l1_sqx_green_bytes {
04652 uint64_t u64;
04653 struct cvmx_pko_l1_sqx_green_bytes_s {
04654 #ifdef __BIG_ENDIAN_BITFIELD
04655 uint64_t reserved_48_63 : 16;
04656 uint64_t count : 48;
04657 #else
04658 uint64_t count : 48;
04659 uint64_t reserved_48_63 : 16;
04660 #endif
04661 } s;
04662 struct cvmx_pko_l1_sqx_green_bytes_s cn73xx;
04663 struct cvmx_pko_l1_sqx_green_bytes_s cn78xx;
04664 struct cvmx_pko_l1_sqx_green_bytes_s cn78xxp1;
04665 struct cvmx_pko_l1_sqx_green_bytes_s cnf75xx;
04666 };
04667 typedef union cvmx_pko_l1_sqx_green_bytes cvmx_pko_l1_sqx_green_bytes_t;
04668
04669
04670
04671
04672 union cvmx_pko_l1_sqx_green_packets {
04673 uint64_t u64;
04674 struct cvmx_pko_l1_sqx_green_packets_s {
04675 #ifdef __BIG_ENDIAN_BITFIELD
04676 uint64_t reserved_40_63 : 24;
04677 uint64_t count : 40;
04678 #else
04679 uint64_t count : 40;
04680 uint64_t reserved_40_63 : 24;
04681 #endif
04682 } s;
04683 struct cvmx_pko_l1_sqx_green_packets_s cn73xx;
04684 struct cvmx_pko_l1_sqx_green_packets_s cn78xx;
04685 struct cvmx_pko_l1_sqx_green_packets_s cn78xxp1;
04686 struct cvmx_pko_l1_sqx_green_packets_s cnf75xx;
04687 };
04688 typedef union cvmx_pko_l1_sqx_green_packets cvmx_pko_l1_sqx_green_packets_t;
04689
04690
04691
04692
04693 union cvmx_pko_l1_sqx_link {
04694 uint64_t u64;
04695 struct cvmx_pko_l1_sqx_link_s {
04696 #ifdef __BIG_ENDIAN_BITFIELD
04697 uint64_t reserved_49_63 : 15;
04698 uint64_t link : 5;
04699 uint64_t reserved_32_43 : 12;
04700 uint64_t cc_word_cnt : 20;
04701
04702
04703
04704
04705
04706 uint64_t cc_packet_cnt : 10;
04707
04708
04709
04710
04711
04712 uint64_t cc_enable : 1;
04713 uint64_t reserved_0_0 : 1;
04714 #else
04715 uint64_t reserved_0_0 : 1;
04716 uint64_t cc_enable : 1;
04717 uint64_t cc_packet_cnt : 10;
04718 uint64_t cc_word_cnt : 20;
04719 uint64_t reserved_32_43 : 12;
04720 uint64_t link : 5;
04721 uint64_t reserved_49_63 : 15;
04722 #endif
04723 } s;
04724 struct cvmx_pko_l1_sqx_link_cn73xx {
04725 #ifdef __BIG_ENDIAN_BITFIELD
04726 uint64_t reserved_48_63 : 16;
04727 uint64_t link : 4;
04728 uint64_t reserved_32_43 : 12;
04729 uint64_t cc_word_cnt : 20;
04730
04731
04732
04733
04734
04735 uint64_t cc_packet_cnt : 10;
04736
04737
04738
04739
04740
04741 uint64_t cc_enable : 1;
04742 uint64_t reserved_0_0 : 1;
04743 #else
04744 uint64_t reserved_0_0 : 1;
04745 uint64_t cc_enable : 1;
04746 uint64_t cc_packet_cnt : 10;
04747 uint64_t cc_word_cnt : 20;
04748 uint64_t reserved_32_43 : 12;
04749 uint64_t link : 4;
04750 uint64_t reserved_48_63 : 16;
04751 #endif
04752 } cn73xx;
04753 struct cvmx_pko_l1_sqx_link_s cn78xx;
04754 struct cvmx_pko_l1_sqx_link_s cn78xxp1;
04755 struct cvmx_pko_l1_sqx_link_cn73xx cnf75xx;
04756 };
04757 typedef union cvmx_pko_l1_sqx_link cvmx_pko_l1_sqx_link_t;
04758
04759
04760
04761
04762
04763
04764
04765 union cvmx_pko_l1_sqx_pick {
04766 uint64_t u64;
04767 struct cvmx_pko_l1_sqx_pick_s {
04768 #ifdef __BIG_ENDIAN_BITFIELD
04769 uint64_t dq : 10;
04770 uint64_t color : 2;
04771 uint64_t child : 10;
04772
04773
04774 uint64_t bubble : 1;
04775 uint64_t p_con : 1;
04776 uint64_t c_con : 1;
04777 uint64_t uid : 7;
04778 uint64_t jump : 1;
04779
04780 uint64_t fpd : 1;
04781
04782 uint64_t ds : 1;
04783
04784 uint64_t adjust : 9;
04785
04786
04787
04788
04789 uint64_t pir_dis : 1;
04790
04791
04792
04793 uint64_t cir_dis : 1;
04794
04795
04796
04797
04798 uint64_t red_algo_override : 2;
04799
04800
04801
04802 uint64_t length : 16;
04803
04804
04805
04806
04807
04808
04809
04810
04811
04812
04813
04814 #else
04815 uint64_t length : 16;
04816 uint64_t red_algo_override : 2;
04817 uint64_t cir_dis : 1;
04818 uint64_t pir_dis : 1;
04819 uint64_t adjust : 9;
04820 uint64_t ds : 1;
04821 uint64_t fpd : 1;
04822 uint64_t jump : 1;
04823 uint64_t uid : 7;
04824 uint64_t c_con : 1;
04825 uint64_t p_con : 1;
04826 uint64_t bubble : 1;
04827 uint64_t child : 10;
04828 uint64_t color : 2;
04829 uint64_t dq : 10;
04830 #endif
04831 } s;
04832 struct cvmx_pko_l1_sqx_pick_s cn73xx;
04833 struct cvmx_pko_l1_sqx_pick_s cn78xx;
04834 struct cvmx_pko_l1_sqx_pick_s cn78xxp1;
04835 struct cvmx_pko_l1_sqx_pick_s cnf75xx;
04836 };
04837 typedef union cvmx_pko_l1_sqx_pick cvmx_pko_l1_sqx_pick_t;
04838
04839
04840
04841
04842
04843
04844
04845 union cvmx_pko_l1_sqx_red {
04846 uint64_t u64;
04847 struct cvmx_pko_l1_sqx_red_s {
04848 #ifdef __BIG_ENDIAN_BITFIELD
04849 uint64_t reserved_19_63 : 45;
04850 uint64_t head : 9;
04851 uint64_t reserved_9_9 : 1;
04852 uint64_t tail : 9;
04853 #else
04854 uint64_t tail : 9;
04855 uint64_t reserved_9_9 : 1;
04856 uint64_t head : 9;
04857 uint64_t reserved_19_63 : 45;
04858 #endif
04859 } s;
04860 struct cvmx_pko_l1_sqx_red_s cn73xx;
04861 struct cvmx_pko_l1_sqx_red_s cn78xx;
04862 struct cvmx_pko_l1_sqx_red_s cn78xxp1;
04863 struct cvmx_pko_l1_sqx_red_s cnf75xx;
04864 };
04865 typedef union cvmx_pko_l1_sqx_red cvmx_pko_l1_sqx_red_t;
04866
04867
04868
04869
04870
04871
04872
04873 union cvmx_pko_l1_sqx_red_bytes {
04874 uint64_t u64;
04875 struct cvmx_pko_l1_sqx_red_bytes_s {
04876 #ifdef __BIG_ENDIAN_BITFIELD
04877 uint64_t reserved_48_63 : 16;
04878 uint64_t count : 48;
04879 #else
04880 uint64_t count : 48;
04881 uint64_t reserved_48_63 : 16;
04882 #endif
04883 } s;
04884 struct cvmx_pko_l1_sqx_red_bytes_s cn73xx;
04885 struct cvmx_pko_l1_sqx_red_bytes_s cn78xx;
04886 struct cvmx_pko_l1_sqx_red_bytes_s cn78xxp1;
04887 struct cvmx_pko_l1_sqx_red_bytes_s cnf75xx;
04888 };
04889 typedef union cvmx_pko_l1_sqx_red_bytes cvmx_pko_l1_sqx_red_bytes_t;
04890
04891
04892
04893
04894
04895
04896
04897 union cvmx_pko_l1_sqx_red_packets {
04898 uint64_t u64;
04899 struct cvmx_pko_l1_sqx_red_packets_s {
04900 #ifdef __BIG_ENDIAN_BITFIELD
04901 uint64_t reserved_40_63 : 24;
04902 uint64_t count : 40;
04903 #else
04904 uint64_t count : 40;
04905 uint64_t reserved_40_63 : 24;
04906 #endif
04907 } s;
04908 struct cvmx_pko_l1_sqx_red_packets_s cn73xx;
04909 struct cvmx_pko_l1_sqx_red_packets_s cn78xx;
04910 struct cvmx_pko_l1_sqx_red_packets_s cn78xxp1;
04911 struct cvmx_pko_l1_sqx_red_packets_s cnf75xx;
04912 };
04913 typedef union cvmx_pko_l1_sqx_red_packets cvmx_pko_l1_sqx_red_packets_t;
04914
04915
04916
04917
04918 union cvmx_pko_l1_sqx_schedule {
04919 uint64_t u64;
04920 struct cvmx_pko_l1_sqx_schedule_s {
04921 #ifdef __BIG_ENDIAN_BITFIELD
04922 uint64_t dummy : 40;
04923 uint64_t rr_quantum : 24;
04924
04925
04926
04927 #else
04928 uint64_t rr_quantum : 24;
04929 uint64_t dummy : 40;
04930 #endif
04931 } s;
04932 struct cvmx_pko_l1_sqx_schedule_cn73xx {
04933 #ifdef __BIG_ENDIAN_BITFIELD
04934 uint64_t reserved_24_63 : 40;
04935 uint64_t rr_quantum : 24;
04936
04937
04938
04939 #else
04940 uint64_t rr_quantum : 24;
04941 uint64_t reserved_24_63 : 40;
04942 #endif
04943 } cn73xx;
04944 struct cvmx_pko_l1_sqx_schedule_cn73xx cn78xx;
04945 struct cvmx_pko_l1_sqx_schedule_s cn78xxp1;
04946 struct cvmx_pko_l1_sqx_schedule_cn73xx cnf75xx;
04947 };
04948 typedef union cvmx_pko_l1_sqx_schedule cvmx_pko_l1_sqx_schedule_t;
04949
04950
04951
04952
04953 union cvmx_pko_l1_sqx_shape {
04954 uint64_t u64;
04955 struct cvmx_pko_l1_sqx_shape_s {
04956 #ifdef __BIG_ENDIAN_BITFIELD
04957 uint64_t reserved_25_63 : 39;
04958 uint64_t length_disable : 1;
04959
04960 uint64_t reserved_18_23 : 6;
04961 uint64_t link : 5;
04962 uint64_t reserved_9_12 : 4;
04963 uint64_t adjust : 9;
04964
04965
04966
04967 #else
04968 uint64_t adjust : 9;
04969 uint64_t reserved_9_12 : 4;
04970 uint64_t link : 5;
04971 uint64_t reserved_18_23 : 6;
04972 uint64_t length_disable : 1;
04973 uint64_t reserved_25_63 : 39;
04974 #endif
04975 } s;
04976 struct cvmx_pko_l1_sqx_shape_cn73xx {
04977 #ifdef __BIG_ENDIAN_BITFIELD
04978 uint64_t reserved_25_63 : 39;
04979 uint64_t length_disable : 1;
04980
04981 uint64_t reserved_17_23 : 7;
04982 uint64_t link : 4;
04983 uint64_t reserved_9_12 : 4;
04984 uint64_t adjust : 9;
04985
04986
04987
04988 #else
04989 uint64_t adjust : 9;
04990 uint64_t reserved_9_12 : 4;
04991 uint64_t link : 4;
04992 uint64_t reserved_17_23 : 7;
04993 uint64_t length_disable : 1;
04994 uint64_t reserved_25_63 : 39;
04995 #endif
04996 } cn73xx;
04997 struct cvmx_pko_l1_sqx_shape_s cn78xx;
04998 struct cvmx_pko_l1_sqx_shape_s cn78xxp1;
04999 struct cvmx_pko_l1_sqx_shape_cn73xx cnf75xx;
05000 };
05001 typedef union cvmx_pko_l1_sqx_shape cvmx_pko_l1_sqx_shape_t;
05002
05003
05004
05005
05006
05007
05008
05009 union cvmx_pko_l1_sqx_shape_state {
05010 uint64_t u64;
05011 struct cvmx_pko_l1_sqx_shape_state_s {
05012 #ifdef __BIG_ENDIAN_BITFIELD
05013 uint64_t reserved_60_63 : 4;
05014 uint64_t tw_timestamp : 6;
05015 uint64_t color2 : 1;
05016 uint64_t color : 1;
05017
05018
05019 uint64_t reserved_26_51 : 26;
05020 uint64_t cir_accum : 26;
05021 #else
05022 uint64_t cir_accum : 26;
05023 uint64_t reserved_26_51 : 26;
05024 uint64_t color : 1;
05025 uint64_t color2 : 1;
05026 uint64_t tw_timestamp : 6;
05027 uint64_t reserved_60_63 : 4;
05028 #endif
05029 } s;
05030 struct cvmx_pko_l1_sqx_shape_state_cn73xx {
05031 #ifdef __BIG_ENDIAN_BITFIELD
05032 uint64_t reserved_60_63 : 4;
05033 uint64_t tw_timestamp : 6;
05034 uint64_t reserved_53_53 : 1;
05035 uint64_t color : 1;
05036
05037
05038 uint64_t reserved_26_51 : 26;
05039 uint64_t cir_accum : 26;
05040 #else
05041 uint64_t cir_accum : 26;
05042 uint64_t reserved_26_51 : 26;
05043 uint64_t color : 1;
05044 uint64_t reserved_53_53 : 1;
05045 uint64_t tw_timestamp : 6;
05046 uint64_t reserved_60_63 : 4;
05047 #endif
05048 } cn73xx;
05049 struct cvmx_pko_l1_sqx_shape_state_cn73xx cn78xx;
05050 struct cvmx_pko_l1_sqx_shape_state_s cn78xxp1;
05051 struct cvmx_pko_l1_sqx_shape_state_cn73xx cnf75xx;
05052 };
05053 typedef union cvmx_pko_l1_sqx_shape_state cvmx_pko_l1_sqx_shape_state_t;
05054
05055
05056
05057
05058 union cvmx_pko_l1_sqx_sw_xoff {
05059 uint64_t u64;
05060 struct cvmx_pko_l1_sqx_sw_xoff_s {
05061 #ifdef __BIG_ENDIAN_BITFIELD
05062 uint64_t reserved_4_63 : 60;
05063 uint64_t drain_irq : 1;
05064
05065
05066 uint64_t drain_null_link : 1;
05067
05068
05069
05070
05071
05072 uint64_t drain : 1;
05073
05074
05075
05076
05077
05078
05079
05080
05081
05082 uint64_t xoff : 1;
05083
05084
05085
05086
05087
05088
05089 #else
05090 uint64_t xoff : 1;
05091 uint64_t drain : 1;
05092 uint64_t drain_null_link : 1;
05093 uint64_t drain_irq : 1;
05094 uint64_t reserved_4_63 : 60;
05095 #endif
05096 } s;
05097 struct cvmx_pko_l1_sqx_sw_xoff_s cn73xx;
05098 struct cvmx_pko_l1_sqx_sw_xoff_s cn78xx;
05099 struct cvmx_pko_l1_sqx_sw_xoff_s cn78xxp1;
05100 struct cvmx_pko_l1_sqx_sw_xoff_s cnf75xx;
05101 };
05102 typedef union cvmx_pko_l1_sqx_sw_xoff cvmx_pko_l1_sqx_sw_xoff_t;
05103
05104
05105
05106
05107 union cvmx_pko_l1_sqx_topology {
05108 uint64_t u64;
05109 struct cvmx_pko_l1_sqx_topology_s {
05110 #ifdef __BIG_ENDIAN_BITFIELD
05111 uint64_t reserved_41_63 : 23;
05112 uint64_t prio_anchor : 9;
05113
05114
05115
05116
05117
05118
05119
05120
05121
05122 uint64_t reserved_21_31 : 11;
05123 uint64_t link : 5;
05124
05125
05126
05127
05128
05129
05130
05131
05132
05133
05134
05135
05136
05137
05138
05139
05140
05141
05142
05143 uint64_t reserved_5_15 : 11;
05144 uint64_t rr_prio : 4;
05145
05146
05147
05148
05149
05150
05151
05152
05153
05154 uint64_t reserved_0_0 : 1;
05155 #else
05156 uint64_t reserved_0_0 : 1;
05157 uint64_t rr_prio : 4;
05158 uint64_t reserved_5_15 : 11;
05159 uint64_t link : 5;
05160 uint64_t reserved_21_31 : 11;
05161 uint64_t prio_anchor : 9;
05162 uint64_t reserved_41_63 : 23;
05163 #endif
05164 } s;
05165 struct cvmx_pko_l1_sqx_topology_cn73xx {
05166 #ifdef __BIG_ENDIAN_BITFIELD
05167 uint64_t reserved_40_63 : 24;
05168 uint64_t prio_anchor : 8;
05169
05170
05171
05172
05173
05174
05175
05176
05177
05178 uint64_t reserved_20_31 : 12;
05179 uint64_t link : 4;
05180
05181
05182
05183
05184
05185
05186
05187
05188
05189
05190
05191
05192
05193
05194
05195
05196
05197
05198
05199
05200
05201
05202
05203 uint64_t reserved_5_15 : 11;
05204 uint64_t rr_prio : 4;
05205
05206
05207
05208
05209
05210
05211
05212
05213
05214 uint64_t reserved_0_0 : 1;
05215 #else
05216 uint64_t reserved_0_0 : 1;
05217 uint64_t rr_prio : 4;
05218 uint64_t reserved_5_15 : 11;
05219 uint64_t link : 4;
05220 uint64_t reserved_20_31 : 12;
05221 uint64_t prio_anchor : 8;
05222 uint64_t reserved_40_63 : 24;
05223 #endif
05224 } cn73xx;
05225 struct cvmx_pko_l1_sqx_topology_s cn78xx;
05226 struct cvmx_pko_l1_sqx_topology_s cn78xxp1;
05227 struct cvmx_pko_l1_sqx_topology_cn73xx cnf75xx;
05228 };
05229 typedef union cvmx_pko_l1_sqx_topology cvmx_pko_l1_sqx_topology_t;
05230
05231
05232
05233
05234 union cvmx_pko_l1_sqx_yellow {
05235 uint64_t u64;
05236 struct cvmx_pko_l1_sqx_yellow_s {
05237 #ifdef __BIG_ENDIAN_BITFIELD
05238 uint64_t reserved_19_63 : 45;
05239 uint64_t head : 9;
05240 uint64_t reserved_9_9 : 1;
05241 uint64_t tail : 9;
05242 #else
05243 uint64_t tail : 9;
05244 uint64_t reserved_9_9 : 1;
05245 uint64_t head : 9;
05246 uint64_t reserved_19_63 : 45;
05247 #endif
05248 } s;
05249 struct cvmx_pko_l1_sqx_yellow_s cn73xx;
05250 struct cvmx_pko_l1_sqx_yellow_s cn78xx;
05251 struct cvmx_pko_l1_sqx_yellow_s cn78xxp1;
05252 struct cvmx_pko_l1_sqx_yellow_s cnf75xx;
05253 };
05254 typedef union cvmx_pko_l1_sqx_yellow cvmx_pko_l1_sqx_yellow_t;
05255
05256
05257
05258
05259
05260
05261
05262 union cvmx_pko_l1_sqx_yellow_bytes {
05263 uint64_t u64;
05264 struct cvmx_pko_l1_sqx_yellow_bytes_s {
05265 #ifdef __BIG_ENDIAN_BITFIELD
05266 uint64_t reserved_48_63 : 16;
05267 uint64_t count : 48;
05268 #else
05269 uint64_t count : 48;
05270 uint64_t reserved_48_63 : 16;
05271 #endif
05272 } s;
05273 struct cvmx_pko_l1_sqx_yellow_bytes_s cn73xx;
05274 struct cvmx_pko_l1_sqx_yellow_bytes_s cn78xx;
05275 struct cvmx_pko_l1_sqx_yellow_bytes_s cn78xxp1;
05276 struct cvmx_pko_l1_sqx_yellow_bytes_s cnf75xx;
05277 };
05278 typedef union cvmx_pko_l1_sqx_yellow_bytes cvmx_pko_l1_sqx_yellow_bytes_t;
05279
05280
05281
05282
05283
05284
05285
05286 union cvmx_pko_l1_sqx_yellow_packets {
05287 uint64_t u64;
05288 struct cvmx_pko_l1_sqx_yellow_packets_s {
05289 #ifdef __BIG_ENDIAN_BITFIELD
05290 uint64_t reserved_40_63 : 24;
05291 uint64_t count : 40;
05292 #else
05293 uint64_t count : 40;
05294 uint64_t reserved_40_63 : 24;
05295 #endif
05296 } s;
05297 struct cvmx_pko_l1_sqx_yellow_packets_s cn73xx;
05298 struct cvmx_pko_l1_sqx_yellow_packets_s cn78xx;
05299 struct cvmx_pko_l1_sqx_yellow_packets_s cn78xxp1;
05300 struct cvmx_pko_l1_sqx_yellow_packets_s cnf75xx;
05301 };
05302 typedef union cvmx_pko_l1_sqx_yellow_packets cvmx_pko_l1_sqx_yellow_packets_t;
05303
05304
05305
05306
05307 union cvmx_pko_l1_sq_csr_bus_debug {
05308 uint64_t u64;
05309 struct cvmx_pko_l1_sq_csr_bus_debug_s {
05310 #ifdef __BIG_ENDIAN_BITFIELD
05311 uint64_t csr_bus_debug : 64;
05312 #else
05313 uint64_t csr_bus_debug : 64;
05314 #endif
05315 } s;
05316 struct cvmx_pko_l1_sq_csr_bus_debug_s cn73xx;
05317 struct cvmx_pko_l1_sq_csr_bus_debug_s cn78xx;
05318 struct cvmx_pko_l1_sq_csr_bus_debug_s cn78xxp1;
05319 struct cvmx_pko_l1_sq_csr_bus_debug_s cnf75xx;
05320 };
05321 typedef union cvmx_pko_l1_sq_csr_bus_debug cvmx_pko_l1_sq_csr_bus_debug_t;
05322
05323
05324
05325
05326
05327
05328
05329 union cvmx_pko_l1_sqa_debug {
05330 uint64_t u64;
05331 struct cvmx_pko_l1_sqa_debug_s {
05332 #ifdef __BIG_ENDIAN_BITFIELD
05333 uint64_t dbg_vec : 64;
05334 #else
05335 uint64_t dbg_vec : 64;
05336 #endif
05337 } s;
05338 struct cvmx_pko_l1_sqa_debug_s cn73xx;
05339 struct cvmx_pko_l1_sqa_debug_s cn78xx;
05340 struct cvmx_pko_l1_sqa_debug_s cn78xxp1;
05341 struct cvmx_pko_l1_sqa_debug_s cnf75xx;
05342 };
05343 typedef union cvmx_pko_l1_sqa_debug cvmx_pko_l1_sqa_debug_t;
05344
05345
05346
05347
05348
05349
05350
05351 union cvmx_pko_l1_sqb_debug {
05352 uint64_t u64;
05353 struct cvmx_pko_l1_sqb_debug_s {
05354 #ifdef __BIG_ENDIAN_BITFIELD
05355 uint64_t dbg_vec : 64;
05356 #else
05357 uint64_t dbg_vec : 64;
05358 #endif
05359 } s;
05360 struct cvmx_pko_l1_sqb_debug_s cn73xx;
05361 struct cvmx_pko_l1_sqb_debug_s cn78xx;
05362 struct cvmx_pko_l1_sqb_debug_s cn78xxp1;
05363 struct cvmx_pko_l1_sqb_debug_s cnf75xx;
05364 };
05365 typedef union cvmx_pko_l1_sqb_debug cvmx_pko_l1_sqb_debug_t;
05366
05367
05368
05369
05370
05371
05372
05373 union cvmx_pko_l2_sqx_cir {
05374 uint64_t u64;
05375 struct cvmx_pko_l2_sqx_cir_s {
05376 #ifdef __BIG_ENDIAN_BITFIELD
05377 uint64_t reserved_41_63 : 23;
05378 uint64_t burst_exponent : 4;
05379
05380
05381 uint64_t burst_mantissa : 8;
05382
05383
05384 uint64_t reserved_17_28 : 12;
05385 uint64_t rate_divider_exponent : 4;
05386
05387
05388
05389
05390
05391
05392
05393
05394
05395
05396
05397
05398
05399 uint64_t rate_exponent : 4;
05400
05401
05402 uint64_t rate_mantissa : 8;
05403 uint64_t enable : 1;
05404 #else
05405 uint64_t enable : 1;
05406 uint64_t rate_mantissa : 8;
05407 uint64_t rate_exponent : 4;
05408 uint64_t rate_divider_exponent : 4;
05409 uint64_t reserved_17_28 : 12;
05410 uint64_t burst_mantissa : 8;
05411 uint64_t burst_exponent : 4;
05412 uint64_t reserved_41_63 : 23;
05413 #endif
05414 } s;
05415 struct cvmx_pko_l2_sqx_cir_s cn73xx;
05416 struct cvmx_pko_l2_sqx_cir_s cn78xx;
05417 struct cvmx_pko_l2_sqx_cir_s cn78xxp1;
05418 struct cvmx_pko_l2_sqx_cir_s cnf75xx;
05419 };
05420 typedef union cvmx_pko_l2_sqx_cir cvmx_pko_l2_sqx_cir_t;
05421
05422
05423
05424
05425
05426
05427
05428 union cvmx_pko_l2_sqx_green {
05429 uint64_t u64;
05430 struct cvmx_pko_l2_sqx_green_s {
05431 #ifdef __BIG_ENDIAN_BITFIELD
05432 uint64_t reserved_41_63 : 23;
05433 uint64_t rr_active : 1;
05434
05435 uint64_t active_vec : 20;
05436
05437
05438
05439
05440 uint64_t reserved_19_19 : 1;
05441 uint64_t head : 9;
05442 uint64_t reserved_9_9 : 1;
05443 uint64_t tail : 9;
05444 #else
05445 uint64_t tail : 9;
05446 uint64_t reserved_9_9 : 1;
05447 uint64_t head : 9;
05448 uint64_t reserved_19_19 : 1;
05449 uint64_t active_vec : 20;
05450 uint64_t rr_active : 1;
05451 uint64_t reserved_41_63 : 23;
05452 #endif
05453 } s;
05454 struct cvmx_pko_l2_sqx_green_s cn73xx;
05455 struct cvmx_pko_l2_sqx_green_s cn78xx;
05456 struct cvmx_pko_l2_sqx_green_s cn78xxp1;
05457 struct cvmx_pko_l2_sqx_green_s cnf75xx;
05458 };
05459 typedef union cvmx_pko_l2_sqx_green cvmx_pko_l2_sqx_green_t;
05460
05461
05462
05463
05464
05465
05466
05467 union cvmx_pko_l2_sqx_pick {
05468 uint64_t u64;
05469 struct cvmx_pko_l2_sqx_pick_s {
05470 #ifdef __BIG_ENDIAN_BITFIELD
05471 uint64_t dq : 10;
05472 uint64_t color : 2;
05473 uint64_t child : 10;
05474
05475
05476 uint64_t bubble : 1;
05477 uint64_t p_con : 1;
05478 uint64_t c_con : 1;
05479 uint64_t uid : 7;
05480 uint64_t jump : 1;
05481
05482 uint64_t fpd : 1;
05483
05484 uint64_t ds : 1;
05485
05486 uint64_t adjust : 9;
05487
05488
05489
05490
05491 uint64_t pir_dis : 1;
05492
05493
05494
05495 uint64_t cir_dis : 1;
05496
05497
05498
05499
05500 uint64_t red_algo_override : 2;
05501
05502
05503
05504 uint64_t length : 16;
05505
05506
05507
05508
05509
05510
05511
05512
05513
05514
05515
05516 #else
05517 uint64_t length : 16;
05518 uint64_t red_algo_override : 2;
05519 uint64_t cir_dis : 1;
05520 uint64_t pir_dis : 1;
05521 uint64_t adjust : 9;
05522 uint64_t ds : 1;
05523 uint64_t fpd : 1;
05524 uint64_t jump : 1;
05525 uint64_t uid : 7;
05526 uint64_t c_con : 1;
05527 uint64_t p_con : 1;
05528 uint64_t bubble : 1;
05529 uint64_t child : 10;
05530 uint64_t color : 2;
05531 uint64_t dq : 10;
05532 #endif
05533 } s;
05534 struct cvmx_pko_l2_sqx_pick_s cn73xx;
05535 struct cvmx_pko_l2_sqx_pick_s cn78xx;
05536 struct cvmx_pko_l2_sqx_pick_s cn78xxp1;
05537 struct cvmx_pko_l2_sqx_pick_s cnf75xx;
05538 };
05539 typedef union cvmx_pko_l2_sqx_pick cvmx_pko_l2_sqx_pick_t;
05540
05541
05542
05543
05544
05545
05546
05547 union cvmx_pko_l2_sqx_pir {
05548 uint64_t u64;
05549 struct cvmx_pko_l2_sqx_pir_s {
05550 #ifdef __BIG_ENDIAN_BITFIELD
05551 uint64_t reserved_41_63 : 23;
05552 uint64_t burst_exponent : 4;
05553
05554
05555 uint64_t burst_mantissa : 8;
05556
05557
05558 uint64_t reserved_17_28 : 12;
05559 uint64_t rate_divider_exponent : 4;
05560
05561
05562
05563
05564
05565
05566
05567
05568
05569
05570
05571
05572
05573 uint64_t rate_exponent : 4;
05574
05575
05576 uint64_t rate_mantissa : 8;
05577 uint64_t enable : 1;
05578 #else
05579 uint64_t enable : 1;
05580 uint64_t rate_mantissa : 8;
05581 uint64_t rate_exponent : 4;
05582 uint64_t rate_divider_exponent : 4;
05583 uint64_t reserved_17_28 : 12;
05584 uint64_t burst_mantissa : 8;
05585 uint64_t burst_exponent : 4;
05586 uint64_t reserved_41_63 : 23;
05587 #endif
05588 } s;
05589 struct cvmx_pko_l2_sqx_pir_s cn73xx;
05590 struct cvmx_pko_l2_sqx_pir_s cn78xx;
05591 struct cvmx_pko_l2_sqx_pir_s cn78xxp1;
05592 struct cvmx_pko_l2_sqx_pir_s cnf75xx;
05593 };
05594 typedef union cvmx_pko_l2_sqx_pir cvmx_pko_l2_sqx_pir_t;
05595
05596
05597
05598
05599 union cvmx_pko_l2_sqx_pointers {
05600 uint64_t u64;
05601 struct cvmx_pko_l2_sqx_pointers_s {
05602 #ifdef __BIG_ENDIAN_BITFIELD
05603 uint64_t reserved_25_63 : 39;
05604 uint64_t prev : 9;
05605 uint64_t reserved_9_15 : 7;
05606 uint64_t next : 9;
05607 #else
05608 uint64_t next : 9;
05609 uint64_t reserved_9_15 : 7;
05610 uint64_t prev : 9;
05611 uint64_t reserved_25_63 : 39;
05612 #endif
05613 } s;
05614 struct cvmx_pko_l2_sqx_pointers_cn73xx {
05615 #ifdef __BIG_ENDIAN_BITFIELD
05616 uint64_t reserved_24_63 : 40;
05617 uint64_t prev : 8;
05618 uint64_t reserved_8_15 : 8;
05619 uint64_t next : 8;
05620 #else
05621 uint64_t next : 8;
05622 uint64_t reserved_8_15 : 8;
05623 uint64_t prev : 8;
05624 uint64_t reserved_24_63 : 40;
05625 #endif
05626 } cn73xx;
05627 struct cvmx_pko_l2_sqx_pointers_s cn78xx;
05628 struct cvmx_pko_l2_sqx_pointers_s cn78xxp1;
05629 struct cvmx_pko_l2_sqx_pointers_cn73xx cnf75xx;
05630 };
05631 typedef union cvmx_pko_l2_sqx_pointers cvmx_pko_l2_sqx_pointers_t;
05632
05633
05634
05635
05636
05637
05638
05639 union cvmx_pko_l2_sqx_red {
05640 uint64_t u64;
05641 struct cvmx_pko_l2_sqx_red_s {
05642 #ifdef __BIG_ENDIAN_BITFIELD
05643 uint64_t reserved_19_63 : 45;
05644 uint64_t head : 9;
05645 uint64_t reserved_9_9 : 1;
05646 uint64_t tail : 9;
05647 #else
05648 uint64_t tail : 9;
05649 uint64_t reserved_9_9 : 1;
05650 uint64_t head : 9;
05651 uint64_t reserved_19_63 : 45;
05652 #endif
05653 } s;
05654 struct cvmx_pko_l2_sqx_red_s cn73xx;
05655 struct cvmx_pko_l2_sqx_red_s cn78xx;
05656 struct cvmx_pko_l2_sqx_red_s cn78xxp1;
05657 struct cvmx_pko_l2_sqx_red_s cnf75xx;
05658 };
05659 typedef union cvmx_pko_l2_sqx_red cvmx_pko_l2_sqx_red_t;
05660
05661
05662
05663
05664 union cvmx_pko_l2_sqx_sched_state {
05665 uint64_t u64;
05666 struct cvmx_pko_l2_sqx_sched_state_s {
05667 #ifdef __BIG_ENDIAN_BITFIELD
05668 uint64_t reserved_25_63 : 39;
05669 uint64_t rr_count : 25;
05670 #else
05671 uint64_t rr_count : 25;
05672 uint64_t reserved_25_63 : 39;
05673 #endif
05674 } s;
05675 struct cvmx_pko_l2_sqx_sched_state_s cn73xx;
05676 struct cvmx_pko_l2_sqx_sched_state_s cn78xx;
05677 struct cvmx_pko_l2_sqx_sched_state_s cn78xxp1;
05678 struct cvmx_pko_l2_sqx_sched_state_s cnf75xx;
05679 };
05680 typedef union cvmx_pko_l2_sqx_sched_state cvmx_pko_l2_sqx_sched_state_t;
05681
05682
05683
05684
05685 union cvmx_pko_l2_sqx_schedule {
05686 uint64_t u64;
05687 struct cvmx_pko_l2_sqx_schedule_s {
05688 #ifdef __BIG_ENDIAN_BITFIELD
05689 uint64_t reserved_28_63 : 36;
05690 uint64_t prio : 4;
05691
05692
05693
05694
05695
05696 uint64_t rr_quantum : 24;
05697
05698
05699
05700
05701
05702
05703 #else
05704 uint64_t rr_quantum : 24;
05705 uint64_t prio : 4;
05706 uint64_t reserved_28_63 : 36;
05707 #endif
05708 } s;
05709 struct cvmx_pko_l2_sqx_schedule_s cn73xx;
05710 struct cvmx_pko_l2_sqx_schedule_s cn78xx;
05711 struct cvmx_pko_l2_sqx_schedule_s cn78xxp1;
05712 struct cvmx_pko_l2_sqx_schedule_s cnf75xx;
05713 };
05714 typedef union cvmx_pko_l2_sqx_schedule cvmx_pko_l2_sqx_schedule_t;
05715
05716
05717
05718
05719 union cvmx_pko_l2_sqx_shape {
05720 uint64_t u64;
05721 struct cvmx_pko_l2_sqx_shape_s {
05722 #ifdef __BIG_ENDIAN_BITFIELD
05723 uint64_t reserved_27_63 : 37;
05724 uint64_t schedule_list : 2;
05725
05726
05727
05728
05729 uint64_t length_disable : 1;
05730
05731 uint64_t reserved_13_23 : 11;
05732 uint64_t yellow_disable : 1;
05733
05734 uint64_t red_disable : 1;
05735
05736
05737 uint64_t red_algo : 2;
05738
05739
05740
05741
05742
05743
05744
05745
05746
05747
05748
05749
05750
05751
05752
05753
05754
05755
05756
05757
05758
05759
05760
05761 uint64_t adjust : 9;
05762
05763
05764 #else
05765 uint64_t adjust : 9;
05766 uint64_t red_algo : 2;
05767 uint64_t red_disable : 1;
05768 uint64_t yellow_disable : 1;
05769 uint64_t reserved_13_23 : 11;
05770 uint64_t length_disable : 1;
05771 uint64_t schedule_list : 2;
05772 uint64_t reserved_27_63 : 37;
05773 #endif
05774 } s;
05775 struct cvmx_pko_l2_sqx_shape_s cn73xx;
05776 struct cvmx_pko_l2_sqx_shape_cn78xx {
05777 #ifdef __BIG_ENDIAN_BITFIELD
05778 uint64_t reserved_25_63 : 39;
05779 uint64_t length_disable : 1;
05780
05781 uint64_t reserved_13_23 : 11;
05782 uint64_t yellow_disable : 1;
05783
05784 uint64_t red_disable : 1;
05785
05786
05787 uint64_t red_algo : 2;
05788
05789
05790
05791
05792
05793
05794
05795
05796
05797
05798
05799
05800
05801
05802
05803
05804
05805
05806
05807
05808
05809
05810
05811 uint64_t adjust : 9;
05812
05813
05814 #else
05815 uint64_t adjust : 9;
05816 uint64_t red_algo : 2;
05817 uint64_t red_disable : 1;
05818 uint64_t yellow_disable : 1;
05819 uint64_t reserved_13_23 : 11;
05820 uint64_t length_disable : 1;
05821 uint64_t reserved_25_63 : 39;
05822 #endif
05823 } cn78xx;
05824 struct cvmx_pko_l2_sqx_shape_cn78xx cn78xxp1;
05825 struct cvmx_pko_l2_sqx_shape_s cnf75xx;
05826 };
05827 typedef union cvmx_pko_l2_sqx_shape cvmx_pko_l2_sqx_shape_t;
05828
05829
05830
05831
05832
05833
05834
05835 union cvmx_pko_l2_sqx_shape_state {
05836 uint64_t u64;
05837 struct cvmx_pko_l2_sqx_shape_state_s {
05838 #ifdef __BIG_ENDIAN_BITFIELD
05839 uint64_t reserved_60_63 : 4;
05840 uint64_t tw_timestamp : 6;
05841 uint64_t color : 2;
05842
05843
05844
05845
05846 uint64_t pir_accum : 26;
05847 uint64_t cir_accum : 26;
05848 #else
05849 uint64_t cir_accum : 26;
05850 uint64_t pir_accum : 26;
05851 uint64_t color : 2;
05852 uint64_t tw_timestamp : 6;
05853 uint64_t reserved_60_63 : 4;
05854 #endif
05855 } s;
05856 struct cvmx_pko_l2_sqx_shape_state_s cn73xx;
05857 struct cvmx_pko_l2_sqx_shape_state_s cn78xx;
05858 struct cvmx_pko_l2_sqx_shape_state_s cn78xxp1;
05859 struct cvmx_pko_l2_sqx_shape_state_s cnf75xx;
05860 };
05861 typedef union cvmx_pko_l2_sqx_shape_state cvmx_pko_l2_sqx_shape_state_t;
05862
05863
05864
05865
05866
05867
05868
05869 union cvmx_pko_l2_sqx_sw_xoff {
05870 uint64_t u64;
05871 struct cvmx_pko_l2_sqx_sw_xoff_s {
05872 #ifdef __BIG_ENDIAN_BITFIELD
05873 uint64_t reserved_4_63 : 60;
05874 uint64_t drain_irq : 1;
05875
05876
05877 uint64_t drain_null_link : 1;
05878
05879
05880
05881
05882
05883 uint64_t drain : 1;
05884
05885
05886
05887
05888
05889
05890
05891
05892
05893 uint64_t xoff : 1;
05894
05895
05896
05897
05898
05899
05900 #else
05901 uint64_t xoff : 1;
05902 uint64_t drain : 1;
05903 uint64_t drain_null_link : 1;
05904 uint64_t drain_irq : 1;
05905 uint64_t reserved_4_63 : 60;
05906 #endif
05907 } s;
05908 struct cvmx_pko_l2_sqx_sw_xoff_s cn73xx;
05909 struct cvmx_pko_l2_sqx_sw_xoff_s cn78xx;
05910 struct cvmx_pko_l2_sqx_sw_xoff_s cn78xxp1;
05911 struct cvmx_pko_l2_sqx_sw_xoff_s cnf75xx;
05912 };
05913 typedef union cvmx_pko_l2_sqx_sw_xoff cvmx_pko_l2_sqx_sw_xoff_t;
05914
05915
05916
05917
05918 union cvmx_pko_l2_sqx_topology {
05919 uint64_t u64;
05920 struct cvmx_pko_l2_sqx_topology_s {
05921 #ifdef __BIG_ENDIAN_BITFIELD
05922 uint64_t reserved_41_63 : 23;
05923 uint64_t prio_anchor : 9;
05924 uint64_t reserved_21_31 : 11;
05925 uint64_t parent : 5;
05926
05927
05928
05929
05930 uint64_t reserved_5_15 : 11;
05931 uint64_t rr_prio : 4;
05932 uint64_t reserved_0_0 : 1;
05933 #else
05934 uint64_t reserved_0_0 : 1;
05935 uint64_t rr_prio : 4;
05936 uint64_t reserved_5_15 : 11;
05937 uint64_t parent : 5;
05938 uint64_t reserved_21_31 : 11;
05939 uint64_t prio_anchor : 9;
05940 uint64_t reserved_41_63 : 23;
05941 #endif
05942 } s;
05943 struct cvmx_pko_l2_sqx_topology_cn73xx {
05944 #ifdef __BIG_ENDIAN_BITFIELD
05945 uint64_t reserved_40_63 : 24;
05946 uint64_t prio_anchor : 8;
05947 uint64_t reserved_20_31 : 12;
05948 uint64_t parent : 4;
05949
05950
05951
05952
05953 uint64_t reserved_5_15 : 11;
05954 uint64_t rr_prio : 4;
05955 uint64_t reserved_0_0 : 1;
05956 #else
05957 uint64_t reserved_0_0 : 1;
05958 uint64_t rr_prio : 4;
05959 uint64_t reserved_5_15 : 11;
05960 uint64_t parent : 4;
05961 uint64_t reserved_20_31 : 12;
05962 uint64_t prio_anchor : 8;
05963 uint64_t reserved_40_63 : 24;
05964 #endif
05965 } cn73xx;
05966 struct cvmx_pko_l2_sqx_topology_s cn78xx;
05967 struct cvmx_pko_l2_sqx_topology_s cn78xxp1;
05968 struct cvmx_pko_l2_sqx_topology_cn73xx cnf75xx;
05969 };
05970 typedef union cvmx_pko_l2_sqx_topology cvmx_pko_l2_sqx_topology_t;
05971
05972
05973
05974
05975
05976
05977
05978 union cvmx_pko_l2_sqx_yellow {
05979 uint64_t u64;
05980 struct cvmx_pko_l2_sqx_yellow_s {
05981 #ifdef __BIG_ENDIAN_BITFIELD
05982 uint64_t reserved_19_63 : 45;
05983 uint64_t head : 9;
05984 uint64_t reserved_9_9 : 1;
05985 uint64_t tail : 9;
05986 #else
05987 uint64_t tail : 9;
05988 uint64_t reserved_9_9 : 1;
05989 uint64_t head : 9;
05990 uint64_t reserved_19_63 : 45;
05991 #endif
05992 } s;
05993 struct cvmx_pko_l2_sqx_yellow_s cn73xx;
05994 struct cvmx_pko_l2_sqx_yellow_s cn78xx;
05995 struct cvmx_pko_l2_sqx_yellow_s cn78xxp1;
05996 struct cvmx_pko_l2_sqx_yellow_s cnf75xx;
05997 };
05998 typedef union cvmx_pko_l2_sqx_yellow cvmx_pko_l2_sqx_yellow_t;
05999
06000
06001
06002
06003 union cvmx_pko_l2_sq_csr_bus_debug {
06004 uint64_t u64;
06005 struct cvmx_pko_l2_sq_csr_bus_debug_s {
06006 #ifdef __BIG_ENDIAN_BITFIELD
06007 uint64_t csr_bus_debug : 64;
06008 #else
06009 uint64_t csr_bus_debug : 64;
06010 #endif
06011 } s;
06012 struct cvmx_pko_l2_sq_csr_bus_debug_s cn73xx;
06013 struct cvmx_pko_l2_sq_csr_bus_debug_s cn78xx;
06014 struct cvmx_pko_l2_sq_csr_bus_debug_s cn78xxp1;
06015 struct cvmx_pko_l2_sq_csr_bus_debug_s cnf75xx;
06016 };
06017 typedef union cvmx_pko_l2_sq_csr_bus_debug cvmx_pko_l2_sq_csr_bus_debug_t;
06018
06019
06020
06021
06022
06023
06024
06025 union cvmx_pko_l2_sqa_debug {
06026 uint64_t u64;
06027 struct cvmx_pko_l2_sqa_debug_s {
06028 #ifdef __BIG_ENDIAN_BITFIELD
06029 uint64_t dbg_vec : 64;
06030 #else
06031 uint64_t dbg_vec : 64;
06032 #endif
06033 } s;
06034 struct cvmx_pko_l2_sqa_debug_s cn73xx;
06035 struct cvmx_pko_l2_sqa_debug_s cn78xx;
06036 struct cvmx_pko_l2_sqa_debug_s cn78xxp1;
06037 struct cvmx_pko_l2_sqa_debug_s cnf75xx;
06038 };
06039 typedef union cvmx_pko_l2_sqa_debug cvmx_pko_l2_sqa_debug_t;
06040
06041
06042
06043
06044
06045
06046
06047 union cvmx_pko_l2_sqb_debug {
06048 uint64_t u64;
06049 struct cvmx_pko_l2_sqb_debug_s {
06050 #ifdef __BIG_ENDIAN_BITFIELD
06051 uint64_t dbg_vec : 64;
06052 #else
06053 uint64_t dbg_vec : 64;
06054 #endif
06055 } s;
06056 struct cvmx_pko_l2_sqb_debug_s cn73xx;
06057 struct cvmx_pko_l2_sqb_debug_s cn78xx;
06058 struct cvmx_pko_l2_sqb_debug_s cn78xxp1;
06059 struct cvmx_pko_l2_sqb_debug_s cnf75xx;
06060 };
06061 typedef union cvmx_pko_l2_sqb_debug cvmx_pko_l2_sqb_debug_t;
06062
06063
06064
06065
06066
06067
06068
06069 union cvmx_pko_l3_l2_sqx_channel {
06070 uint64_t u64;
06071 struct cvmx_pko_l3_l2_sqx_channel_s {
06072 #ifdef __BIG_ENDIAN_BITFIELD
06073 uint64_t reserved_44_63 : 20;
06074 uint64_t cc_channel : 12;
06075 uint64_t cc_word_cnt : 20;
06076
06077
06078
06079
06080
06081 uint64_t cc_packet_cnt : 10;
06082
06083
06084
06085
06086 uint64_t cc_enable : 1;
06087 uint64_t hw_xoff : 1;
06088
06089
06090
06091 #else
06092 uint64_t hw_xoff : 1;
06093 uint64_t cc_enable : 1;
06094 uint64_t cc_packet_cnt : 10;
06095 uint64_t cc_word_cnt : 20;
06096 uint64_t cc_channel : 12;
06097 uint64_t reserved_44_63 : 20;
06098 #endif
06099 } s;
06100 struct cvmx_pko_l3_l2_sqx_channel_s cn73xx;
06101 struct cvmx_pko_l3_l2_sqx_channel_s cn78xx;
06102 struct cvmx_pko_l3_l2_sqx_channel_s cn78xxp1;
06103 struct cvmx_pko_l3_l2_sqx_channel_s cnf75xx;
06104 };
06105 typedef union cvmx_pko_l3_l2_sqx_channel cvmx_pko_l3_l2_sqx_channel_t;
06106
06107
06108
06109
06110
06111
06112
06113 union cvmx_pko_l3_sqx_cir {
06114 uint64_t u64;
06115 struct cvmx_pko_l3_sqx_cir_s {
06116 #ifdef __BIG_ENDIAN_BITFIELD
06117 uint64_t reserved_41_63 : 23;
06118 uint64_t burst_exponent : 4;
06119
06120
06121 uint64_t burst_mantissa : 8;
06122
06123
06124 uint64_t reserved_17_28 : 12;
06125 uint64_t rate_divider_exponent : 4;
06126
06127
06128
06129
06130
06131
06132
06133
06134
06135
06136
06137
06138
06139 uint64_t rate_exponent : 4;
06140
06141
06142 uint64_t rate_mantissa : 8;
06143 uint64_t enable : 1;
06144 #else
06145 uint64_t enable : 1;
06146 uint64_t rate_mantissa : 8;
06147 uint64_t rate_exponent : 4;
06148 uint64_t rate_divider_exponent : 4;
06149 uint64_t reserved_17_28 : 12;
06150 uint64_t burst_mantissa : 8;
06151 uint64_t burst_exponent : 4;
06152 uint64_t reserved_41_63 : 23;
06153 #endif
06154 } s;
06155 struct cvmx_pko_l3_sqx_cir_s cn73xx;
06156 struct cvmx_pko_l3_sqx_cir_s cn78xx;
06157 struct cvmx_pko_l3_sqx_cir_s cn78xxp1;
06158 struct cvmx_pko_l3_sqx_cir_s cnf75xx;
06159 };
06160 typedef union cvmx_pko_l3_sqx_cir cvmx_pko_l3_sqx_cir_t;
06161
06162
06163
06164
06165 union cvmx_pko_l3_sqx_green {
06166 uint64_t u64;
06167 struct cvmx_pko_l3_sqx_green_s {
06168 #ifdef __BIG_ENDIAN_BITFIELD
06169 uint64_t reserved_41_63 : 23;
06170 uint64_t rr_active : 1;
06171 uint64_t active_vec : 20;
06172
06173 uint64_t head : 10;
06174 uint64_t tail : 10;
06175 #else
06176 uint64_t tail : 10;
06177 uint64_t head : 10;
06178 uint64_t active_vec : 20;
06179 uint64_t rr_active : 1;
06180 uint64_t reserved_41_63 : 23;
06181 #endif
06182 } s;
06183 struct cvmx_pko_l3_sqx_green_cn73xx {
06184 #ifdef __BIG_ENDIAN_BITFIELD
06185 uint64_t reserved_41_63 : 23;
06186 uint64_t rr_active : 1;
06187 uint64_t active_vec : 20;
06188
06189 uint64_t reserved_18_19 : 2;
06190 uint64_t head : 8;
06191 uint64_t reserved_8_9 : 2;
06192 uint64_t tail : 8;
06193 #else
06194 uint64_t tail : 8;
06195 uint64_t reserved_8_9 : 2;
06196 uint64_t head : 8;
06197 uint64_t reserved_18_19 : 2;
06198 uint64_t active_vec : 20;
06199 uint64_t rr_active : 1;
06200 uint64_t reserved_41_63 : 23;
06201 #endif
06202 } cn73xx;
06203 struct cvmx_pko_l3_sqx_green_s cn78xx;
06204 struct cvmx_pko_l3_sqx_green_s cn78xxp1;
06205 struct cvmx_pko_l3_sqx_green_cn73xx cnf75xx;
06206 };
06207 typedef union cvmx_pko_l3_sqx_green cvmx_pko_l3_sqx_green_t;
06208
06209
06210
06211
06212
06213
06214
06215 union cvmx_pko_l3_sqx_pick {
06216 uint64_t u64;
06217 struct cvmx_pko_l3_sqx_pick_s {
06218 #ifdef __BIG_ENDIAN_BITFIELD
06219 uint64_t dq : 10;
06220 uint64_t color : 2;
06221 uint64_t child : 10;
06222
06223
06224 uint64_t bubble : 1;
06225 uint64_t p_con : 1;
06226 uint64_t c_con : 1;
06227 uint64_t uid : 7;
06228 uint64_t jump : 1;
06229
06230 uint64_t fpd : 1;
06231
06232 uint64_t ds : 1;
06233
06234 uint64_t adjust : 9;
06235
06236
06237
06238
06239 uint64_t pir_dis : 1;
06240
06241
06242
06243 uint64_t cir_dis : 1;
06244
06245
06246
06247
06248 uint64_t red_algo_override : 2;
06249
06250
06251
06252 uint64_t length : 16;
06253
06254
06255
06256
06257
06258
06259
06260
06261
06262
06263
06264 #else
06265 uint64_t length : 16;
06266 uint64_t red_algo_override : 2;
06267 uint64_t cir_dis : 1;
06268 uint64_t pir_dis : 1;
06269 uint64_t adjust : 9;
06270 uint64_t ds : 1;
06271 uint64_t fpd : 1;
06272 uint64_t jump : 1;
06273 uint64_t uid : 7;
06274 uint64_t c_con : 1;
06275 uint64_t p_con : 1;
06276 uint64_t bubble : 1;
06277 uint64_t child : 10;
06278 uint64_t color : 2;
06279 uint64_t dq : 10;
06280 #endif
06281 } s;
06282 struct cvmx_pko_l3_sqx_pick_s cn73xx;
06283 struct cvmx_pko_l3_sqx_pick_s cn78xx;
06284 struct cvmx_pko_l3_sqx_pick_s cn78xxp1;
06285 struct cvmx_pko_l3_sqx_pick_s cnf75xx;
06286 };
06287 typedef union cvmx_pko_l3_sqx_pick cvmx_pko_l3_sqx_pick_t;
06288
06289
06290
06291
06292
06293
06294
06295 union cvmx_pko_l3_sqx_pir {
06296 uint64_t u64;
06297 struct cvmx_pko_l3_sqx_pir_s {
06298 #ifdef __BIG_ENDIAN_BITFIELD
06299 uint64_t reserved_41_63 : 23;
06300 uint64_t burst_exponent : 4;
06301
06302
06303 uint64_t burst_mantissa : 8;
06304
06305
06306 uint64_t reserved_17_28 : 12;
06307 uint64_t rate_divider_exponent : 4;
06308
06309
06310
06311
06312
06313
06314
06315
06316
06317
06318
06319
06320
06321 uint64_t rate_exponent : 4;
06322
06323
06324 uint64_t rate_mantissa : 8;
06325 uint64_t enable : 1;
06326 #else
06327 uint64_t enable : 1;
06328 uint64_t rate_mantissa : 8;
06329 uint64_t rate_exponent : 4;
06330 uint64_t rate_divider_exponent : 4;
06331 uint64_t reserved_17_28 : 12;
06332 uint64_t burst_mantissa : 8;
06333 uint64_t burst_exponent : 4;
06334 uint64_t reserved_41_63 : 23;
06335 #endif
06336 } s;
06337 struct cvmx_pko_l3_sqx_pir_s cn73xx;
06338 struct cvmx_pko_l3_sqx_pir_s cn78xx;
06339 struct cvmx_pko_l3_sqx_pir_s cn78xxp1;
06340 struct cvmx_pko_l3_sqx_pir_s cnf75xx;
06341 };
06342 typedef union cvmx_pko_l3_sqx_pir cvmx_pko_l3_sqx_pir_t;
06343
06344
06345
06346
06347
06348
06349
06350 union cvmx_pko_l3_sqx_pointers {
06351 uint64_t u64;
06352 struct cvmx_pko_l3_sqx_pointers_s {
06353 #ifdef __BIG_ENDIAN_BITFIELD
06354 uint64_t reserved_25_63 : 39;
06355 uint64_t prev : 9;
06356 uint64_t reserved_9_15 : 7;
06357 uint64_t next : 9;
06358 #else
06359 uint64_t next : 9;
06360 uint64_t reserved_9_15 : 7;
06361 uint64_t prev : 9;
06362 uint64_t reserved_25_63 : 39;
06363 #endif
06364 } s;
06365 struct cvmx_pko_l3_sqx_pointers_cn73xx {
06366 #ifdef __BIG_ENDIAN_BITFIELD
06367 uint64_t reserved_24_63 : 40;
06368 uint64_t prev : 8;
06369 uint64_t reserved_8_15 : 8;
06370 uint64_t next : 8;
06371 #else
06372 uint64_t next : 8;
06373 uint64_t reserved_8_15 : 8;
06374 uint64_t prev : 8;
06375 uint64_t reserved_24_63 : 40;
06376 #endif
06377 } cn73xx;
06378 struct cvmx_pko_l3_sqx_pointers_s cn78xx;
06379 struct cvmx_pko_l3_sqx_pointers_s cn78xxp1;
06380 struct cvmx_pko_l3_sqx_pointers_cn73xx cnf75xx;
06381 };
06382 typedef union cvmx_pko_l3_sqx_pointers cvmx_pko_l3_sqx_pointers_t;
06383
06384
06385
06386
06387
06388
06389
06390 union cvmx_pko_l3_sqx_red {
06391 uint64_t u64;
06392 struct cvmx_pko_l3_sqx_red_s {
06393 #ifdef __BIG_ENDIAN_BITFIELD
06394 uint64_t reserved_20_63 : 44;
06395 uint64_t head : 10;
06396 uint64_t tail : 10;
06397 #else
06398 uint64_t tail : 10;
06399 uint64_t head : 10;
06400 uint64_t reserved_20_63 : 44;
06401 #endif
06402 } s;
06403 struct cvmx_pko_l3_sqx_red_cn73xx {
06404 #ifdef __BIG_ENDIAN_BITFIELD
06405 uint64_t reserved_18_63 : 46;
06406 uint64_t head : 8;
06407 uint64_t reserved_8_9 : 2;
06408 uint64_t tail : 8;
06409 #else
06410 uint64_t tail : 8;
06411 uint64_t reserved_8_9 : 2;
06412 uint64_t head : 8;
06413 uint64_t reserved_18_63 : 46;
06414 #endif
06415 } cn73xx;
06416 struct cvmx_pko_l3_sqx_red_s cn78xx;
06417 struct cvmx_pko_l3_sqx_red_s cn78xxp1;
06418 struct cvmx_pko_l3_sqx_red_cn73xx cnf75xx;
06419 };
06420 typedef union cvmx_pko_l3_sqx_red cvmx_pko_l3_sqx_red_t;
06421
06422
06423
06424
06425
06426
06427
06428 union cvmx_pko_l3_sqx_sched_state {
06429 uint64_t u64;
06430 struct cvmx_pko_l3_sqx_sched_state_s {
06431 #ifdef __BIG_ENDIAN_BITFIELD
06432 uint64_t reserved_25_63 : 39;
06433 uint64_t rr_count : 25;
06434 #else
06435 uint64_t rr_count : 25;
06436 uint64_t reserved_25_63 : 39;
06437 #endif
06438 } s;
06439 struct cvmx_pko_l3_sqx_sched_state_s cn73xx;
06440 struct cvmx_pko_l3_sqx_sched_state_s cn78xx;
06441 struct cvmx_pko_l3_sqx_sched_state_s cn78xxp1;
06442 struct cvmx_pko_l3_sqx_sched_state_s cnf75xx;
06443 };
06444 typedef union cvmx_pko_l3_sqx_sched_state cvmx_pko_l3_sqx_sched_state_t;
06445
06446
06447
06448
06449
06450
06451
06452 union cvmx_pko_l3_sqx_schedule {
06453 uint64_t u64;
06454 struct cvmx_pko_l3_sqx_schedule_s {
06455 #ifdef __BIG_ENDIAN_BITFIELD
06456 uint64_t reserved_28_63 : 36;
06457 uint64_t prio : 4;
06458
06459
06460
06461
06462
06463 uint64_t rr_quantum : 24;
06464
06465
06466
06467
06468
06469
06470 #else
06471 uint64_t rr_quantum : 24;
06472 uint64_t prio : 4;
06473 uint64_t reserved_28_63 : 36;
06474 #endif
06475 } s;
06476 struct cvmx_pko_l3_sqx_schedule_s cn73xx;
06477 struct cvmx_pko_l3_sqx_schedule_s cn78xx;
06478 struct cvmx_pko_l3_sqx_schedule_s cn78xxp1;
06479 struct cvmx_pko_l3_sqx_schedule_s cnf75xx;
06480 };
06481 typedef union cvmx_pko_l3_sqx_schedule cvmx_pko_l3_sqx_schedule_t;
06482
06483
06484
06485
06486 union cvmx_pko_l3_sqx_shape {
06487 uint64_t u64;
06488 struct cvmx_pko_l3_sqx_shape_s {
06489 #ifdef __BIG_ENDIAN_BITFIELD
06490 uint64_t reserved_27_63 : 37;
06491 uint64_t schedule_list : 2;
06492
06493
06494
06495
06496 uint64_t length_disable : 1;
06497
06498 uint64_t reserved_13_23 : 11;
06499 uint64_t yellow_disable : 1;
06500 uint64_t red_disable : 1;
06501 uint64_t red_algo : 2;
06502 uint64_t adjust : 9;
06503 #else
06504 uint64_t adjust : 9;
06505 uint64_t red_algo : 2;
06506 uint64_t red_disable : 1;
06507 uint64_t yellow_disable : 1;
06508 uint64_t reserved_13_23 : 11;
06509 uint64_t length_disable : 1;
06510 uint64_t schedule_list : 2;
06511 uint64_t reserved_27_63 : 37;
06512 #endif
06513 } s;
06514 struct cvmx_pko_l3_sqx_shape_s cn73xx;
06515 struct cvmx_pko_l3_sqx_shape_cn78xx {
06516 #ifdef __BIG_ENDIAN_BITFIELD
06517 uint64_t reserved_25_63 : 39;
06518 uint64_t length_disable : 1;
06519
06520 uint64_t reserved_13_23 : 11;
06521 uint64_t yellow_disable : 1;
06522 uint64_t red_disable : 1;
06523 uint64_t red_algo : 2;
06524 uint64_t adjust : 9;
06525 #else
06526 uint64_t adjust : 9;
06527 uint64_t red_algo : 2;
06528 uint64_t red_disable : 1;
06529 uint64_t yellow_disable : 1;
06530 uint64_t reserved_13_23 : 11;
06531 uint64_t length_disable : 1;
06532 uint64_t reserved_25_63 : 39;
06533 #endif
06534 } cn78xx;
06535 struct cvmx_pko_l3_sqx_shape_cn78xx cn78xxp1;
06536 struct cvmx_pko_l3_sqx_shape_s cnf75xx;
06537 };
06538 typedef union cvmx_pko_l3_sqx_shape cvmx_pko_l3_sqx_shape_t;
06539
06540
06541
06542
06543
06544
06545
06546 union cvmx_pko_l3_sqx_shape_state {
06547 uint64_t u64;
06548 struct cvmx_pko_l3_sqx_shape_state_s {
06549 #ifdef __BIG_ENDIAN_BITFIELD
06550 uint64_t reserved_60_63 : 4;
06551 uint64_t tw_timestamp : 6;
06552 uint64_t color : 2;
06553
06554
06555
06556
06557 uint64_t pir_accum : 26;
06558 uint64_t cir_accum : 26;
06559 #else
06560 uint64_t cir_accum : 26;
06561 uint64_t pir_accum : 26;
06562 uint64_t color : 2;
06563 uint64_t tw_timestamp : 6;
06564 uint64_t reserved_60_63 : 4;
06565 #endif
06566 } s;
06567 struct cvmx_pko_l3_sqx_shape_state_s cn73xx;
06568 struct cvmx_pko_l3_sqx_shape_state_s cn78xx;
06569 struct cvmx_pko_l3_sqx_shape_state_s cn78xxp1;
06570 struct cvmx_pko_l3_sqx_shape_state_s cnf75xx;
06571 };
06572 typedef union cvmx_pko_l3_sqx_shape_state cvmx_pko_l3_sqx_shape_state_t;
06573
06574
06575
06576
06577
06578
06579
06580 union cvmx_pko_l3_sqx_sw_xoff {
06581 uint64_t u64;
06582 struct cvmx_pko_l3_sqx_sw_xoff_s {
06583 #ifdef __BIG_ENDIAN_BITFIELD
06584 uint64_t reserved_4_63 : 60;
06585 uint64_t drain_irq : 1;
06586
06587
06588 uint64_t drain_null_link : 1;
06589
06590
06591
06592
06593
06594 uint64_t drain : 1;
06595
06596
06597
06598
06599
06600
06601
06602
06603
06604 uint64_t xoff : 1;
06605
06606
06607
06608
06609
06610
06611 #else
06612 uint64_t xoff : 1;
06613 uint64_t drain : 1;
06614 uint64_t drain_null_link : 1;
06615 uint64_t drain_irq : 1;
06616 uint64_t reserved_4_63 : 60;
06617 #endif
06618 } s;
06619 struct cvmx_pko_l3_sqx_sw_xoff_s cn73xx;
06620 struct cvmx_pko_l3_sqx_sw_xoff_s cn78xx;
06621 struct cvmx_pko_l3_sqx_sw_xoff_s cn78xxp1;
06622 struct cvmx_pko_l3_sqx_sw_xoff_s cnf75xx;
06623 };
06624 typedef union cvmx_pko_l3_sqx_sw_xoff cvmx_pko_l3_sqx_sw_xoff_t;
06625
06626
06627
06628
06629 union cvmx_pko_l3_sqx_topology {
06630 uint64_t u64;
06631 struct cvmx_pko_l3_sqx_topology_s {
06632 #ifdef __BIG_ENDIAN_BITFIELD
06633 uint64_t reserved_42_63 : 22;
06634 uint64_t prio_anchor : 10;
06635 uint64_t reserved_25_31 : 7;
06636 uint64_t parent : 9;
06637 uint64_t reserved_5_15 : 11;
06638 uint64_t rr_prio : 4;
06639 uint64_t reserved_0_0 : 1;
06640 #else
06641 uint64_t reserved_0_0 : 1;
06642 uint64_t rr_prio : 4;
06643 uint64_t reserved_5_15 : 11;
06644 uint64_t parent : 9;
06645 uint64_t reserved_25_31 : 7;
06646 uint64_t prio_anchor : 10;
06647 uint64_t reserved_42_63 : 22;
06648 #endif
06649 } s;
06650 struct cvmx_pko_l3_sqx_topology_cn73xx {
06651 #ifdef __BIG_ENDIAN_BITFIELD
06652 uint64_t reserved_40_63 : 24;
06653 uint64_t prio_anchor : 8;
06654 uint64_t reserved_24_31 : 8;
06655 uint64_t parent : 8;
06656 uint64_t reserved_5_15 : 11;
06657 uint64_t rr_prio : 4;
06658 uint64_t reserved_0_0 : 1;
06659 #else
06660 uint64_t reserved_0_0 : 1;
06661 uint64_t rr_prio : 4;
06662 uint64_t reserved_5_15 : 11;
06663 uint64_t parent : 8;
06664 uint64_t reserved_24_31 : 8;
06665 uint64_t prio_anchor : 8;
06666 uint64_t reserved_40_63 : 24;
06667 #endif
06668 } cn73xx;
06669 struct cvmx_pko_l3_sqx_topology_s cn78xx;
06670 struct cvmx_pko_l3_sqx_topology_s cn78xxp1;
06671 struct cvmx_pko_l3_sqx_topology_cn73xx cnf75xx;
06672 };
06673 typedef union cvmx_pko_l3_sqx_topology cvmx_pko_l3_sqx_topology_t;
06674
06675
06676
06677
06678 union cvmx_pko_l3_sqx_yellow {
06679 uint64_t u64;
06680 struct cvmx_pko_l3_sqx_yellow_s {
06681 #ifdef __BIG_ENDIAN_BITFIELD
06682 uint64_t reserved_20_63 : 44;
06683 uint64_t head : 10;
06684 uint64_t tail : 10;
06685 #else
06686 uint64_t tail : 10;
06687 uint64_t head : 10;
06688 uint64_t reserved_20_63 : 44;
06689 #endif
06690 } s;
06691 struct cvmx_pko_l3_sqx_yellow_cn73xx {
06692 #ifdef __BIG_ENDIAN_BITFIELD
06693 uint64_t reserved_18_63 : 46;
06694 uint64_t head : 8;
06695 uint64_t reserved_8_9 : 2;
06696 uint64_t tail : 8;
06697 #else
06698 uint64_t tail : 8;
06699 uint64_t reserved_8_9 : 2;
06700 uint64_t head : 8;
06701 uint64_t reserved_18_63 : 46;
06702 #endif
06703 } cn73xx;
06704 struct cvmx_pko_l3_sqx_yellow_s cn78xx;
06705 struct cvmx_pko_l3_sqx_yellow_s cn78xxp1;
06706 struct cvmx_pko_l3_sqx_yellow_cn73xx cnf75xx;
06707 };
06708 typedef union cvmx_pko_l3_sqx_yellow cvmx_pko_l3_sqx_yellow_t;
06709
06710
06711
06712
06713 union cvmx_pko_l3_sq_csr_bus_debug {
06714 uint64_t u64;
06715 struct cvmx_pko_l3_sq_csr_bus_debug_s {
06716 #ifdef __BIG_ENDIAN_BITFIELD
06717 uint64_t csr_bus_debug : 64;
06718 #else
06719 uint64_t csr_bus_debug : 64;
06720 #endif
06721 } s;
06722 struct cvmx_pko_l3_sq_csr_bus_debug_s cn73xx;
06723 struct cvmx_pko_l3_sq_csr_bus_debug_s cn78xx;
06724 struct cvmx_pko_l3_sq_csr_bus_debug_s cn78xxp1;
06725 struct cvmx_pko_l3_sq_csr_bus_debug_s cnf75xx;
06726 };
06727 typedef union cvmx_pko_l3_sq_csr_bus_debug cvmx_pko_l3_sq_csr_bus_debug_t;
06728
06729
06730
06731
06732
06733
06734
06735 union cvmx_pko_l3_sqa_debug {
06736 uint64_t u64;
06737 struct cvmx_pko_l3_sqa_debug_s {
06738 #ifdef __BIG_ENDIAN_BITFIELD
06739 uint64_t dbg_vec : 64;
06740 #else
06741 uint64_t dbg_vec : 64;
06742 #endif
06743 } s;
06744 struct cvmx_pko_l3_sqa_debug_s cn73xx;
06745 struct cvmx_pko_l3_sqa_debug_s cn78xx;
06746 struct cvmx_pko_l3_sqa_debug_s cn78xxp1;
06747 struct cvmx_pko_l3_sqa_debug_s cnf75xx;
06748 };
06749 typedef union cvmx_pko_l3_sqa_debug cvmx_pko_l3_sqa_debug_t;
06750
06751
06752
06753
06754
06755
06756
06757 union cvmx_pko_l3_sqb_debug {
06758 uint64_t u64;
06759 struct cvmx_pko_l3_sqb_debug_s {
06760 #ifdef __BIG_ENDIAN_BITFIELD
06761 uint64_t dbg_vec : 64;
06762 #else
06763 uint64_t dbg_vec : 64;
06764 #endif
06765 } s;
06766 struct cvmx_pko_l3_sqb_debug_s cn73xx;
06767 struct cvmx_pko_l3_sqb_debug_s cn78xx;
06768 struct cvmx_pko_l3_sqb_debug_s cn78xxp1;
06769 struct cvmx_pko_l3_sqb_debug_s cnf75xx;
06770 };
06771 typedef union cvmx_pko_l3_sqb_debug cvmx_pko_l3_sqb_debug_t;
06772
06773
06774
06775
06776
06777
06778
06779 union cvmx_pko_l4_sqx_cir {
06780 uint64_t u64;
06781 struct cvmx_pko_l4_sqx_cir_s {
06782 #ifdef __BIG_ENDIAN_BITFIELD
06783 uint64_t reserved_41_63 : 23;
06784 uint64_t burst_exponent : 4;
06785
06786
06787 uint64_t burst_mantissa : 8;
06788
06789
06790 uint64_t reserved_17_28 : 12;
06791 uint64_t rate_divider_exponent : 4;
06792
06793
06794
06795
06796
06797
06798
06799
06800
06801
06802
06803
06804
06805 uint64_t rate_exponent : 4;
06806
06807
06808 uint64_t rate_mantissa : 8;
06809 uint64_t enable : 1;
06810 #else
06811 uint64_t enable : 1;
06812 uint64_t rate_mantissa : 8;
06813 uint64_t rate_exponent : 4;
06814 uint64_t rate_divider_exponent : 4;
06815 uint64_t reserved_17_28 : 12;
06816 uint64_t burst_mantissa : 8;
06817 uint64_t burst_exponent : 4;
06818 uint64_t reserved_41_63 : 23;
06819 #endif
06820 } s;
06821 struct cvmx_pko_l4_sqx_cir_s cn78xx;
06822 struct cvmx_pko_l4_sqx_cir_s cn78xxp1;
06823 };
06824 typedef union cvmx_pko_l4_sqx_cir cvmx_pko_l4_sqx_cir_t;
06825
06826
06827
06828
06829
06830
06831
06832 union cvmx_pko_l4_sqx_green {
06833 uint64_t u64;
06834 struct cvmx_pko_l4_sqx_green_s {
06835 #ifdef __BIG_ENDIAN_BITFIELD
06836 uint64_t reserved_41_63 : 23;
06837 uint64_t rr_active : 1;
06838 uint64_t active_vec : 20;
06839
06840 uint64_t head : 10;
06841 uint64_t tail : 10;
06842 #else
06843 uint64_t tail : 10;
06844 uint64_t head : 10;
06845 uint64_t active_vec : 20;
06846 uint64_t rr_active : 1;
06847 uint64_t reserved_41_63 : 23;
06848 #endif
06849 } s;
06850 struct cvmx_pko_l4_sqx_green_s cn78xx;
06851 struct cvmx_pko_l4_sqx_green_s cn78xxp1;
06852 };
06853 typedef union cvmx_pko_l4_sqx_green cvmx_pko_l4_sqx_green_t;
06854
06855
06856
06857
06858
06859
06860
06861 union cvmx_pko_l4_sqx_pick {
06862 uint64_t u64;
06863 struct cvmx_pko_l4_sqx_pick_s {
06864 #ifdef __BIG_ENDIAN_BITFIELD
06865 uint64_t dq : 10;
06866 uint64_t color : 2;
06867 uint64_t child : 10;
06868
06869
06870 uint64_t bubble : 1;
06871 uint64_t p_con : 1;
06872 uint64_t c_con : 1;
06873 uint64_t uid : 7;
06874 uint64_t jump : 1;
06875
06876 uint64_t fpd : 1;
06877
06878 uint64_t ds : 1;
06879
06880 uint64_t adjust : 9;
06881
06882
06883
06884
06885 uint64_t pir_dis : 1;
06886
06887
06888
06889 uint64_t cir_dis : 1;
06890
06891
06892
06893
06894 uint64_t red_algo_override : 2;
06895
06896
06897
06898 uint64_t length : 16;
06899
06900
06901
06902
06903
06904
06905
06906
06907
06908
06909
06910 #else
06911 uint64_t length : 16;
06912 uint64_t red_algo_override : 2;
06913 uint64_t cir_dis : 1;
06914 uint64_t pir_dis : 1;
06915 uint64_t adjust : 9;
06916 uint64_t ds : 1;
06917 uint64_t fpd : 1;
06918 uint64_t jump : 1;
06919 uint64_t uid : 7;
06920 uint64_t c_con : 1;
06921 uint64_t p_con : 1;
06922 uint64_t bubble : 1;
06923 uint64_t child : 10;
06924 uint64_t color : 2;
06925 uint64_t dq : 10;
06926 #endif
06927 } s;
06928 struct cvmx_pko_l4_sqx_pick_s cn78xx;
06929 struct cvmx_pko_l4_sqx_pick_s cn78xxp1;
06930 };
06931 typedef union cvmx_pko_l4_sqx_pick cvmx_pko_l4_sqx_pick_t;
06932
06933
06934
06935
06936
06937
06938
06939 union cvmx_pko_l4_sqx_pir {
06940 uint64_t u64;
06941 struct cvmx_pko_l4_sqx_pir_s {
06942 #ifdef __BIG_ENDIAN_BITFIELD
06943 uint64_t reserved_41_63 : 23;
06944 uint64_t burst_exponent : 4;
06945
06946
06947 uint64_t burst_mantissa : 8;
06948
06949
06950 uint64_t reserved_17_28 : 12;
06951 uint64_t rate_divider_exponent : 4;
06952
06953
06954
06955
06956
06957
06958
06959
06960
06961
06962
06963
06964
06965 uint64_t rate_exponent : 4;
06966
06967
06968 uint64_t rate_mantissa : 8;
06969 uint64_t enable : 1;
06970 #else
06971 uint64_t enable : 1;
06972 uint64_t rate_mantissa : 8;
06973 uint64_t rate_exponent : 4;
06974 uint64_t rate_divider_exponent : 4;
06975 uint64_t reserved_17_28 : 12;
06976 uint64_t burst_mantissa : 8;
06977 uint64_t burst_exponent : 4;
06978 uint64_t reserved_41_63 : 23;
06979 #endif
06980 } s;
06981 struct cvmx_pko_l4_sqx_pir_s cn78xx;
06982 struct cvmx_pko_l4_sqx_pir_s cn78xxp1;
06983 };
06984 typedef union cvmx_pko_l4_sqx_pir cvmx_pko_l4_sqx_pir_t;
06985
06986
06987
06988
06989 union cvmx_pko_l4_sqx_pointers {
06990 uint64_t u64;
06991 struct cvmx_pko_l4_sqx_pointers_s {
06992 #ifdef __BIG_ENDIAN_BITFIELD
06993 uint64_t reserved_26_63 : 38;
06994 uint64_t prev : 10;
06995 uint64_t reserved_10_15 : 6;
06996 uint64_t next : 10;
06997 #else
06998 uint64_t next : 10;
06999 uint64_t reserved_10_15 : 6;
07000 uint64_t prev : 10;
07001 uint64_t reserved_26_63 : 38;
07002 #endif
07003 } s;
07004 struct cvmx_pko_l4_sqx_pointers_s cn78xx;
07005 struct cvmx_pko_l4_sqx_pointers_s cn78xxp1;
07006 };
07007 typedef union cvmx_pko_l4_sqx_pointers cvmx_pko_l4_sqx_pointers_t;
07008
07009
07010
07011
07012
07013
07014
07015 union cvmx_pko_l4_sqx_red {
07016 uint64_t u64;
07017 struct cvmx_pko_l4_sqx_red_s {
07018 #ifdef __BIG_ENDIAN_BITFIELD
07019 uint64_t reserved_20_63 : 44;
07020 uint64_t head : 10;
07021 uint64_t tail : 10;
07022 #else
07023 uint64_t tail : 10;
07024 uint64_t head : 10;
07025 uint64_t reserved_20_63 : 44;
07026 #endif
07027 } s;
07028 struct cvmx_pko_l4_sqx_red_s cn78xx;
07029 struct cvmx_pko_l4_sqx_red_s cn78xxp1;
07030 };
07031 typedef union cvmx_pko_l4_sqx_red cvmx_pko_l4_sqx_red_t;
07032
07033
07034
07035
07036
07037
07038
07039 union cvmx_pko_l4_sqx_sched_state {
07040 uint64_t u64;
07041 struct cvmx_pko_l4_sqx_sched_state_s {
07042 #ifdef __BIG_ENDIAN_BITFIELD
07043 uint64_t reserved_25_63 : 39;
07044 uint64_t rr_count : 25;
07045 #else
07046 uint64_t rr_count : 25;
07047 uint64_t reserved_25_63 : 39;
07048 #endif
07049 } s;
07050 struct cvmx_pko_l4_sqx_sched_state_s cn78xx;
07051 struct cvmx_pko_l4_sqx_sched_state_s cn78xxp1;
07052 };
07053 typedef union cvmx_pko_l4_sqx_sched_state cvmx_pko_l4_sqx_sched_state_t;
07054
07055
07056
07057
07058
07059
07060
07061 union cvmx_pko_l4_sqx_schedule {
07062 uint64_t u64;
07063 struct cvmx_pko_l4_sqx_schedule_s {
07064 #ifdef __BIG_ENDIAN_BITFIELD
07065 uint64_t reserved_28_63 : 36;
07066 uint64_t prio : 4;
07067
07068
07069
07070
07071
07072 uint64_t rr_quantum : 24;
07073
07074
07075
07076
07077
07078
07079 #else
07080 uint64_t rr_quantum : 24;
07081 uint64_t prio : 4;
07082 uint64_t reserved_28_63 : 36;
07083 #endif
07084 } s;
07085 struct cvmx_pko_l4_sqx_schedule_s cn78xx;
07086 struct cvmx_pko_l4_sqx_schedule_s cn78xxp1;
07087 };
07088 typedef union cvmx_pko_l4_sqx_schedule cvmx_pko_l4_sqx_schedule_t;
07089
07090
07091
07092
07093
07094
07095
07096 union cvmx_pko_l4_sqx_shape {
07097 uint64_t u64;
07098 struct cvmx_pko_l4_sqx_shape_s {
07099 #ifdef __BIG_ENDIAN_BITFIELD
07100 uint64_t reserved_25_63 : 39;
07101 uint64_t length_disable : 1;
07102
07103 uint64_t reserved_13_23 : 11;
07104 uint64_t yellow_disable : 1;
07105 uint64_t red_disable : 1;
07106 uint64_t red_algo : 2;
07107 uint64_t adjust : 9;
07108 #else
07109 uint64_t adjust : 9;
07110 uint64_t red_algo : 2;
07111 uint64_t red_disable : 1;
07112 uint64_t yellow_disable : 1;
07113 uint64_t reserved_13_23 : 11;
07114 uint64_t length_disable : 1;
07115 uint64_t reserved_25_63 : 39;
07116 #endif
07117 } s;
07118 struct cvmx_pko_l4_sqx_shape_s cn78xx;
07119 struct cvmx_pko_l4_sqx_shape_s cn78xxp1;
07120 };
07121 typedef union cvmx_pko_l4_sqx_shape cvmx_pko_l4_sqx_shape_t;
07122
07123
07124
07125
07126
07127
07128
07129 union cvmx_pko_l4_sqx_shape_state {
07130 uint64_t u64;
07131 struct cvmx_pko_l4_sqx_shape_state_s {
07132 #ifdef __BIG_ENDIAN_BITFIELD
07133 uint64_t reserved_60_63 : 4;
07134 uint64_t tw_timestamp : 6;
07135 uint64_t color : 2;
07136
07137
07138
07139
07140 uint64_t pir_accum : 26;
07141 uint64_t cir_accum : 26;
07142 #else
07143 uint64_t cir_accum : 26;
07144 uint64_t pir_accum : 26;
07145 uint64_t color : 2;
07146 uint64_t tw_timestamp : 6;
07147 uint64_t reserved_60_63 : 4;
07148 #endif
07149 } s;
07150 struct cvmx_pko_l4_sqx_shape_state_s cn78xx;
07151 struct cvmx_pko_l4_sqx_shape_state_s cn78xxp1;
07152 };
07153 typedef union cvmx_pko_l4_sqx_shape_state cvmx_pko_l4_sqx_shape_state_t;
07154
07155
07156
07157
07158
07159
07160
07161 union cvmx_pko_l4_sqx_sw_xoff {
07162 uint64_t u64;
07163 struct cvmx_pko_l4_sqx_sw_xoff_s {
07164 #ifdef __BIG_ENDIAN_BITFIELD
07165 uint64_t reserved_4_63 : 60;
07166 uint64_t drain_irq : 1;
07167
07168
07169 uint64_t drain_null_link : 1;
07170
07171
07172
07173
07174
07175 uint64_t drain : 1;
07176
07177
07178
07179
07180
07181
07182
07183
07184
07185 uint64_t xoff : 1;
07186
07187
07188
07189
07190
07191
07192 #else
07193 uint64_t xoff : 1;
07194 uint64_t drain : 1;
07195 uint64_t drain_null_link : 1;
07196 uint64_t drain_irq : 1;
07197 uint64_t reserved_4_63 : 60;
07198 #endif
07199 } s;
07200 struct cvmx_pko_l4_sqx_sw_xoff_s cn78xx;
07201 struct cvmx_pko_l4_sqx_sw_xoff_s cn78xxp1;
07202 };
07203 typedef union cvmx_pko_l4_sqx_sw_xoff cvmx_pko_l4_sqx_sw_xoff_t;
07204
07205
07206
07207
07208 union cvmx_pko_l4_sqx_topology {
07209 uint64_t u64;
07210 struct cvmx_pko_l4_sqx_topology_s {
07211 #ifdef __BIG_ENDIAN_BITFIELD
07212 uint64_t reserved_42_63 : 22;
07213 uint64_t prio_anchor : 10;
07214 uint64_t reserved_25_31 : 7;
07215 uint64_t parent : 9;
07216 uint64_t reserved_5_15 : 11;
07217 uint64_t rr_prio : 4;
07218 uint64_t reserved_0_0 : 1;
07219 #else
07220 uint64_t reserved_0_0 : 1;
07221 uint64_t rr_prio : 4;
07222 uint64_t reserved_5_15 : 11;
07223 uint64_t parent : 9;
07224 uint64_t reserved_25_31 : 7;
07225 uint64_t prio_anchor : 10;
07226 uint64_t reserved_42_63 : 22;
07227 #endif
07228 } s;
07229 struct cvmx_pko_l4_sqx_topology_s cn78xx;
07230 struct cvmx_pko_l4_sqx_topology_s cn78xxp1;
07231 };
07232 typedef union cvmx_pko_l4_sqx_topology cvmx_pko_l4_sqx_topology_t;
07233
07234
07235
07236
07237
07238
07239
07240 union cvmx_pko_l4_sqx_yellow {
07241 uint64_t u64;
07242 struct cvmx_pko_l4_sqx_yellow_s {
07243 #ifdef __BIG_ENDIAN_BITFIELD
07244 uint64_t reserved_20_63 : 44;
07245 uint64_t head : 10;
07246 uint64_t tail : 10;
07247 #else
07248 uint64_t tail : 10;
07249 uint64_t head : 10;
07250 uint64_t reserved_20_63 : 44;
07251 #endif
07252 } s;
07253 struct cvmx_pko_l4_sqx_yellow_s cn78xx;
07254 struct cvmx_pko_l4_sqx_yellow_s cn78xxp1;
07255 };
07256 typedef union cvmx_pko_l4_sqx_yellow cvmx_pko_l4_sqx_yellow_t;
07257
07258
07259
07260
07261 union cvmx_pko_l4_sq_csr_bus_debug {
07262 uint64_t u64;
07263 struct cvmx_pko_l4_sq_csr_bus_debug_s {
07264 #ifdef __BIG_ENDIAN_BITFIELD
07265 uint64_t csr_bus_debug : 64;
07266 #else
07267 uint64_t csr_bus_debug : 64;
07268 #endif
07269 } s;
07270 struct cvmx_pko_l4_sq_csr_bus_debug_s cn78xx;
07271 struct cvmx_pko_l4_sq_csr_bus_debug_s cn78xxp1;
07272 };
07273 typedef union cvmx_pko_l4_sq_csr_bus_debug cvmx_pko_l4_sq_csr_bus_debug_t;
07274
07275
07276
07277
07278
07279
07280
07281 union cvmx_pko_l4_sqa_debug {
07282 uint64_t u64;
07283 struct cvmx_pko_l4_sqa_debug_s {
07284 #ifdef __BIG_ENDIAN_BITFIELD
07285 uint64_t dbg_vec : 64;
07286 #else
07287 uint64_t dbg_vec : 64;
07288 #endif
07289 } s;
07290 struct cvmx_pko_l4_sqa_debug_s cn78xx;
07291 struct cvmx_pko_l4_sqa_debug_s cn78xxp1;
07292 };
07293 typedef union cvmx_pko_l4_sqa_debug cvmx_pko_l4_sqa_debug_t;
07294
07295
07296
07297
07298
07299
07300
07301 union cvmx_pko_l4_sqb_debug {
07302 uint64_t u64;
07303 struct cvmx_pko_l4_sqb_debug_s {
07304 #ifdef __BIG_ENDIAN_BITFIELD
07305 uint64_t dbg_vec : 64;
07306 #else
07307 uint64_t dbg_vec : 64;
07308 #endif
07309 } s;
07310 struct cvmx_pko_l4_sqb_debug_s cn78xx;
07311 struct cvmx_pko_l4_sqb_debug_s cn78xxp1;
07312 };
07313 typedef union cvmx_pko_l4_sqb_debug cvmx_pko_l4_sqb_debug_t;
07314
07315
07316
07317
07318
07319
07320
07321 union cvmx_pko_l5_sqx_cir {
07322 uint64_t u64;
07323 struct cvmx_pko_l5_sqx_cir_s {
07324 #ifdef __BIG_ENDIAN_BITFIELD
07325 uint64_t reserved_41_63 : 23;
07326 uint64_t burst_exponent : 4;
07327
07328
07329 uint64_t burst_mantissa : 8;
07330
07331
07332 uint64_t reserved_17_28 : 12;
07333 uint64_t rate_divider_exponent : 4;
07334
07335
07336
07337
07338
07339
07340
07341
07342
07343
07344
07345
07346
07347 uint64_t rate_exponent : 4;
07348
07349
07350 uint64_t rate_mantissa : 8;
07351 uint64_t enable : 1;
07352 #else
07353 uint64_t enable : 1;
07354 uint64_t rate_mantissa : 8;
07355 uint64_t rate_exponent : 4;
07356 uint64_t rate_divider_exponent : 4;
07357 uint64_t reserved_17_28 : 12;
07358 uint64_t burst_mantissa : 8;
07359 uint64_t burst_exponent : 4;
07360 uint64_t reserved_41_63 : 23;
07361 #endif
07362 } s;
07363 struct cvmx_pko_l5_sqx_cir_s cn78xx;
07364 struct cvmx_pko_l5_sqx_cir_s cn78xxp1;
07365 };
07366 typedef union cvmx_pko_l5_sqx_cir cvmx_pko_l5_sqx_cir_t;
07367
07368
07369
07370
07371
07372
07373
07374 union cvmx_pko_l5_sqx_green {
07375 uint64_t u64;
07376 struct cvmx_pko_l5_sqx_green_s {
07377 #ifdef __BIG_ENDIAN_BITFIELD
07378 uint64_t reserved_41_63 : 23;
07379 uint64_t rr_active : 1;
07380 uint64_t active_vec : 20;
07381
07382 uint64_t head : 10;
07383 uint64_t tail : 10;
07384 #else
07385 uint64_t tail : 10;
07386 uint64_t head : 10;
07387 uint64_t active_vec : 20;
07388 uint64_t rr_active : 1;
07389 uint64_t reserved_41_63 : 23;
07390 #endif
07391 } s;
07392 struct cvmx_pko_l5_sqx_green_s cn78xx;
07393 struct cvmx_pko_l5_sqx_green_s cn78xxp1;
07394 };
07395 typedef union cvmx_pko_l5_sqx_green cvmx_pko_l5_sqx_green_t;
07396
07397
07398
07399
07400
07401
07402
07403 union cvmx_pko_l5_sqx_pick {
07404 uint64_t u64;
07405 struct cvmx_pko_l5_sqx_pick_s {
07406 #ifdef __BIG_ENDIAN_BITFIELD
07407 uint64_t dq : 10;
07408 uint64_t color : 2;
07409 uint64_t child : 10;
07410
07411
07412 uint64_t bubble : 1;
07413 uint64_t p_con : 1;
07414 uint64_t c_con : 1;
07415 uint64_t uid : 7;
07416 uint64_t jump : 1;
07417
07418 uint64_t fpd : 1;
07419
07420 uint64_t ds : 1;
07421
07422 uint64_t adjust : 9;
07423
07424
07425
07426
07427 uint64_t pir_dis : 1;
07428
07429
07430
07431 uint64_t cir_dis : 1;
07432
07433
07434
07435
07436 uint64_t red_algo_override : 2;
07437
07438
07439
07440 uint64_t length : 16;
07441
07442
07443
07444
07445
07446
07447
07448
07449
07450
07451
07452 #else
07453 uint64_t length : 16;
07454 uint64_t red_algo_override : 2;
07455 uint64_t cir_dis : 1;
07456 uint64_t pir_dis : 1;
07457 uint64_t adjust : 9;
07458 uint64_t ds : 1;
07459 uint64_t fpd : 1;
07460 uint64_t jump : 1;
07461 uint64_t uid : 7;
07462 uint64_t c_con : 1;
07463 uint64_t p_con : 1;
07464 uint64_t bubble : 1;
07465 uint64_t child : 10;
07466 uint64_t color : 2;
07467 uint64_t dq : 10;
07468 #endif
07469 } s;
07470 struct cvmx_pko_l5_sqx_pick_s cn78xx;
07471 struct cvmx_pko_l5_sqx_pick_s cn78xxp1;
07472 };
07473 typedef union cvmx_pko_l5_sqx_pick cvmx_pko_l5_sqx_pick_t;
07474
07475
07476
07477
07478
07479
07480
07481 union cvmx_pko_l5_sqx_pir {
07482 uint64_t u64;
07483 struct cvmx_pko_l5_sqx_pir_s {
07484 #ifdef __BIG_ENDIAN_BITFIELD
07485 uint64_t reserved_41_63 : 23;
07486 uint64_t burst_exponent : 4;
07487
07488
07489 uint64_t burst_mantissa : 8;
07490
07491
07492 uint64_t reserved_17_28 : 12;
07493 uint64_t rate_divider_exponent : 4;
07494
07495
07496
07497
07498
07499
07500
07501
07502
07503
07504
07505
07506
07507 uint64_t rate_exponent : 4;
07508
07509
07510 uint64_t rate_mantissa : 8;
07511 uint64_t enable : 1;
07512 #else
07513 uint64_t enable : 1;
07514 uint64_t rate_mantissa : 8;
07515 uint64_t rate_exponent : 4;
07516 uint64_t rate_divider_exponent : 4;
07517 uint64_t reserved_17_28 : 12;
07518 uint64_t burst_mantissa : 8;
07519 uint64_t burst_exponent : 4;
07520 uint64_t reserved_41_63 : 23;
07521 #endif
07522 } s;
07523 struct cvmx_pko_l5_sqx_pir_s cn78xx;
07524 struct cvmx_pko_l5_sqx_pir_s cn78xxp1;
07525 };
07526 typedef union cvmx_pko_l5_sqx_pir cvmx_pko_l5_sqx_pir_t;
07527
07528
07529
07530
07531
07532
07533
07534 union cvmx_pko_l5_sqx_pointers {
07535 uint64_t u64;
07536 struct cvmx_pko_l5_sqx_pointers_s {
07537 #ifdef __BIG_ENDIAN_BITFIELD
07538 uint64_t reserved_26_63 : 38;
07539 uint64_t prev : 10;
07540 uint64_t reserved_10_15 : 6;
07541 uint64_t next : 10;
07542 #else
07543 uint64_t next : 10;
07544 uint64_t reserved_10_15 : 6;
07545 uint64_t prev : 10;
07546 uint64_t reserved_26_63 : 38;
07547 #endif
07548 } s;
07549 struct cvmx_pko_l5_sqx_pointers_s cn78xx;
07550 struct cvmx_pko_l5_sqx_pointers_s cn78xxp1;
07551 };
07552 typedef union cvmx_pko_l5_sqx_pointers cvmx_pko_l5_sqx_pointers_t;
07553
07554
07555
07556
07557
07558
07559
07560 union cvmx_pko_l5_sqx_red {
07561 uint64_t u64;
07562 struct cvmx_pko_l5_sqx_red_s {
07563 #ifdef __BIG_ENDIAN_BITFIELD
07564 uint64_t reserved_20_63 : 44;
07565 uint64_t head : 10;
07566 uint64_t tail : 10;
07567 #else
07568 uint64_t tail : 10;
07569 uint64_t head : 10;
07570 uint64_t reserved_20_63 : 44;
07571 #endif
07572 } s;
07573 struct cvmx_pko_l5_sqx_red_s cn78xx;
07574 struct cvmx_pko_l5_sqx_red_s cn78xxp1;
07575 };
07576 typedef union cvmx_pko_l5_sqx_red cvmx_pko_l5_sqx_red_t;
07577
07578
07579
07580
07581
07582
07583
07584 union cvmx_pko_l5_sqx_sched_state {
07585 uint64_t u64;
07586 struct cvmx_pko_l5_sqx_sched_state_s {
07587 #ifdef __BIG_ENDIAN_BITFIELD
07588 uint64_t reserved_25_63 : 39;
07589 uint64_t rr_count : 25;
07590 #else
07591 uint64_t rr_count : 25;
07592 uint64_t reserved_25_63 : 39;
07593 #endif
07594 } s;
07595 struct cvmx_pko_l5_sqx_sched_state_s cn78xx;
07596 struct cvmx_pko_l5_sqx_sched_state_s cn78xxp1;
07597 };
07598 typedef union cvmx_pko_l5_sqx_sched_state cvmx_pko_l5_sqx_sched_state_t;
07599
07600
07601
07602
07603
07604
07605
07606 union cvmx_pko_l5_sqx_schedule {
07607 uint64_t u64;
07608 struct cvmx_pko_l5_sqx_schedule_s {
07609 #ifdef __BIG_ENDIAN_BITFIELD
07610 uint64_t reserved_28_63 : 36;
07611 uint64_t prio : 4;
07612
07613
07614
07615
07616
07617 uint64_t rr_quantum : 24;
07618
07619
07620
07621
07622
07623
07624 #else
07625 uint64_t rr_quantum : 24;
07626 uint64_t prio : 4;
07627 uint64_t reserved_28_63 : 36;
07628 #endif
07629 } s;
07630 struct cvmx_pko_l5_sqx_schedule_s cn78xx;
07631 struct cvmx_pko_l5_sqx_schedule_s cn78xxp1;
07632 };
07633 typedef union cvmx_pko_l5_sqx_schedule cvmx_pko_l5_sqx_schedule_t;
07634
07635
07636
07637
07638 union cvmx_pko_l5_sqx_shape {
07639 uint64_t u64;
07640 struct cvmx_pko_l5_sqx_shape_s {
07641 #ifdef __BIG_ENDIAN_BITFIELD
07642 uint64_t reserved_25_63 : 39;
07643 uint64_t length_disable : 1;
07644
07645 uint64_t reserved_13_23 : 11;
07646 uint64_t yellow_disable : 1;
07647 uint64_t red_disable : 1;
07648 uint64_t red_algo : 2;
07649 uint64_t adjust : 9;
07650 #else
07651 uint64_t adjust : 9;
07652 uint64_t red_algo : 2;
07653 uint64_t red_disable : 1;
07654 uint64_t yellow_disable : 1;
07655 uint64_t reserved_13_23 : 11;
07656 uint64_t length_disable : 1;
07657 uint64_t reserved_25_63 : 39;
07658 #endif
07659 } s;
07660 struct cvmx_pko_l5_sqx_shape_s cn78xx;
07661 struct cvmx_pko_l5_sqx_shape_s cn78xxp1;
07662 };
07663 typedef union cvmx_pko_l5_sqx_shape cvmx_pko_l5_sqx_shape_t;
07664
07665
07666
07667
07668
07669
07670
07671 union cvmx_pko_l5_sqx_shape_state {
07672 uint64_t u64;
07673 struct cvmx_pko_l5_sqx_shape_state_s {
07674 #ifdef __BIG_ENDIAN_BITFIELD
07675 uint64_t reserved_60_63 : 4;
07676 uint64_t tw_timestamp : 6;
07677 uint64_t color : 2;
07678
07679
07680
07681
07682 uint64_t pir_accum : 26;
07683 uint64_t cir_accum : 26;
07684 #else
07685 uint64_t cir_accum : 26;
07686 uint64_t pir_accum : 26;
07687 uint64_t color : 2;
07688 uint64_t tw_timestamp : 6;
07689 uint64_t reserved_60_63 : 4;
07690 #endif
07691 } s;
07692 struct cvmx_pko_l5_sqx_shape_state_s cn78xx;
07693 struct cvmx_pko_l5_sqx_shape_state_s cn78xxp1;
07694 };
07695 typedef union cvmx_pko_l5_sqx_shape_state cvmx_pko_l5_sqx_shape_state_t;
07696
07697
07698
07699
07700
07701
07702
07703 union cvmx_pko_l5_sqx_sw_xoff {
07704 uint64_t u64;
07705 struct cvmx_pko_l5_sqx_sw_xoff_s {
07706 #ifdef __BIG_ENDIAN_BITFIELD
07707 uint64_t reserved_4_63 : 60;
07708 uint64_t drain_irq : 1;
07709
07710
07711 uint64_t drain_null_link : 1;
07712
07713
07714
07715
07716
07717 uint64_t drain : 1;
07718
07719
07720
07721
07722
07723
07724
07725
07726
07727 uint64_t xoff : 1;
07728
07729
07730
07731
07732
07733
07734 #else
07735 uint64_t xoff : 1;
07736 uint64_t drain : 1;
07737 uint64_t drain_null_link : 1;
07738 uint64_t drain_irq : 1;
07739 uint64_t reserved_4_63 : 60;
07740 #endif
07741 } s;
07742 struct cvmx_pko_l5_sqx_sw_xoff_s cn78xx;
07743 struct cvmx_pko_l5_sqx_sw_xoff_s cn78xxp1;
07744 };
07745 typedef union cvmx_pko_l5_sqx_sw_xoff cvmx_pko_l5_sqx_sw_xoff_t;
07746
07747
07748
07749
07750 union cvmx_pko_l5_sqx_topology {
07751 uint64_t u64;
07752 struct cvmx_pko_l5_sqx_topology_s {
07753 #ifdef __BIG_ENDIAN_BITFIELD
07754 uint64_t reserved_42_63 : 22;
07755 uint64_t prio_anchor : 10;
07756 uint64_t reserved_26_31 : 6;
07757 uint64_t parent : 10;
07758 uint64_t reserved_5_15 : 11;
07759 uint64_t rr_prio : 4;
07760 uint64_t reserved_0_0 : 1;
07761 #else
07762 uint64_t reserved_0_0 : 1;
07763 uint64_t rr_prio : 4;
07764 uint64_t reserved_5_15 : 11;
07765 uint64_t parent : 10;
07766 uint64_t reserved_26_31 : 6;
07767 uint64_t prio_anchor : 10;
07768 uint64_t reserved_42_63 : 22;
07769 #endif
07770 } s;
07771 struct cvmx_pko_l5_sqx_topology_s cn78xx;
07772 struct cvmx_pko_l5_sqx_topology_s cn78xxp1;
07773 };
07774 typedef union cvmx_pko_l5_sqx_topology cvmx_pko_l5_sqx_topology_t;
07775
07776
07777
07778
07779
07780
07781
07782 union cvmx_pko_l5_sqx_yellow {
07783 uint64_t u64;
07784 struct cvmx_pko_l5_sqx_yellow_s {
07785 #ifdef __BIG_ENDIAN_BITFIELD
07786 uint64_t reserved_20_63 : 44;
07787 uint64_t head : 10;
07788 uint64_t tail : 10;
07789 #else
07790 uint64_t tail : 10;
07791 uint64_t head : 10;
07792 uint64_t reserved_20_63 : 44;
07793 #endif
07794 } s;
07795 struct cvmx_pko_l5_sqx_yellow_s cn78xx;
07796 struct cvmx_pko_l5_sqx_yellow_s cn78xxp1;
07797 };
07798 typedef union cvmx_pko_l5_sqx_yellow cvmx_pko_l5_sqx_yellow_t;
07799
07800
07801
07802
07803 union cvmx_pko_l5_sq_csr_bus_debug {
07804 uint64_t u64;
07805 struct cvmx_pko_l5_sq_csr_bus_debug_s {
07806 #ifdef __BIG_ENDIAN_BITFIELD
07807 uint64_t csr_bus_debug : 64;
07808 #else
07809 uint64_t csr_bus_debug : 64;
07810 #endif
07811 } s;
07812 struct cvmx_pko_l5_sq_csr_bus_debug_s cn78xx;
07813 struct cvmx_pko_l5_sq_csr_bus_debug_s cn78xxp1;
07814 };
07815 typedef union cvmx_pko_l5_sq_csr_bus_debug cvmx_pko_l5_sq_csr_bus_debug_t;
07816
07817
07818
07819
07820
07821
07822
07823 union cvmx_pko_l5_sqa_debug {
07824 uint64_t u64;
07825 struct cvmx_pko_l5_sqa_debug_s {
07826 #ifdef __BIG_ENDIAN_BITFIELD
07827 uint64_t dbg_vec : 64;
07828 #else
07829 uint64_t dbg_vec : 64;
07830 #endif
07831 } s;
07832 struct cvmx_pko_l5_sqa_debug_s cn78xx;
07833 struct cvmx_pko_l5_sqa_debug_s cn78xxp1;
07834 };
07835 typedef union cvmx_pko_l5_sqa_debug cvmx_pko_l5_sqa_debug_t;
07836
07837
07838
07839
07840
07841
07842
07843 union cvmx_pko_l5_sqb_debug {
07844 uint64_t u64;
07845 struct cvmx_pko_l5_sqb_debug_s {
07846 #ifdef __BIG_ENDIAN_BITFIELD
07847 uint64_t dbg_vec : 64;
07848 #else
07849 uint64_t dbg_vec : 64;
07850 #endif
07851 } s;
07852 struct cvmx_pko_l5_sqb_debug_s cn78xx;
07853 struct cvmx_pko_l5_sqb_debug_s cn78xxp1;
07854 };
07855 typedef union cvmx_pko_l5_sqb_debug cvmx_pko_l5_sqb_debug_t;
07856
07857
07858
07859
07860
07861
07862
07863
07864
07865
07866
07867
07868
07869
07870
07871
07872
07873
07874
07875
07876 union cvmx_pko_lutx {
07877 uint64_t u64;
07878 struct cvmx_pko_lutx_s {
07879 #ifdef __BIG_ENDIAN_BITFIELD
07880 uint64_t reserved_16_63 : 48;
07881 uint64_t valid : 1;
07882 uint64_t reserved_14_14 : 1;
07883 uint64_t pq_idx : 5;
07884
07885 uint64_t queue_number : 9;
07886
07887
07888
07889 #else
07890 uint64_t queue_number : 9;
07891 uint64_t pq_idx : 5;
07892 uint64_t reserved_14_14 : 1;
07893 uint64_t valid : 1;
07894 uint64_t reserved_16_63 : 48;
07895 #endif
07896 } s;
07897 struct cvmx_pko_lutx_cn73xx {
07898 #ifdef __BIG_ENDIAN_BITFIELD
07899 uint64_t reserved_16_63 : 48;
07900 uint64_t valid : 1;
07901 uint64_t reserved_13_14 : 2;
07902 uint64_t pq_idx : 4;
07903
07904 uint64_t reserved_8_8 : 1;
07905 uint64_t queue_number : 8;
07906
07907
07908
07909 #else
07910 uint64_t queue_number : 8;
07911 uint64_t reserved_8_8 : 1;
07912 uint64_t pq_idx : 4;
07913 uint64_t reserved_13_14 : 2;
07914 uint64_t valid : 1;
07915 uint64_t reserved_16_63 : 48;
07916 #endif
07917 } cn73xx;
07918 struct cvmx_pko_lutx_s cn78xx;
07919 struct cvmx_pko_lutx_s cn78xxp1;
07920 struct cvmx_pko_lutx_cn73xx cnf75xx;
07921 };
07922 typedef union cvmx_pko_lutx cvmx_pko_lutx_t;
07923
07924
07925
07926
07927 union cvmx_pko_lut_bist_status {
07928 uint64_t u64;
07929 struct cvmx_pko_lut_bist_status_s {
07930 #ifdef __BIG_ENDIAN_BITFIELD
07931 uint64_t reserved_1_63 : 63;
07932 uint64_t bist_status : 1;
07933 #else
07934 uint64_t bist_status : 1;
07935 uint64_t reserved_1_63 : 63;
07936 #endif
07937 } s;
07938 struct cvmx_pko_lut_bist_status_s cn73xx;
07939 struct cvmx_pko_lut_bist_status_s cn78xx;
07940 struct cvmx_pko_lut_bist_status_s cn78xxp1;
07941 struct cvmx_pko_lut_bist_status_s cnf75xx;
07942 };
07943 typedef union cvmx_pko_lut_bist_status cvmx_pko_lut_bist_status_t;
07944
07945
07946
07947
07948 union cvmx_pko_lut_ecc_ctl0 {
07949 uint64_t u64;
07950 struct cvmx_pko_lut_ecc_ctl0_s {
07951 #ifdef __BIG_ENDIAN_BITFIELD
07952 uint64_t c2q_lut_ram_flip : 2;
07953 uint64_t c2q_lut_ram_cdis : 1;
07954 uint64_t reserved_0_60 : 61;
07955 #else
07956 uint64_t reserved_0_60 : 61;
07957 uint64_t c2q_lut_ram_cdis : 1;
07958 uint64_t c2q_lut_ram_flip : 2;
07959 #endif
07960 } s;
07961 struct cvmx_pko_lut_ecc_ctl0_s cn73xx;
07962 struct cvmx_pko_lut_ecc_ctl0_s cn78xx;
07963 struct cvmx_pko_lut_ecc_ctl0_s cn78xxp1;
07964 struct cvmx_pko_lut_ecc_ctl0_s cnf75xx;
07965 };
07966 typedef union cvmx_pko_lut_ecc_ctl0 cvmx_pko_lut_ecc_ctl0_t;
07967
07968
07969
07970
07971 union cvmx_pko_lut_ecc_dbe_sts0 {
07972 uint64_t u64;
07973 struct cvmx_pko_lut_ecc_dbe_sts0_s {
07974 #ifdef __BIG_ENDIAN_BITFIELD
07975 uint64_t c2q_lut_ram_dbe : 1;
07976 uint64_t reserved_0_62 : 63;
07977 #else
07978 uint64_t reserved_0_62 : 63;
07979 uint64_t c2q_lut_ram_dbe : 1;
07980 #endif
07981 } s;
07982 struct cvmx_pko_lut_ecc_dbe_sts0_s cn73xx;
07983 struct cvmx_pko_lut_ecc_dbe_sts0_s cn78xx;
07984 struct cvmx_pko_lut_ecc_dbe_sts0_s cn78xxp1;
07985 struct cvmx_pko_lut_ecc_dbe_sts0_s cnf75xx;
07986 };
07987 typedef union cvmx_pko_lut_ecc_dbe_sts0 cvmx_pko_lut_ecc_dbe_sts0_t;
07988
07989
07990
07991
07992 union cvmx_pko_lut_ecc_dbe_sts_cmb0 {
07993 uint64_t u64;
07994 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s {
07995 #ifdef __BIG_ENDIAN_BITFIELD
07996 uint64_t lut_dbe_cmb0 : 1;
07997
07998
07999
08000 uint64_t reserved_0_62 : 63;
08001 #else
08002 uint64_t reserved_0_62 : 63;
08003 uint64_t lut_dbe_cmb0 : 1;
08004 #endif
08005 } s;
08006 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn73xx;
08007 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn78xx;
08008 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn78xxp1;
08009 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cnf75xx;
08010 };
08011 typedef union cvmx_pko_lut_ecc_dbe_sts_cmb0 cvmx_pko_lut_ecc_dbe_sts_cmb0_t;
08012
08013
08014
08015
08016 union cvmx_pko_lut_ecc_sbe_sts0 {
08017 uint64_t u64;
08018 struct cvmx_pko_lut_ecc_sbe_sts0_s {
08019 #ifdef __BIG_ENDIAN_BITFIELD
08020 uint64_t c2q_lut_ram_sbe : 1;
08021 uint64_t reserved_0_62 : 63;
08022 #else
08023 uint64_t reserved_0_62 : 63;
08024 uint64_t c2q_lut_ram_sbe : 1;
08025 #endif
08026 } s;
08027 struct cvmx_pko_lut_ecc_sbe_sts0_s cn73xx;
08028 struct cvmx_pko_lut_ecc_sbe_sts0_s cn78xx;
08029 struct cvmx_pko_lut_ecc_sbe_sts0_s cn78xxp1;
08030 struct cvmx_pko_lut_ecc_sbe_sts0_s cnf75xx;
08031 };
08032 typedef union cvmx_pko_lut_ecc_sbe_sts0 cvmx_pko_lut_ecc_sbe_sts0_t;
08033
08034
08035
08036
08037 union cvmx_pko_lut_ecc_sbe_sts_cmb0 {
08038 uint64_t u64;
08039 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s {
08040 #ifdef __BIG_ENDIAN_BITFIELD
08041 uint64_t lut_sbe_cmb0 : 1;
08042
08043
08044
08045 uint64_t reserved_0_62 : 63;
08046 #else
08047 uint64_t reserved_0_62 : 63;
08048 uint64_t lut_sbe_cmb0 : 1;
08049 #endif
08050 } s;
08051 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn73xx;
08052 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn78xx;
08053 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn78xxp1;
08054 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cnf75xx;
08055 };
08056 typedef union cvmx_pko_lut_ecc_sbe_sts_cmb0 cvmx_pko_lut_ecc_sbe_sts_cmb0_t;
08057
08058
08059
08060
08061
08062
08063
08064
08065
08066
08067
08068
08069
08070
08071
08072
08073
08074
08075
08076
08077
08078
08079
08080 union cvmx_pko_macx_cfg {
08081 uint64_t u64;
08082 struct cvmx_pko_macx_cfg_s {
08083 #ifdef __BIG_ENDIAN_BITFIELD
08084 uint64_t reserved_17_63 : 47;
08085 uint64_t min_pad_ena : 1;
08086
08087
08088
08089
08090 uint64_t fcs_ena : 1;
08091
08092
08093 uint64_t fcs_sop_off : 8;
08094
08095 uint64_t skid_max_cnt : 2;
08096 uint64_t fifo_num : 5;
08097
08098
08099
08100
08101
08102 #else
08103 uint64_t fifo_num : 5;
08104 uint64_t skid_max_cnt : 2;
08105 uint64_t fcs_sop_off : 8;
08106 uint64_t fcs_ena : 1;
08107 uint64_t min_pad_ena : 1;
08108 uint64_t reserved_17_63 : 47;
08109 #endif
08110 } s;
08111 struct cvmx_pko_macx_cfg_s cn73xx;
08112 struct cvmx_pko_macx_cfg_s cn78xx;
08113 struct cvmx_pko_macx_cfg_s cn78xxp1;
08114 struct cvmx_pko_macx_cfg_s cnf75xx;
08115 };
08116 typedef union cvmx_pko_macx_cfg cvmx_pko_macx_cfg_t;
08117
08118
08119
08120
08121 union cvmx_pko_mci0_cred_cntx {
08122 uint64_t u64;
08123 struct cvmx_pko_mci0_cred_cntx_s {
08124 #ifdef __BIG_ENDIAN_BITFIELD
08125 uint64_t reserved_13_63 : 51;
08126 uint64_t cred_cnt : 13;
08127 #else
08128 uint64_t cred_cnt : 13;
08129 uint64_t reserved_13_63 : 51;
08130 #endif
08131 } s;
08132 struct cvmx_pko_mci0_cred_cntx_s cn78xx;
08133 struct cvmx_pko_mci0_cred_cntx_s cn78xxp1;
08134 };
08135 typedef union cvmx_pko_mci0_cred_cntx cvmx_pko_mci0_cred_cntx_t;
08136
08137
08138
08139
08140 union cvmx_pko_mci0_max_credx {
08141 uint64_t u64;
08142 struct cvmx_pko_mci0_max_credx_s {
08143 #ifdef __BIG_ENDIAN_BITFIELD
08144 uint64_t reserved_12_63 : 52;
08145 uint64_t max_cred_lim : 12;
08146
08147
08148 #else
08149 uint64_t max_cred_lim : 12;
08150 uint64_t reserved_12_63 : 52;
08151 #endif
08152 } s;
08153 struct cvmx_pko_mci0_max_credx_s cn78xx;
08154 struct cvmx_pko_mci0_max_credx_s cn78xxp1;
08155 };
08156 typedef union cvmx_pko_mci0_max_credx cvmx_pko_mci0_max_credx_t;
08157
08158
08159
08160
08161 union cvmx_pko_mci1_cred_cntx {
08162 uint64_t u64;
08163 struct cvmx_pko_mci1_cred_cntx_s {
08164 #ifdef __BIG_ENDIAN_BITFIELD
08165 uint64_t reserved_13_63 : 51;
08166 uint64_t cred_cnt : 13;
08167 #else
08168 uint64_t cred_cnt : 13;
08169 uint64_t reserved_13_63 : 51;
08170 #endif
08171 } s;
08172 struct cvmx_pko_mci1_cred_cntx_s cn73xx;
08173 struct cvmx_pko_mci1_cred_cntx_s cn78xx;
08174 struct cvmx_pko_mci1_cred_cntx_s cn78xxp1;
08175 struct cvmx_pko_mci1_cred_cntx_s cnf75xx;
08176 };
08177 typedef union cvmx_pko_mci1_cred_cntx cvmx_pko_mci1_cred_cntx_t;
08178
08179
08180
08181
08182 union cvmx_pko_mci1_max_credx {
08183 uint64_t u64;
08184 struct cvmx_pko_mci1_max_credx_s {
08185 #ifdef __BIG_ENDIAN_BITFIELD
08186 uint64_t reserved_12_63 : 52;
08187 uint64_t max_cred_lim : 12;
08188
08189 #else
08190 uint64_t max_cred_lim : 12;
08191 uint64_t reserved_12_63 : 52;
08192 #endif
08193 } s;
08194 struct cvmx_pko_mci1_max_credx_s cn73xx;
08195 struct cvmx_pko_mci1_max_credx_s cn78xx;
08196 struct cvmx_pko_mci1_max_credx_s cn78xxp1;
08197 struct cvmx_pko_mci1_max_credx_s cnf75xx;
08198 };
08199 typedef union cvmx_pko_mci1_max_credx cvmx_pko_mci1_max_credx_t;
08200
08201
08202
08203
08204
08205
08206
08207
08208
08209
08210
08211 union cvmx_pko_mem_count0 {
08212 uint64_t u64;
08213 struct cvmx_pko_mem_count0_s {
08214 #ifdef __BIG_ENDIAN_BITFIELD
08215 uint64_t reserved_32_63 : 32;
08216 uint64_t count : 32;
08217 #else
08218 uint64_t count : 32;
08219 uint64_t reserved_32_63 : 32;
08220 #endif
08221 } s;
08222 struct cvmx_pko_mem_count0_s cn30xx;
08223 struct cvmx_pko_mem_count0_s cn31xx;
08224 struct cvmx_pko_mem_count0_s cn38xx;
08225 struct cvmx_pko_mem_count0_s cn38xxp2;
08226 struct cvmx_pko_mem_count0_s cn50xx;
08227 struct cvmx_pko_mem_count0_s cn52xx;
08228 struct cvmx_pko_mem_count0_s cn52xxp1;
08229 struct cvmx_pko_mem_count0_s cn56xx;
08230 struct cvmx_pko_mem_count0_s cn56xxp1;
08231 struct cvmx_pko_mem_count0_s cn58xx;
08232 struct cvmx_pko_mem_count0_s cn58xxp1;
08233 struct cvmx_pko_mem_count0_s cn61xx;
08234 struct cvmx_pko_mem_count0_s cn63xx;
08235 struct cvmx_pko_mem_count0_s cn63xxp1;
08236 struct cvmx_pko_mem_count0_s cn66xx;
08237 struct cvmx_pko_mem_count0_s cn68xx;
08238 struct cvmx_pko_mem_count0_s cn68xxp1;
08239 struct cvmx_pko_mem_count0_s cn70xx;
08240 struct cvmx_pko_mem_count0_s cn70xxp1;
08241 struct cvmx_pko_mem_count0_s cnf71xx;
08242 };
08243 typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t;
08244
08245
08246
08247
08248
08249
08250
08251
08252
08253
08254
08255 union cvmx_pko_mem_count1 {
08256 uint64_t u64;
08257 struct cvmx_pko_mem_count1_s {
08258 #ifdef __BIG_ENDIAN_BITFIELD
08259 uint64_t reserved_48_63 : 16;
08260 uint64_t count : 48;
08261 #else
08262 uint64_t count : 48;
08263 uint64_t reserved_48_63 : 16;
08264 #endif
08265 } s;
08266 struct cvmx_pko_mem_count1_s cn30xx;
08267 struct cvmx_pko_mem_count1_s cn31xx;
08268 struct cvmx_pko_mem_count1_s cn38xx;
08269 struct cvmx_pko_mem_count1_s cn38xxp2;
08270 struct cvmx_pko_mem_count1_s cn50xx;
08271 struct cvmx_pko_mem_count1_s cn52xx;
08272 struct cvmx_pko_mem_count1_s cn52xxp1;
08273 struct cvmx_pko_mem_count1_s cn56xx;
08274 struct cvmx_pko_mem_count1_s cn56xxp1;
08275 struct cvmx_pko_mem_count1_s cn58xx;
08276 struct cvmx_pko_mem_count1_s cn58xxp1;
08277 struct cvmx_pko_mem_count1_s cn61xx;
08278 struct cvmx_pko_mem_count1_s cn63xx;
08279 struct cvmx_pko_mem_count1_s cn63xxp1;
08280 struct cvmx_pko_mem_count1_s cn66xx;
08281 struct cvmx_pko_mem_count1_s cn68xx;
08282 struct cvmx_pko_mem_count1_s cn68xxp1;
08283 struct cvmx_pko_mem_count1_s cn70xx;
08284 struct cvmx_pko_mem_count1_s cn70xxp1;
08285 struct cvmx_pko_mem_count1_s cnf71xx;
08286 };
08287 typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t;
08288
08289
08290
08291
08292
08293
08294
08295
08296
08297 union cvmx_pko_mem_debug0 {
08298 uint64_t u64;
08299 struct cvmx_pko_mem_debug0_s {
08300 #ifdef __BIG_ENDIAN_BITFIELD
08301 uint64_t fau : 28;
08302 uint64_t cmd : 14;
08303 uint64_t segs : 6;
08304 uint64_t size : 16;
08305 #else
08306 uint64_t size : 16;
08307 uint64_t segs : 6;
08308 uint64_t cmd : 14;
08309 uint64_t fau : 28;
08310 #endif
08311 } s;
08312 struct cvmx_pko_mem_debug0_s cn30xx;
08313 struct cvmx_pko_mem_debug0_s cn31xx;
08314 struct cvmx_pko_mem_debug0_s cn38xx;
08315 struct cvmx_pko_mem_debug0_s cn38xxp2;
08316 struct cvmx_pko_mem_debug0_s cn50xx;
08317 struct cvmx_pko_mem_debug0_s cn52xx;
08318 struct cvmx_pko_mem_debug0_s cn52xxp1;
08319 struct cvmx_pko_mem_debug0_s cn56xx;
08320 struct cvmx_pko_mem_debug0_s cn56xxp1;
08321 struct cvmx_pko_mem_debug0_s cn58xx;
08322 struct cvmx_pko_mem_debug0_s cn58xxp1;
08323 struct cvmx_pko_mem_debug0_s cn61xx;
08324 struct cvmx_pko_mem_debug0_s cn63xx;
08325 struct cvmx_pko_mem_debug0_s cn63xxp1;
08326 struct cvmx_pko_mem_debug0_s cn66xx;
08327 struct cvmx_pko_mem_debug0_s cn68xx;
08328 struct cvmx_pko_mem_debug0_s cn68xxp1;
08329 struct cvmx_pko_mem_debug0_s cn70xx;
08330 struct cvmx_pko_mem_debug0_s cn70xxp1;
08331 struct cvmx_pko_mem_debug0_s cnf71xx;
08332 };
08333 typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t;
08334
08335
08336
08337
08338
08339
08340
08341
08342
08343 union cvmx_pko_mem_debug1 {
08344 uint64_t u64;
08345 struct cvmx_pko_mem_debug1_s {
08346 #ifdef __BIG_ENDIAN_BITFIELD
08347 uint64_t i : 1;
08348 uint64_t back : 4;
08349 uint64_t pool : 3;
08350 uint64_t size : 16;
08351 uint64_t ptr : 40;
08352 #else
08353 uint64_t ptr : 40;
08354 uint64_t size : 16;
08355 uint64_t pool : 3;
08356 uint64_t back : 4;
08357 uint64_t i : 1;
08358 #endif
08359 } s;
08360 struct cvmx_pko_mem_debug1_s cn30xx;
08361 struct cvmx_pko_mem_debug1_s cn31xx;
08362 struct cvmx_pko_mem_debug1_s cn38xx;
08363 struct cvmx_pko_mem_debug1_s cn38xxp2;
08364 struct cvmx_pko_mem_debug1_s cn50xx;
08365 struct cvmx_pko_mem_debug1_s cn52xx;
08366 struct cvmx_pko_mem_debug1_s cn52xxp1;
08367 struct cvmx_pko_mem_debug1_s cn56xx;
08368 struct cvmx_pko_mem_debug1_s cn56xxp1;
08369 struct cvmx_pko_mem_debug1_s cn58xx;
08370 struct cvmx_pko_mem_debug1_s cn58xxp1;
08371 struct cvmx_pko_mem_debug1_s cn61xx;
08372 struct cvmx_pko_mem_debug1_s cn63xx;
08373 struct cvmx_pko_mem_debug1_s cn63xxp1;
08374 struct cvmx_pko_mem_debug1_s cn66xx;
08375 struct cvmx_pko_mem_debug1_s cn68xx;
08376 struct cvmx_pko_mem_debug1_s cn68xxp1;
08377 struct cvmx_pko_mem_debug1_s cn70xx;
08378 struct cvmx_pko_mem_debug1_s cn70xxp1;
08379 struct cvmx_pko_mem_debug1_s cnf71xx;
08380 };
08381 typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t;
08382
08383
08384
08385
08386
08387
08388
08389
08390
08391 union cvmx_pko_mem_debug10 {
08392 uint64_t u64;
08393 struct cvmx_pko_mem_debug10_s {
08394 #ifdef __BIG_ENDIAN_BITFIELD
08395 uint64_t reserved_0_63 : 64;
08396 #else
08397 uint64_t reserved_0_63 : 64;
08398 #endif
08399 } s;
08400 struct cvmx_pko_mem_debug10_cn30xx {
08401 #ifdef __BIG_ENDIAN_BITFIELD
08402 uint64_t fau : 28;
08403 uint64_t cmd : 14;
08404 uint64_t segs : 6;
08405 uint64_t size : 16;
08406 #else
08407 uint64_t size : 16;
08408 uint64_t segs : 6;
08409 uint64_t cmd : 14;
08410 uint64_t fau : 28;
08411 #endif
08412 } cn30xx;
08413 struct cvmx_pko_mem_debug10_cn30xx cn31xx;
08414 struct cvmx_pko_mem_debug10_cn30xx cn38xx;
08415 struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
08416 struct cvmx_pko_mem_debug10_cn50xx {
08417 #ifdef __BIG_ENDIAN_BITFIELD
08418 uint64_t reserved_49_63 : 15;
08419 uint64_t ptrs1 : 17;
08420 uint64_t reserved_17_31 : 15;
08421 uint64_t ptrs2 : 17;
08422 #else
08423 uint64_t ptrs2 : 17;
08424 uint64_t reserved_17_31 : 15;
08425 uint64_t ptrs1 : 17;
08426 uint64_t reserved_49_63 : 15;
08427 #endif
08428 } cn50xx;
08429 struct cvmx_pko_mem_debug10_cn50xx cn52xx;
08430 struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
08431 struct cvmx_pko_mem_debug10_cn50xx cn56xx;
08432 struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
08433 struct cvmx_pko_mem_debug10_cn50xx cn58xx;
08434 struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
08435 struct cvmx_pko_mem_debug10_cn50xx cn61xx;
08436 struct cvmx_pko_mem_debug10_cn50xx cn63xx;
08437 struct cvmx_pko_mem_debug10_cn50xx cn63xxp1;
08438 struct cvmx_pko_mem_debug10_cn50xx cn66xx;
08439 struct cvmx_pko_mem_debug10_cn50xx cn68xx;
08440 struct cvmx_pko_mem_debug10_cn50xx cn68xxp1;
08441 struct cvmx_pko_mem_debug10_cn50xx cn70xx;
08442 struct cvmx_pko_mem_debug10_cn50xx cn70xxp1;
08443 struct cvmx_pko_mem_debug10_cn50xx cnf71xx;
08444 };
08445 typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t;
08446
08447
08448
08449
08450
08451
08452
08453
08454
08455 union cvmx_pko_mem_debug11 {
08456 uint64_t u64;
08457 struct cvmx_pko_mem_debug11_s {
08458 #ifdef __BIG_ENDIAN_BITFIELD
08459 uint64_t i : 1;
08460 uint64_t back : 4;
08461 uint64_t pool : 3;
08462 uint64_t size : 16;
08463 uint64_t reserved_0_39 : 40;
08464 #else
08465 uint64_t reserved_0_39 : 40;
08466 uint64_t size : 16;
08467 uint64_t pool : 3;
08468 uint64_t back : 4;
08469 uint64_t i : 1;
08470 #endif
08471 } s;
08472 struct cvmx_pko_mem_debug11_cn30xx {
08473 #ifdef __BIG_ENDIAN_BITFIELD
08474 uint64_t i : 1;
08475 uint64_t back : 4;
08476 uint64_t pool : 3;
08477 uint64_t size : 16;
08478 uint64_t ptr : 40;
08479 #else
08480 uint64_t ptr : 40;
08481 uint64_t size : 16;
08482 uint64_t pool : 3;
08483 uint64_t back : 4;
08484 uint64_t i : 1;
08485 #endif
08486 } cn30xx;
08487 struct cvmx_pko_mem_debug11_cn30xx cn31xx;
08488 struct cvmx_pko_mem_debug11_cn30xx cn38xx;
08489 struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
08490 struct cvmx_pko_mem_debug11_cn50xx {
08491 #ifdef __BIG_ENDIAN_BITFIELD
08492 uint64_t reserved_23_63 : 41;
08493 uint64_t maj : 1;
08494 uint64_t uid : 3;
08495 uint64_t sop : 1;
08496 uint64_t len : 1;
08497 uint64_t chk : 1;
08498 uint64_t cnt : 13;
08499 uint64_t mod : 3;
08500 #else
08501 uint64_t mod : 3;
08502 uint64_t cnt : 13;
08503 uint64_t chk : 1;
08504 uint64_t len : 1;
08505 uint64_t sop : 1;
08506 uint64_t uid : 3;
08507 uint64_t maj : 1;
08508 uint64_t reserved_23_63 : 41;
08509 #endif
08510 } cn50xx;
08511 struct cvmx_pko_mem_debug11_cn50xx cn52xx;
08512 struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
08513 struct cvmx_pko_mem_debug11_cn50xx cn56xx;
08514 struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
08515 struct cvmx_pko_mem_debug11_cn50xx cn58xx;
08516 struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
08517 struct cvmx_pko_mem_debug11_cn50xx cn61xx;
08518 struct cvmx_pko_mem_debug11_cn50xx cn63xx;
08519 struct cvmx_pko_mem_debug11_cn50xx cn63xxp1;
08520 struct cvmx_pko_mem_debug11_cn50xx cn66xx;
08521 struct cvmx_pko_mem_debug11_cn50xx cn68xx;
08522 struct cvmx_pko_mem_debug11_cn50xx cn68xxp1;
08523 struct cvmx_pko_mem_debug11_cn50xx cn70xx;
08524 struct cvmx_pko_mem_debug11_cn50xx cn70xxp1;
08525 struct cvmx_pko_mem_debug11_cn50xx cnf71xx;
08526 };
08527 typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t;
08528
08529
08530
08531
08532
08533
08534
08535
08536
08537 union cvmx_pko_mem_debug12 {
08538 uint64_t u64;
08539 struct cvmx_pko_mem_debug12_s {
08540 #ifdef __BIG_ENDIAN_BITFIELD
08541 uint64_t reserved_0_63 : 64;
08542 #else
08543 uint64_t reserved_0_63 : 64;
08544 #endif
08545 } s;
08546 struct cvmx_pko_mem_debug12_cn30xx {
08547 #ifdef __BIG_ENDIAN_BITFIELD
08548 uint64_t data : 64;
08549 #else
08550 uint64_t data : 64;
08551 #endif
08552 } cn30xx;
08553 struct cvmx_pko_mem_debug12_cn30xx cn31xx;
08554 struct cvmx_pko_mem_debug12_cn30xx cn38xx;
08555 struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
08556 struct cvmx_pko_mem_debug12_cn50xx {
08557 #ifdef __BIG_ENDIAN_BITFIELD
08558 uint64_t fau : 28;
08559 uint64_t cmd : 14;
08560 uint64_t segs : 6;
08561 uint64_t size : 16;
08562 #else
08563 uint64_t size : 16;
08564 uint64_t segs : 6;
08565 uint64_t cmd : 14;
08566 uint64_t fau : 28;
08567 #endif
08568 } cn50xx;
08569 struct cvmx_pko_mem_debug12_cn50xx cn52xx;
08570 struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
08571 struct cvmx_pko_mem_debug12_cn50xx cn56xx;
08572 struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
08573 struct cvmx_pko_mem_debug12_cn50xx cn58xx;
08574 struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
08575 struct cvmx_pko_mem_debug12_cn50xx cn61xx;
08576 struct cvmx_pko_mem_debug12_cn50xx cn63xx;
08577 struct cvmx_pko_mem_debug12_cn50xx cn63xxp1;
08578 struct cvmx_pko_mem_debug12_cn50xx cn66xx;
08579 struct cvmx_pko_mem_debug12_cn68xx {
08580 #ifdef __BIG_ENDIAN_BITFIELD
08581 uint64_t state : 64;
08582 #else
08583 uint64_t state : 64;
08584 #endif
08585 } cn68xx;
08586 struct cvmx_pko_mem_debug12_cn68xx cn68xxp1;
08587 struct cvmx_pko_mem_debug12_cn50xx cn70xx;
08588 struct cvmx_pko_mem_debug12_cn50xx cn70xxp1;
08589 struct cvmx_pko_mem_debug12_cn50xx cnf71xx;
08590 };
08591 typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t;
08592
08593
08594
08595
08596
08597
08598
08599
08600
08601 union cvmx_pko_mem_debug13 {
08602 uint64_t u64;
08603 struct cvmx_pko_mem_debug13_s {
08604 #ifdef __BIG_ENDIAN_BITFIELD
08605 uint64_t reserved_0_63 : 64;
08606 #else
08607 uint64_t reserved_0_63 : 64;
08608 #endif
08609 } s;
08610 struct cvmx_pko_mem_debug13_cn30xx {
08611 #ifdef __BIG_ENDIAN_BITFIELD
08612 uint64_t reserved_51_63 : 13;
08613 uint64_t widx : 17;
08614 uint64_t ridx2 : 17;
08615 uint64_t widx2 : 17;
08616 #else
08617 uint64_t widx2 : 17;
08618 uint64_t ridx2 : 17;
08619 uint64_t widx : 17;
08620 uint64_t reserved_51_63 : 13;
08621 #endif
08622 } cn30xx;
08623 struct cvmx_pko_mem_debug13_cn30xx cn31xx;
08624 struct cvmx_pko_mem_debug13_cn30xx cn38xx;
08625 struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
08626 struct cvmx_pko_mem_debug13_cn50xx {
08627 #ifdef __BIG_ENDIAN_BITFIELD
08628 uint64_t i : 1;
08629 uint64_t back : 4;
08630 uint64_t pool : 3;
08631 uint64_t size : 16;
08632 uint64_t ptr : 40;
08633 #else
08634 uint64_t ptr : 40;
08635 uint64_t size : 16;
08636 uint64_t pool : 3;
08637 uint64_t back : 4;
08638 uint64_t i : 1;
08639 #endif
08640 } cn50xx;
08641 struct cvmx_pko_mem_debug13_cn50xx cn52xx;
08642 struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
08643 struct cvmx_pko_mem_debug13_cn50xx cn56xx;
08644 struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
08645 struct cvmx_pko_mem_debug13_cn50xx cn58xx;
08646 struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
08647 struct cvmx_pko_mem_debug13_cn50xx cn61xx;
08648 struct cvmx_pko_mem_debug13_cn50xx cn63xx;
08649 struct cvmx_pko_mem_debug13_cn50xx cn63xxp1;
08650 struct cvmx_pko_mem_debug13_cn50xx cn66xx;
08651 struct cvmx_pko_mem_debug13_cn68xx {
08652 #ifdef __BIG_ENDIAN_BITFIELD
08653 uint64_t state : 64;
08654 #else
08655 uint64_t state : 64;
08656 #endif
08657 } cn68xx;
08658 struct cvmx_pko_mem_debug13_cn68xx cn68xxp1;
08659 struct cvmx_pko_mem_debug13_cn50xx cn70xx;
08660 struct cvmx_pko_mem_debug13_cn50xx cn70xxp1;
08661 struct cvmx_pko_mem_debug13_cn50xx cnf71xx;
08662 };
08663 typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t;
08664
08665
08666
08667
08668
08669
08670
08671
08672
08673 union cvmx_pko_mem_debug14 {
08674 uint64_t u64;
08675 struct cvmx_pko_mem_debug14_s {
08676 #ifdef __BIG_ENDIAN_BITFIELD
08677 uint64_t reserved_0_63 : 64;
08678 #else
08679 uint64_t reserved_0_63 : 64;
08680 #endif
08681 } s;
08682 struct cvmx_pko_mem_debug14_cn30xx {
08683 #ifdef __BIG_ENDIAN_BITFIELD
08684 uint64_t reserved_17_63 : 47;
08685 uint64_t ridx : 17;
08686 #else
08687 uint64_t ridx : 17;
08688 uint64_t reserved_17_63 : 47;
08689 #endif
08690 } cn30xx;
08691 struct cvmx_pko_mem_debug14_cn30xx cn31xx;
08692 struct cvmx_pko_mem_debug14_cn30xx cn38xx;
08693 struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
08694 struct cvmx_pko_mem_debug14_cn52xx {
08695 #ifdef __BIG_ENDIAN_BITFIELD
08696 uint64_t data : 64;
08697 #else
08698 uint64_t data : 64;
08699 #endif
08700 } cn52xx;
08701 struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
08702 struct cvmx_pko_mem_debug14_cn52xx cn56xx;
08703 struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
08704 struct cvmx_pko_mem_debug14_cn52xx cn61xx;
08705 struct cvmx_pko_mem_debug14_cn52xx cn63xx;
08706 struct cvmx_pko_mem_debug14_cn52xx cn63xxp1;
08707 struct cvmx_pko_mem_debug14_cn52xx cn66xx;
08708 struct cvmx_pko_mem_debug14_cn52xx cn70xx;
08709 struct cvmx_pko_mem_debug14_cn52xx cn70xxp1;
08710 struct cvmx_pko_mem_debug14_cn52xx cnf71xx;
08711 };
08712 typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t;
08713
08714
08715
08716
08717
08718
08719
08720
08721
08722 union cvmx_pko_mem_debug2 {
08723 uint64_t u64;
08724 struct cvmx_pko_mem_debug2_s {
08725 #ifdef __BIG_ENDIAN_BITFIELD
08726 uint64_t i : 1;
08727 uint64_t back : 4;
08728 uint64_t pool : 3;
08729 uint64_t size : 16;
08730 uint64_t ptr : 40;
08731 #else
08732 uint64_t ptr : 40;
08733 uint64_t size : 16;
08734 uint64_t pool : 3;
08735 uint64_t back : 4;
08736 uint64_t i : 1;
08737 #endif
08738 } s;
08739 struct cvmx_pko_mem_debug2_s cn30xx;
08740 struct cvmx_pko_mem_debug2_s cn31xx;
08741 struct cvmx_pko_mem_debug2_s cn38xx;
08742 struct cvmx_pko_mem_debug2_s cn38xxp2;
08743 struct cvmx_pko_mem_debug2_s cn50xx;
08744 struct cvmx_pko_mem_debug2_s cn52xx;
08745 struct cvmx_pko_mem_debug2_s cn52xxp1;
08746 struct cvmx_pko_mem_debug2_s cn56xx;
08747 struct cvmx_pko_mem_debug2_s cn56xxp1;
08748 struct cvmx_pko_mem_debug2_s cn58xx;
08749 struct cvmx_pko_mem_debug2_s cn58xxp1;
08750 struct cvmx_pko_mem_debug2_s cn61xx;
08751 struct cvmx_pko_mem_debug2_s cn63xx;
08752 struct cvmx_pko_mem_debug2_s cn63xxp1;
08753 struct cvmx_pko_mem_debug2_s cn66xx;
08754 struct cvmx_pko_mem_debug2_s cn68xx;
08755 struct cvmx_pko_mem_debug2_s cn68xxp1;
08756 struct cvmx_pko_mem_debug2_s cn70xx;
08757 struct cvmx_pko_mem_debug2_s cn70xxp1;
08758 struct cvmx_pko_mem_debug2_s cnf71xx;
08759 };
08760 typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t;
08761
08762
08763
08764
08765
08766
08767
08768
08769
08770 union cvmx_pko_mem_debug3 {
08771 uint64_t u64;
08772 struct cvmx_pko_mem_debug3_s {
08773 #ifdef __BIG_ENDIAN_BITFIELD
08774 uint64_t reserved_0_63 : 64;
08775 #else
08776 uint64_t reserved_0_63 : 64;
08777 #endif
08778 } s;
08779 struct cvmx_pko_mem_debug3_cn30xx {
08780 #ifdef __BIG_ENDIAN_BITFIELD
08781 uint64_t i : 1;
08782 uint64_t back : 4;
08783 uint64_t pool : 3;
08784 uint64_t size : 16;
08785 uint64_t ptr : 40;
08786 #else
08787 uint64_t ptr : 40;
08788 uint64_t size : 16;
08789 uint64_t pool : 3;
08790 uint64_t back : 4;
08791 uint64_t i : 1;
08792 #endif
08793 } cn30xx;
08794 struct cvmx_pko_mem_debug3_cn30xx cn31xx;
08795 struct cvmx_pko_mem_debug3_cn30xx cn38xx;
08796 struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
08797 struct cvmx_pko_mem_debug3_cn50xx {
08798 #ifdef __BIG_ENDIAN_BITFIELD
08799 uint64_t data : 64;
08800 #else
08801 uint64_t data : 64;
08802 #endif
08803 } cn50xx;
08804 struct cvmx_pko_mem_debug3_cn50xx cn52xx;
08805 struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
08806 struct cvmx_pko_mem_debug3_cn50xx cn56xx;
08807 struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
08808 struct cvmx_pko_mem_debug3_cn50xx cn58xx;
08809 struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
08810 struct cvmx_pko_mem_debug3_cn50xx cn61xx;
08811 struct cvmx_pko_mem_debug3_cn50xx cn63xx;
08812 struct cvmx_pko_mem_debug3_cn50xx cn63xxp1;
08813 struct cvmx_pko_mem_debug3_cn50xx cn66xx;
08814 struct cvmx_pko_mem_debug3_cn50xx cn68xx;
08815 struct cvmx_pko_mem_debug3_cn50xx cn68xxp1;
08816 struct cvmx_pko_mem_debug3_cn50xx cn70xx;
08817 struct cvmx_pko_mem_debug3_cn50xx cn70xxp1;
08818 struct cvmx_pko_mem_debug3_cn50xx cnf71xx;
08819 };
08820 typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t;
08821
08822
08823
08824
08825
08826
08827
08828
08829
08830 union cvmx_pko_mem_debug4 {
08831 uint64_t u64;
08832 struct cvmx_pko_mem_debug4_s {
08833 #ifdef __BIG_ENDIAN_BITFIELD
08834 uint64_t reserved_0_63 : 64;
08835 #else
08836 uint64_t reserved_0_63 : 64;
08837 #endif
08838 } s;
08839 struct cvmx_pko_mem_debug4_cn30xx {
08840 #ifdef __BIG_ENDIAN_BITFIELD
08841 uint64_t data : 64;
08842 #else
08843 uint64_t data : 64;
08844 #endif
08845 } cn30xx;
08846 struct cvmx_pko_mem_debug4_cn30xx cn31xx;
08847 struct cvmx_pko_mem_debug4_cn30xx cn38xx;
08848 struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
08849 struct cvmx_pko_mem_debug4_cn50xx {
08850 #ifdef __BIG_ENDIAN_BITFIELD
08851 uint64_t cmnd_segs : 3;
08852 uint64_t cmnd_siz : 16;
08853 uint64_t cmnd_off : 6;
08854 uint64_t uid : 3;
08855 uint64_t dread_sop : 1;
08856 uint64_t init_dwrite : 1;
08857 uint64_t chk_once : 1;
08858 uint64_t chk_mode : 1;
08859 uint64_t active : 1;
08860 uint64_t static_p : 1;
08861 uint64_t qos : 3;
08862 uint64_t qcb_ridx : 5;
08863 uint64_t qid_off_max : 4;
08864 uint64_t qid_off : 4;
08865 uint64_t qid_base : 8;
08866 uint64_t wait : 1;
08867 uint64_t minor : 2;
08868 uint64_t major : 3;
08869 #else
08870 uint64_t major : 3;
08871 uint64_t minor : 2;
08872 uint64_t wait : 1;
08873 uint64_t qid_base : 8;
08874 uint64_t qid_off : 4;
08875 uint64_t qid_off_max : 4;
08876 uint64_t qcb_ridx : 5;
08877 uint64_t qos : 3;
08878 uint64_t static_p : 1;
08879 uint64_t active : 1;
08880 uint64_t chk_mode : 1;
08881 uint64_t chk_once : 1;
08882 uint64_t init_dwrite : 1;
08883 uint64_t dread_sop : 1;
08884 uint64_t uid : 3;
08885 uint64_t cmnd_off : 6;
08886 uint64_t cmnd_siz : 16;
08887 uint64_t cmnd_segs : 3;
08888 #endif
08889 } cn50xx;
08890 struct cvmx_pko_mem_debug4_cn52xx {
08891 #ifdef __BIG_ENDIAN_BITFIELD
08892 uint64_t curr_siz : 8;
08893 uint64_t curr_off : 16;
08894 uint64_t cmnd_segs : 6;
08895 uint64_t cmnd_siz : 16;
08896 uint64_t cmnd_off : 6;
08897 uint64_t uid : 2;
08898 uint64_t dread_sop : 1;
08899 uint64_t init_dwrite : 1;
08900 uint64_t chk_once : 1;
08901 uint64_t chk_mode : 1;
08902 uint64_t wait : 1;
08903 uint64_t minor : 2;
08904 uint64_t major : 3;
08905 #else
08906 uint64_t major : 3;
08907 uint64_t minor : 2;
08908 uint64_t wait : 1;
08909 uint64_t chk_mode : 1;
08910 uint64_t chk_once : 1;
08911 uint64_t init_dwrite : 1;
08912 uint64_t dread_sop : 1;
08913 uint64_t uid : 2;
08914 uint64_t cmnd_off : 6;
08915 uint64_t cmnd_siz : 16;
08916 uint64_t cmnd_segs : 6;
08917 uint64_t curr_off : 16;
08918 uint64_t curr_siz : 8;
08919 #endif
08920 } cn52xx;
08921 struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
08922 struct cvmx_pko_mem_debug4_cn52xx cn56xx;
08923 struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
08924 struct cvmx_pko_mem_debug4_cn50xx cn58xx;
08925 struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
08926 struct cvmx_pko_mem_debug4_cn52xx cn61xx;
08927 struct cvmx_pko_mem_debug4_cn52xx cn63xx;
08928 struct cvmx_pko_mem_debug4_cn52xx cn63xxp1;
08929 struct cvmx_pko_mem_debug4_cn52xx cn66xx;
08930 struct cvmx_pko_mem_debug4_cn68xx {
08931 #ifdef __BIG_ENDIAN_BITFIELD
08932 uint64_t curr_siz : 9;
08933 uint64_t curr_off : 16;
08934 uint64_t cmnd_segs : 6;
08935 uint64_t cmnd_siz : 16;
08936 uint64_t cmnd_off : 6;
08937 uint64_t dread_sop : 1;
08938 uint64_t init_dwrite : 1;
08939 uint64_t chk_once : 1;
08940 uint64_t chk_mode : 1;
08941 uint64_t reserved_6_6 : 1;
08942 uint64_t minor : 2;
08943 uint64_t major : 4;
08944 #else
08945 uint64_t major : 4;
08946 uint64_t minor : 2;
08947 uint64_t reserved_6_6 : 1;
08948 uint64_t chk_mode : 1;
08949 uint64_t chk_once : 1;
08950 uint64_t init_dwrite : 1;
08951 uint64_t dread_sop : 1;
08952 uint64_t cmnd_off : 6;
08953 uint64_t cmnd_siz : 16;
08954 uint64_t cmnd_segs : 6;
08955 uint64_t curr_off : 16;
08956 uint64_t curr_siz : 9;
08957 #endif
08958 } cn68xx;
08959 struct cvmx_pko_mem_debug4_cn68xx cn68xxp1;
08960 struct cvmx_pko_mem_debug4_cn52xx cn70xx;
08961 struct cvmx_pko_mem_debug4_cn52xx cn70xxp1;
08962 struct cvmx_pko_mem_debug4_cn52xx cnf71xx;
08963 };
08964 typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t;
08965
08966
08967
08968
08969
08970
08971
08972
08973
08974 union cvmx_pko_mem_debug5 {
08975 uint64_t u64;
08976 struct cvmx_pko_mem_debug5_s {
08977 #ifdef __BIG_ENDIAN_BITFIELD
08978 uint64_t reserved_0_63 : 64;
08979 #else
08980 uint64_t reserved_0_63 : 64;
08981 #endif
08982 } s;
08983 struct cvmx_pko_mem_debug5_cn30xx {
08984 #ifdef __BIG_ENDIAN_BITFIELD
08985 uint64_t dwri_mod : 1;
08986 uint64_t dwri_sop : 1;
08987 uint64_t dwri_len : 1;
08988 uint64_t dwri_cnt : 13;
08989 uint64_t cmnd_siz : 16;
08990 uint64_t uid : 1;
08991 uint64_t xfer_wor : 1;
08992 uint64_t xfer_dwr : 1;
08993 uint64_t cbuf_fre : 1;
08994 uint64_t reserved_27_27 : 1;
08995 uint64_t chk_mode : 1;
08996 uint64_t active : 1;
08997 uint64_t qos : 3;
08998 uint64_t qcb_ridx : 5;
08999 uint64_t qid_off : 3;
09000 uint64_t qid_base : 7;
09001 uint64_t wait : 1;
09002 uint64_t minor : 2;
09003 uint64_t major : 4;
09004 #else
09005 uint64_t major : 4;
09006 uint64_t minor : 2;
09007 uint64_t wait : 1;
09008 uint64_t qid_base : 7;
09009 uint64_t qid_off : 3;
09010 uint64_t qcb_ridx : 5;
09011 uint64_t qos : 3;
09012 uint64_t active : 1;
09013 uint64_t chk_mode : 1;
09014 uint64_t reserved_27_27 : 1;
09015 uint64_t cbuf_fre : 1;
09016 uint64_t xfer_dwr : 1;
09017 uint64_t xfer_wor : 1;
09018 uint64_t uid : 1;
09019 uint64_t cmnd_siz : 16;
09020 uint64_t dwri_cnt : 13;
09021 uint64_t dwri_len : 1;
09022 uint64_t dwri_sop : 1;
09023 uint64_t dwri_mod : 1;
09024 #endif
09025 } cn30xx;
09026 struct cvmx_pko_mem_debug5_cn30xx cn31xx;
09027 struct cvmx_pko_mem_debug5_cn30xx cn38xx;
09028 struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
09029 struct cvmx_pko_mem_debug5_cn50xx {
09030 #ifdef __BIG_ENDIAN_BITFIELD
09031 uint64_t curr_ptr : 29;
09032 uint64_t curr_siz : 16;
09033 uint64_t curr_off : 16;
09034 uint64_t cmnd_segs : 3;
09035 #else
09036 uint64_t cmnd_segs : 3;
09037 uint64_t curr_off : 16;
09038 uint64_t curr_siz : 16;
09039 uint64_t curr_ptr : 29;
09040 #endif
09041 } cn50xx;
09042 struct cvmx_pko_mem_debug5_cn52xx {
09043 #ifdef __BIG_ENDIAN_BITFIELD
09044 uint64_t reserved_54_63 : 10;
09045 uint64_t nxt_inflt : 6;
09046 uint64_t curr_ptr : 40;
09047 uint64_t curr_siz : 8;
09048 #else
09049 uint64_t curr_siz : 8;
09050 uint64_t curr_ptr : 40;
09051 uint64_t nxt_inflt : 6;
09052 uint64_t reserved_54_63 : 10;
09053 #endif
09054 } cn52xx;
09055 struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
09056 struct cvmx_pko_mem_debug5_cn52xx cn56xx;
09057 struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
09058 struct cvmx_pko_mem_debug5_cn50xx cn58xx;
09059 struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
09060 struct cvmx_pko_mem_debug5_cn61xx {
09061 #ifdef __BIG_ENDIAN_BITFIELD
09062 uint64_t reserved_56_63 : 8;
09063 uint64_t ptp : 1;
09064 uint64_t major_3 : 1;
09065 uint64_t nxt_inflt : 6;
09066 uint64_t curr_ptr : 40;
09067 uint64_t curr_siz : 8;
09068 #else
09069 uint64_t curr_siz : 8;
09070 uint64_t curr_ptr : 40;
09071 uint64_t nxt_inflt : 6;
09072 uint64_t major_3 : 1;
09073 uint64_t ptp : 1;
09074 uint64_t reserved_56_63 : 8;
09075 #endif
09076 } cn61xx;
09077 struct cvmx_pko_mem_debug5_cn61xx cn63xx;
09078 struct cvmx_pko_mem_debug5_cn61xx cn63xxp1;
09079 struct cvmx_pko_mem_debug5_cn61xx cn66xx;
09080 struct cvmx_pko_mem_debug5_cn68xx {
09081 #ifdef __BIG_ENDIAN_BITFIELD
09082 uint64_t reserved_57_63 : 7;
09083 uint64_t uid : 3;
09084 uint64_t ptp : 1;
09085 uint64_t nxt_inflt : 6;
09086 uint64_t curr_ptr : 40;
09087 uint64_t curr_siz : 7;
09088 #else
09089 uint64_t curr_siz : 7;
09090 uint64_t curr_ptr : 40;
09091 uint64_t nxt_inflt : 6;
09092 uint64_t ptp : 1;
09093 uint64_t uid : 3;
09094 uint64_t reserved_57_63 : 7;
09095 #endif
09096 } cn68xx;
09097 struct cvmx_pko_mem_debug5_cn68xx cn68xxp1;
09098 struct cvmx_pko_mem_debug5_cn61xx cn70xx;
09099 struct cvmx_pko_mem_debug5_cn61xx cn70xxp1;
09100 struct cvmx_pko_mem_debug5_cn61xx cnf71xx;
09101 };
09102 typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t;
09103
09104
09105
09106
09107
09108
09109
09110
09111
09112 union cvmx_pko_mem_debug6 {
09113 uint64_t u64;
09114 struct cvmx_pko_mem_debug6_s {
09115 #ifdef __BIG_ENDIAN_BITFIELD
09116 uint64_t reserved_38_63 : 26;
09117 uint64_t qos_active : 1;
09118 uint64_t reserved_0_36 : 37;
09119 #else
09120 uint64_t reserved_0_36 : 37;
09121 uint64_t qos_active : 1;
09122 uint64_t reserved_38_63 : 26;
09123 #endif
09124 } s;
09125 struct cvmx_pko_mem_debug6_cn30xx {
09126 #ifdef __BIG_ENDIAN_BITFIELD
09127 uint64_t reserved_11_63 : 53;
09128 uint64_t qid_offm : 3;
09129 uint64_t static_p : 1;
09130 uint64_t work_min : 3;
09131 uint64_t dwri_chk : 1;
09132 uint64_t dwri_uid : 1;
09133 uint64_t dwri_mod : 2;
09134 #else
09135 uint64_t dwri_mod : 2;
09136 uint64_t dwri_uid : 1;
09137 uint64_t dwri_chk : 1;
09138 uint64_t work_min : 3;
09139 uint64_t static_p : 1;
09140 uint64_t qid_offm : 3;
09141 uint64_t reserved_11_63 : 53;
09142 #endif
09143 } cn30xx;
09144 struct cvmx_pko_mem_debug6_cn30xx cn31xx;
09145 struct cvmx_pko_mem_debug6_cn30xx cn38xx;
09146 struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
09147 struct cvmx_pko_mem_debug6_cn50xx {
09148 #ifdef __BIG_ENDIAN_BITFIELD
09149 uint64_t reserved_11_63 : 53;
09150 uint64_t curr_ptr : 11;
09151 #else
09152 uint64_t curr_ptr : 11;
09153 uint64_t reserved_11_63 : 53;
09154 #endif
09155 } cn50xx;
09156 struct cvmx_pko_mem_debug6_cn52xx {
09157 #ifdef __BIG_ENDIAN_BITFIELD
09158 uint64_t reserved_37_63 : 27;
09159 uint64_t qid_offres : 4;
09160 uint64_t qid_offths : 4;
09161 uint64_t preempter : 1;
09162 uint64_t preemptee : 1;
09163 uint64_t preempted : 1;
09164 uint64_t active : 1;
09165 uint64_t statc : 1;
09166 uint64_t qos : 3;
09167 uint64_t qcb_ridx : 5;
09168 uint64_t qid_offmax : 4;
09169 uint64_t qid_off : 4;
09170 uint64_t qid_base : 8;
09171 #else
09172 uint64_t qid_base : 8;
09173 uint64_t qid_off : 4;
09174 uint64_t qid_offmax : 4;
09175 uint64_t qcb_ridx : 5;
09176 uint64_t qos : 3;
09177 uint64_t statc : 1;
09178 uint64_t active : 1;
09179 uint64_t preempted : 1;
09180 uint64_t preemptee : 1;
09181 uint64_t preempter : 1;
09182 uint64_t qid_offths : 4;
09183 uint64_t qid_offres : 4;
09184 uint64_t reserved_37_63 : 27;
09185 #endif
09186 } cn52xx;
09187 struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
09188 struct cvmx_pko_mem_debug6_cn52xx cn56xx;
09189 struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
09190 struct cvmx_pko_mem_debug6_cn50xx cn58xx;
09191 struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
09192 struct cvmx_pko_mem_debug6_cn52xx cn61xx;
09193 struct cvmx_pko_mem_debug6_cn52xx cn63xx;
09194 struct cvmx_pko_mem_debug6_cn52xx cn63xxp1;
09195 struct cvmx_pko_mem_debug6_cn52xx cn66xx;
09196 struct cvmx_pko_mem_debug6_cn68xx {
09197 #ifdef __BIG_ENDIAN_BITFIELD
09198 uint64_t reserved_38_63 : 26;
09199 uint64_t qos_active : 1;
09200 uint64_t qid_offths : 5;
09201 uint64_t preempter : 1;
09202 uint64_t preemptee : 1;
09203 uint64_t active : 1;
09204 uint64_t static_p : 1;
09205 uint64_t qos : 3;
09206 uint64_t qcb_ridx : 7;
09207 uint64_t qid_offmax : 5;
09208 uint64_t qid_off : 5;
09209 uint64_t qid_base : 8;
09210 #else
09211 uint64_t qid_base : 8;
09212 uint64_t qid_off : 5;
09213 uint64_t qid_offmax : 5;
09214 uint64_t qcb_ridx : 7;
09215 uint64_t qos : 3;
09216 uint64_t static_p : 1;
09217 uint64_t active : 1;
09218 uint64_t preemptee : 1;
09219 uint64_t preempter : 1;
09220 uint64_t qid_offths : 5;
09221 uint64_t qos_active : 1;
09222 uint64_t reserved_38_63 : 26;
09223 #endif
09224 } cn68xx;
09225 struct cvmx_pko_mem_debug6_cn68xx cn68xxp1;
09226 struct cvmx_pko_mem_debug6_cn70xx {
09227 #ifdef __BIG_ENDIAN_BITFIELD
09228 uint64_t reserved_63_37 : 27;
09229 uint64_t qid_offres : 4;
09230 uint64_t qid_offths : 4;
09231 uint64_t preempter : 1;
09232 uint64_t preemptee : 1;
09233 uint64_t preempted : 1;
09234 uint64_t active : 1;
09235 uint64_t staticb : 1;
09236 uint64_t qos : 3;
09237 uint64_t qcb_ridx : 5;
09238 uint64_t qid_offmax : 4;
09239 uint64_t qid_off : 4;
09240 uint64_t qid_base : 8;
09241 #else
09242 uint64_t qid_base : 8;
09243 uint64_t qid_off : 4;
09244 uint64_t qid_offmax : 4;
09245 uint64_t qcb_ridx : 5;
09246 uint64_t qos : 3;
09247 uint64_t staticb : 1;
09248 uint64_t active : 1;
09249 uint64_t preempted : 1;
09250 uint64_t preemptee : 1;
09251 uint64_t preempter : 1;
09252 uint64_t qid_offths : 4;
09253 uint64_t qid_offres : 4;
09254 uint64_t reserved_63_37 : 27;
09255 #endif
09256 } cn70xx;
09257 struct cvmx_pko_mem_debug6_cn70xx cn70xxp1;
09258 struct cvmx_pko_mem_debug6_cn52xx cnf71xx;
09259 };
09260 typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t;
09261
09262
09263
09264
09265
09266
09267
09268
09269
09270 union cvmx_pko_mem_debug7 {
09271 uint64_t u64;
09272 struct cvmx_pko_mem_debug7_s {
09273 #ifdef __BIG_ENDIAN_BITFIELD
09274 uint64_t reserved_0_63 : 64;
09275 #else
09276 uint64_t reserved_0_63 : 64;
09277 #endif
09278 } s;
09279 struct cvmx_pko_mem_debug7_cn30xx {
09280 #ifdef __BIG_ENDIAN_BITFIELD
09281 uint64_t reserved_58_63 : 6;
09282 uint64_t dwb : 9;
09283 uint64_t start : 33;
09284 uint64_t size : 16;
09285 #else
09286 uint64_t size : 16;
09287 uint64_t start : 33;
09288 uint64_t dwb : 9;
09289 uint64_t reserved_58_63 : 6;
09290 #endif
09291 } cn30xx;
09292 struct cvmx_pko_mem_debug7_cn30xx cn31xx;
09293 struct cvmx_pko_mem_debug7_cn30xx cn38xx;
09294 struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
09295 struct cvmx_pko_mem_debug7_cn50xx {
09296 #ifdef __BIG_ENDIAN_BITFIELD
09297 uint64_t qos : 5;
09298 uint64_t tail : 1;
09299 uint64_t buf_siz : 13;
09300 uint64_t buf_ptr : 33;
09301 uint64_t qcb_widx : 6;
09302 uint64_t qcb_ridx : 6;
09303 #else
09304 uint64_t qcb_ridx : 6;
09305 uint64_t qcb_widx : 6;
09306 uint64_t buf_ptr : 33;
09307 uint64_t buf_siz : 13;
09308 uint64_t tail : 1;
09309 uint64_t qos : 5;
09310 #endif
09311 } cn50xx;
09312 struct cvmx_pko_mem_debug7_cn50xx cn52xx;
09313 struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
09314 struct cvmx_pko_mem_debug7_cn50xx cn56xx;
09315 struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
09316 struct cvmx_pko_mem_debug7_cn50xx cn58xx;
09317 struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
09318 struct cvmx_pko_mem_debug7_cn50xx cn61xx;
09319 struct cvmx_pko_mem_debug7_cn50xx cn63xx;
09320 struct cvmx_pko_mem_debug7_cn50xx cn63xxp1;
09321 struct cvmx_pko_mem_debug7_cn50xx cn66xx;
09322 struct cvmx_pko_mem_debug7_cn68xx {
09323 #ifdef __BIG_ENDIAN_BITFIELD
09324 uint64_t buf_siz : 11;
09325 uint64_t buf_ptr : 37;
09326 uint64_t qcb_widx : 8;
09327 uint64_t qcb_ridx : 8;
09328 #else
09329 uint64_t qcb_ridx : 8;
09330 uint64_t qcb_widx : 8;
09331 uint64_t buf_ptr : 37;
09332 uint64_t buf_siz : 11;
09333 #endif
09334 } cn68xx;
09335 struct cvmx_pko_mem_debug7_cn68xx cn68xxp1;
09336 struct cvmx_pko_mem_debug7_cn50xx cn70xx;
09337 struct cvmx_pko_mem_debug7_cn50xx cn70xxp1;
09338 struct cvmx_pko_mem_debug7_cn50xx cnf71xx;
09339 };
09340 typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t;
09341
09342
09343
09344
09345
09346
09347
09348
09349
09350 union cvmx_pko_mem_debug8 {
09351 uint64_t u64;
09352 struct cvmx_pko_mem_debug8_s {
09353 #ifdef __BIG_ENDIAN_BITFIELD
09354 uint64_t reserved_59_63 : 5;
09355 uint64_t tail : 1;
09356 uint64_t reserved_0_57 : 58;
09357 #else
09358 uint64_t reserved_0_57 : 58;
09359 uint64_t tail : 1;
09360 uint64_t reserved_59_63 : 5;
09361 #endif
09362 } s;
09363 struct cvmx_pko_mem_debug8_cn30xx {
09364 #ifdef __BIG_ENDIAN_BITFIELD
09365 uint64_t qos : 5;
09366 uint64_t tail : 1;
09367 uint64_t buf_siz : 13;
09368 uint64_t buf_ptr : 33;
09369 uint64_t qcb_widx : 6;
09370 uint64_t qcb_ridx : 6;
09371 #else
09372 uint64_t qcb_ridx : 6;
09373 uint64_t qcb_widx : 6;
09374 uint64_t buf_ptr : 33;
09375 uint64_t buf_siz : 13;
09376 uint64_t tail : 1;
09377 uint64_t qos : 5;
09378 #endif
09379 } cn30xx;
09380 struct cvmx_pko_mem_debug8_cn30xx cn31xx;
09381 struct cvmx_pko_mem_debug8_cn30xx cn38xx;
09382 struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
09383 struct cvmx_pko_mem_debug8_cn50xx {
09384 #ifdef __BIG_ENDIAN_BITFIELD
09385 uint64_t reserved_28_63 : 36;
09386 uint64_t doorbell : 20;
09387 uint64_t reserved_6_7 : 2;
09388 uint64_t static_p : 1;
09389 uint64_t s_tail : 1;
09390 uint64_t static_q : 1;
09391 uint64_t qos : 3;
09392 #else
09393 uint64_t qos : 3;
09394 uint64_t static_q : 1;
09395 uint64_t s_tail : 1;
09396 uint64_t static_p : 1;
09397 uint64_t reserved_6_7 : 2;
09398 uint64_t doorbell : 20;
09399 uint64_t reserved_28_63 : 36;
09400 #endif
09401 } cn50xx;
09402 struct cvmx_pko_mem_debug8_cn52xx {
09403 #ifdef __BIG_ENDIAN_BITFIELD
09404 uint64_t reserved_29_63 : 35;
09405 uint64_t preempter : 1;
09406 uint64_t doorbell : 20;
09407 uint64_t reserved_7_7 : 1;
09408 uint64_t preemptee : 1;
09409 uint64_t static_p : 1;
09410 uint64_t s_tail : 1;
09411 uint64_t static_q : 1;
09412 uint64_t qos : 3;
09413 #else
09414 uint64_t qos : 3;
09415 uint64_t static_q : 1;
09416 uint64_t s_tail : 1;
09417 uint64_t static_p : 1;
09418 uint64_t preemptee : 1;
09419 uint64_t reserved_7_7 : 1;
09420 uint64_t doorbell : 20;
09421 uint64_t preempter : 1;
09422 uint64_t reserved_29_63 : 35;
09423 #endif
09424 } cn52xx;
09425 struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
09426 struct cvmx_pko_mem_debug8_cn52xx cn56xx;
09427 struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
09428 struct cvmx_pko_mem_debug8_cn50xx cn58xx;
09429 struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
09430 struct cvmx_pko_mem_debug8_cn61xx {
09431 #ifdef __BIG_ENDIAN_BITFIELD
09432 uint64_t reserved_42_63 : 22;
09433 uint64_t qid_qqos : 8;
09434 uint64_t reserved_33_33 : 1;
09435 uint64_t qid_idx : 4;
09436 uint64_t preempter : 1;
09437 uint64_t doorbell : 20;
09438 uint64_t reserved_7_7 : 1;
09439 uint64_t preemptee : 1;
09440 uint64_t static_p : 1;
09441 uint64_t s_tail : 1;
09442 uint64_t static_q : 1;
09443 uint64_t qos : 3;
09444 #else
09445 uint64_t qos : 3;
09446 uint64_t static_q : 1;
09447 uint64_t s_tail : 1;
09448 uint64_t static_p : 1;
09449 uint64_t preemptee : 1;
09450 uint64_t reserved_7_7 : 1;
09451 uint64_t doorbell : 20;
09452 uint64_t preempter : 1;
09453 uint64_t qid_idx : 4;
09454 uint64_t reserved_33_33 : 1;
09455 uint64_t qid_qqos : 8;
09456 uint64_t reserved_42_63 : 22;
09457 #endif
09458 } cn61xx;
09459 struct cvmx_pko_mem_debug8_cn52xx cn63xx;
09460 struct cvmx_pko_mem_debug8_cn52xx cn63xxp1;
09461 struct cvmx_pko_mem_debug8_cn61xx cn66xx;
09462 struct cvmx_pko_mem_debug8_cn68xx {
09463 #ifdef __BIG_ENDIAN_BITFIELD
09464 uint64_t reserved_50_63 : 14;
09465 uint64_t qid_qqos : 8;
09466 uint64_t qid_idx : 5;
09467 uint64_t preempter : 1;
09468 uint64_t doorbell : 20;
09469 uint64_t reserved_9_15 : 7;
09470 uint64_t qid_qos : 6;
09471 uint64_t qid_tail : 1;
09472 uint64_t buf_siz : 2;
09473 #else
09474 uint64_t buf_siz : 2;
09475 uint64_t qid_tail : 1;
09476 uint64_t qid_qos : 6;
09477 uint64_t reserved_9_15 : 7;
09478 uint64_t doorbell : 20;
09479 uint64_t preempter : 1;
09480 uint64_t qid_idx : 5;
09481 uint64_t qid_qqos : 8;
09482 uint64_t reserved_50_63 : 14;
09483 #endif
09484 } cn68xx;
09485 struct cvmx_pko_mem_debug8_cn68xx cn68xxp1;
09486 struct cvmx_pko_mem_debug8_cn61xx cn70xx;
09487 struct cvmx_pko_mem_debug8_cn61xx cn70xxp1;
09488 struct cvmx_pko_mem_debug8_cn61xx cnf71xx;
09489 };
09490 typedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t;
09491
09492
09493
09494
09495
09496
09497
09498
09499
09500 union cvmx_pko_mem_debug9 {
09501 uint64_t u64;
09502 struct cvmx_pko_mem_debug9_s {
09503 #ifdef __BIG_ENDIAN_BITFIELD
09504 uint64_t reserved_49_63 : 15;
09505 uint64_t ptrs0 : 17;
09506 uint64_t reserved_0_31 : 32;
09507 #else
09508 uint64_t reserved_0_31 : 32;
09509 uint64_t ptrs0 : 17;
09510 uint64_t reserved_49_63 : 15;
09511 #endif
09512 } s;
09513 struct cvmx_pko_mem_debug9_cn30xx {
09514 #ifdef __BIG_ENDIAN_BITFIELD
09515 uint64_t reserved_28_63 : 36;
09516 uint64_t doorbell : 20;
09517 uint64_t reserved_5_7 : 3;
09518 uint64_t s_tail : 1;
09519 uint64_t static_q : 1;
09520 uint64_t qos : 3;
09521 #else
09522 uint64_t qos : 3;
09523 uint64_t static_q : 1;
09524 uint64_t s_tail : 1;
09525 uint64_t reserved_5_7 : 3;
09526 uint64_t doorbell : 20;
09527 uint64_t reserved_28_63 : 36;
09528 #endif
09529 } cn30xx;
09530 struct cvmx_pko_mem_debug9_cn30xx cn31xx;
09531 struct cvmx_pko_mem_debug9_cn38xx {
09532 #ifdef __BIG_ENDIAN_BITFIELD
09533 uint64_t reserved_28_63 : 36;
09534 uint64_t doorbell : 20;
09535 uint64_t reserved_6_7 : 2;
09536 uint64_t static_p : 1;
09537 uint64_t s_tail : 1;
09538 uint64_t static_q : 1;
09539 uint64_t qos : 3;
09540 #else
09541 uint64_t qos : 3;
09542 uint64_t static_q : 1;
09543 uint64_t s_tail : 1;
09544 uint64_t static_p : 1;
09545 uint64_t reserved_6_7 : 2;
09546 uint64_t doorbell : 20;
09547 uint64_t reserved_28_63 : 36;
09548 #endif
09549 } cn38xx;
09550 struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
09551 struct cvmx_pko_mem_debug9_cn50xx {
09552 #ifdef __BIG_ENDIAN_BITFIELD
09553 uint64_t reserved_49_63 : 15;
09554 uint64_t ptrs0 : 17;
09555 uint64_t reserved_17_31 : 15;
09556 uint64_t ptrs3 : 17;
09557 #else
09558 uint64_t ptrs3 : 17;
09559 uint64_t reserved_17_31 : 15;
09560 uint64_t ptrs0 : 17;
09561 uint64_t reserved_49_63 : 15;
09562 #endif
09563 } cn50xx;
09564 struct cvmx_pko_mem_debug9_cn50xx cn52xx;
09565 struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
09566 struct cvmx_pko_mem_debug9_cn50xx cn56xx;
09567 struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
09568 struct cvmx_pko_mem_debug9_cn50xx cn58xx;
09569 struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
09570 struct cvmx_pko_mem_debug9_cn50xx cn61xx;
09571 struct cvmx_pko_mem_debug9_cn50xx cn63xx;
09572 struct cvmx_pko_mem_debug9_cn50xx cn63xxp1;
09573 struct cvmx_pko_mem_debug9_cn50xx cn66xx;
09574 struct cvmx_pko_mem_debug9_cn50xx cn68xx;
09575 struct cvmx_pko_mem_debug9_cn50xx cn68xxp1;
09576 struct cvmx_pko_mem_debug9_cn50xx cn70xx;
09577 struct cvmx_pko_mem_debug9_cn50xx cn70xxp1;
09578 struct cvmx_pko_mem_debug9_cn50xx cnf71xx;
09579 };
09580 typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;
09581
09582
09583
09584
09585
09586
09587
09588
09589
09590 union cvmx_pko_mem_iport_ptrs {
09591 uint64_t u64;
09592 struct cvmx_pko_mem_iport_ptrs_s {
09593 #ifdef __BIG_ENDIAN_BITFIELD
09594 uint64_t reserved_63_63 : 1;
09595 uint64_t crc : 1;
09596 uint64_t static_p : 1;
09597 uint64_t qos_mask : 8;
09598 uint64_t min_pkt : 3;
09599 uint64_t reserved_31_49 : 19;
09600 uint64_t pipe : 7;
09601
09602
09603
09604
09605
09606
09607
09608
09609
09610
09611 uint64_t reserved_21_23 : 3;
09612 uint64_t intr : 5;
09613
09614
09615
09616
09617
09618
09619
09620
09621
09622
09623
09624
09625
09626
09627
09628
09629
09630
09631
09632
09633
09634
09635
09636
09637
09638
09639
09640 uint64_t reserved_13_15 : 3;
09641 uint64_t eid : 5;
09642
09643
09644 uint64_t reserved_7_7 : 1;
09645 uint64_t ipid : 7;
09646 #else
09647 uint64_t ipid : 7;
09648 uint64_t reserved_7_7 : 1;
09649 uint64_t eid : 5;
09650 uint64_t reserved_13_15 : 3;
09651 uint64_t intr : 5;
09652 uint64_t reserved_21_23 : 3;
09653 uint64_t pipe : 7;
09654 uint64_t reserved_31_49 : 19;
09655 uint64_t min_pkt : 3;
09656 uint64_t qos_mask : 8;
09657 uint64_t static_p : 1;
09658 uint64_t crc : 1;
09659 uint64_t reserved_63_63 : 1;
09660 #endif
09661 } s;
09662 struct cvmx_pko_mem_iport_ptrs_s cn68xx;
09663 struct cvmx_pko_mem_iport_ptrs_s cn68xxp1;
09664 };
09665 typedef union cvmx_pko_mem_iport_ptrs cvmx_pko_mem_iport_ptrs_t;
09666
09667
09668
09669
09670
09671
09672
09673
09674
09675
09676
09677
09678
09679
09680 union cvmx_pko_mem_iport_qos {
09681 uint64_t u64;
09682 struct cvmx_pko_mem_iport_qos_s {
09683 #ifdef __BIG_ENDIAN_BITFIELD
09684 uint64_t reserved_61_63 : 3;
09685 uint64_t qos_mask : 8;
09686 uint64_t reserved_13_52 : 40;
09687 uint64_t eid : 5;
09688 uint64_t reserved_7_7 : 1;
09689 uint64_t ipid : 7;
09690 #else
09691 uint64_t ipid : 7;
09692 uint64_t reserved_7_7 : 1;
09693 uint64_t eid : 5;
09694 uint64_t reserved_13_52 : 40;
09695 uint64_t qos_mask : 8;
09696 uint64_t reserved_61_63 : 3;
09697 #endif
09698 } s;
09699 struct cvmx_pko_mem_iport_qos_s cn68xx;
09700 struct cvmx_pko_mem_iport_qos_s cn68xxp1;
09701 };
09702 typedef union cvmx_pko_mem_iport_qos cvmx_pko_mem_iport_qos_t;
09703
09704
09705
09706
09707
09708
09709
09710
09711
09712
09713
09714
09715
09716
09717
09718
09719
09720
09721
09722 union cvmx_pko_mem_iqueue_ptrs {
09723 uint64_t u64;
09724 struct cvmx_pko_mem_iqueue_ptrs_s {
09725 #ifdef __BIG_ENDIAN_BITFIELD
09726 uint64_t s_tail : 1;
09727 uint64_t static_p : 1;
09728 uint64_t static_q : 1;
09729 uint64_t qos_mask : 8;
09730 uint64_t buf_ptr : 31;
09731 uint64_t tail : 1;
09732 uint64_t index : 5;
09733 uint64_t reserved_15_15 : 1;
09734 uint64_t ipid : 7;
09735 uint64_t qid : 8;
09736 #else
09737 uint64_t qid : 8;
09738 uint64_t ipid : 7;
09739 uint64_t reserved_15_15 : 1;
09740 uint64_t index : 5;
09741 uint64_t tail : 1;
09742 uint64_t buf_ptr : 31;
09743 uint64_t qos_mask : 8;
09744 uint64_t static_q : 1;
09745 uint64_t static_p : 1;
09746 uint64_t s_tail : 1;
09747 #endif
09748 } s;
09749 struct cvmx_pko_mem_iqueue_ptrs_s cn68xx;
09750 struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1;
09751 };
09752 typedef union cvmx_pko_mem_iqueue_ptrs cvmx_pko_mem_iqueue_ptrs_t;
09753
09754
09755
09756
09757
09758
09759
09760
09761
09762
09763
09764
09765
09766
09767 union cvmx_pko_mem_iqueue_qos {
09768 uint64_t u64;
09769 struct cvmx_pko_mem_iqueue_qos_s {
09770 #ifdef __BIG_ENDIAN_BITFIELD
09771 uint64_t reserved_61_63 : 3;
09772 uint64_t qos_mask : 8;
09773 uint64_t reserved_15_52 : 38;
09774 uint64_t ipid : 7;
09775 uint64_t qid : 8;
09776 #else
09777 uint64_t qid : 8;
09778 uint64_t ipid : 7;
09779 uint64_t reserved_15_52 : 38;
09780 uint64_t qos_mask : 8;
09781 uint64_t reserved_61_63 : 3;
09782 #endif
09783 } s;
09784 struct cvmx_pko_mem_iqueue_qos_s cn68xx;
09785 struct cvmx_pko_mem_iqueue_qos_s cn68xxp1;
09786 };
09787 typedef union cvmx_pko_mem_iqueue_qos cvmx_pko_mem_iqueue_qos_t;
09788
09789
09790
09791
09792
09793
09794
09795
09796
09797
09798
09799
09800
09801
09802
09803
09804
09805
09806
09807
09808
09809
09810
09811
09812
09813
09814
09815
09816
09817
09818
09819
09820
09821
09822
09823
09824
09825
09826
09827
09828
09829
09830
09831
09832
09833
09834
09835
09836
09837
09838
09839
09840
09841
09842
09843
09844
09845
09846
09847
09848 union cvmx_pko_mem_port_ptrs {
09849 uint64_t u64;
09850 struct cvmx_pko_mem_port_ptrs_s {
09851 #ifdef __BIG_ENDIAN_BITFIELD
09852 uint64_t reserved_62_63 : 2;
09853 uint64_t static_p : 1;
09854 uint64_t qos_mask : 8;
09855 uint64_t reserved_16_52 : 37;
09856 uint64_t bp_port : 6;
09857 uint64_t eid : 4;
09858
09859 uint64_t pid : 6;
09860 #else
09861 uint64_t pid : 6;
09862 uint64_t eid : 4;
09863 uint64_t bp_port : 6;
09864 uint64_t reserved_16_52 : 37;
09865 uint64_t qos_mask : 8;
09866 uint64_t static_p : 1;
09867 uint64_t reserved_62_63 : 2;
09868 #endif
09869 } s;
09870 struct cvmx_pko_mem_port_ptrs_s cn52xx;
09871 struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
09872 struct cvmx_pko_mem_port_ptrs_s cn56xx;
09873 struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
09874 struct cvmx_pko_mem_port_ptrs_s cn61xx;
09875 struct cvmx_pko_mem_port_ptrs_s cn63xx;
09876 struct cvmx_pko_mem_port_ptrs_s cn63xxp1;
09877 struct cvmx_pko_mem_port_ptrs_s cn66xx;
09878 struct cvmx_pko_mem_port_ptrs_s cn70xx;
09879 struct cvmx_pko_mem_port_ptrs_s cn70xxp1;
09880 struct cvmx_pko_mem_port_ptrs_s cnf71xx;
09881 };
09882 typedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t;
09883
09884
09885
09886
09887
09888
09889
09890
09891
09892
09893
09894
09895
09896
09897 union cvmx_pko_mem_port_qos {
09898 uint64_t u64;
09899 struct cvmx_pko_mem_port_qos_s {
09900 #ifdef __BIG_ENDIAN_BITFIELD
09901 uint64_t reserved_61_63 : 3;
09902 uint64_t qos_mask : 8;
09903 uint64_t reserved_10_52 : 43;
09904 uint64_t eid : 4;
09905
09906 uint64_t pid : 6;
09907 #else
09908 uint64_t pid : 6;
09909 uint64_t eid : 4;
09910 uint64_t reserved_10_52 : 43;
09911 uint64_t qos_mask : 8;
09912 uint64_t reserved_61_63 : 3;
09913 #endif
09914 } s;
09915 struct cvmx_pko_mem_port_qos_s cn52xx;
09916 struct cvmx_pko_mem_port_qos_s cn52xxp1;
09917 struct cvmx_pko_mem_port_qos_s cn56xx;
09918 struct cvmx_pko_mem_port_qos_s cn56xxp1;
09919 struct cvmx_pko_mem_port_qos_s cn61xx;
09920 struct cvmx_pko_mem_port_qos_s cn63xx;
09921 struct cvmx_pko_mem_port_qos_s cn63xxp1;
09922 struct cvmx_pko_mem_port_qos_s cn66xx;
09923 struct cvmx_pko_mem_port_qos_s cn70xx;
09924 struct cvmx_pko_mem_port_qos_s cn70xxp1;
09925 struct cvmx_pko_mem_port_qos_s cnf71xx;
09926 };
09927 typedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t;
09928
09929
09930
09931
09932
09933
09934
09935
09936
09937 union cvmx_pko_mem_port_rate0 {
09938 uint64_t u64;
09939 struct cvmx_pko_mem_port_rate0_s {
09940 #ifdef __BIG_ENDIAN_BITFIELD
09941 uint64_t reserved_51_63 : 13;
09942 uint64_t rate_word : 19;
09943 uint64_t rate_pkt : 24;
09944 uint64_t reserved_7_7 : 1;
09945 uint64_t pid : 7;
09946 #else
09947 uint64_t pid : 7;
09948 uint64_t reserved_7_7 : 1;
09949 uint64_t rate_pkt : 24;
09950 uint64_t rate_word : 19;
09951 uint64_t reserved_51_63 : 13;
09952 #endif
09953 } s;
09954 struct cvmx_pko_mem_port_rate0_cn52xx {
09955 #ifdef __BIG_ENDIAN_BITFIELD
09956 uint64_t reserved_51_63 : 13;
09957 uint64_t rate_word : 19;
09958 uint64_t rate_pkt : 24;
09959 uint64_t reserved_6_7 : 2;
09960 uint64_t pid : 6;
09961 #else
09962 uint64_t pid : 6;
09963 uint64_t reserved_6_7 : 2;
09964 uint64_t rate_pkt : 24;
09965 uint64_t rate_word : 19;
09966 uint64_t reserved_51_63 : 13;
09967 #endif
09968 } cn52xx;
09969 struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1;
09970 struct cvmx_pko_mem_port_rate0_cn52xx cn56xx;
09971 struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1;
09972 struct cvmx_pko_mem_port_rate0_cn52xx cn61xx;
09973 struct cvmx_pko_mem_port_rate0_cn52xx cn63xx;
09974 struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1;
09975 struct cvmx_pko_mem_port_rate0_cn52xx cn66xx;
09976 struct cvmx_pko_mem_port_rate0_s cn68xx;
09977 struct cvmx_pko_mem_port_rate0_s cn68xxp1;
09978 struct cvmx_pko_mem_port_rate0_cn52xx cn70xx;
09979 struct cvmx_pko_mem_port_rate0_cn52xx cn70xxp1;
09980 struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx;
09981 };
09982 typedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t;
09983
09984
09985
09986
09987
09988
09989
09990
09991
09992
09993
09994 union cvmx_pko_mem_port_rate1 {
09995 uint64_t u64;
09996 struct cvmx_pko_mem_port_rate1_s {
09997 #ifdef __BIG_ENDIAN_BITFIELD
09998 uint64_t reserved_32_63 : 32;
09999 uint64_t rate_lim : 24;
10000 uint64_t reserved_7_7 : 1;
10001 uint64_t pid : 7;
10002 #else
10003 uint64_t pid : 7;
10004 uint64_t reserved_7_7 : 1;
10005 uint64_t rate_lim : 24;
10006 uint64_t reserved_32_63 : 32;
10007 #endif
10008 } s;
10009 struct cvmx_pko_mem_port_rate1_cn52xx {
10010 #ifdef __BIG_ENDIAN_BITFIELD
10011 uint64_t reserved_32_63 : 32;
10012 uint64_t rate_lim : 24;
10013 uint64_t reserved_6_7 : 2;
10014 uint64_t pid : 6;
10015 #else
10016 uint64_t pid : 6;
10017 uint64_t reserved_6_7 : 2;
10018 uint64_t rate_lim : 24;
10019 uint64_t reserved_32_63 : 32;
10020 #endif
10021 } cn52xx;
10022 struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1;
10023 struct cvmx_pko_mem_port_rate1_cn52xx cn56xx;
10024 struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1;
10025 struct cvmx_pko_mem_port_rate1_cn52xx cn61xx;
10026 struct cvmx_pko_mem_port_rate1_cn52xx cn63xx;
10027 struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1;
10028 struct cvmx_pko_mem_port_rate1_cn52xx cn66xx;
10029 struct cvmx_pko_mem_port_rate1_s cn68xx;
10030 struct cvmx_pko_mem_port_rate1_s cn68xxp1;
10031 struct cvmx_pko_mem_port_rate1_cn52xx cn70xx;
10032 struct cvmx_pko_mem_port_rate1_cn52xx cn70xxp1;
10033 struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx;
10034 };
10035 typedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t;
10036
10037
10038
10039
10040
10041
10042
10043
10044
10045
10046
10047
10048
10049
10050
10051
10052
10053
10054
10055 union cvmx_pko_mem_queue_ptrs {
10056 uint64_t u64;
10057 struct cvmx_pko_mem_queue_ptrs_s {
10058 #ifdef __BIG_ENDIAN_BITFIELD
10059 uint64_t s_tail : 1;
10060 uint64_t static_p : 1;
10061 uint64_t static_q : 1;
10062 uint64_t qos_mask : 8;
10063 uint64_t buf_ptr : 36;
10064 uint64_t tail : 1;
10065 uint64_t index : 3;
10066 uint64_t port : 6;
10067 uint64_t queue : 7;
10068 #else
10069 uint64_t queue : 7;
10070 uint64_t port : 6;
10071 uint64_t index : 3;
10072 uint64_t tail : 1;
10073 uint64_t buf_ptr : 36;
10074 uint64_t qos_mask : 8;
10075 uint64_t static_q : 1;
10076 uint64_t static_p : 1;
10077 uint64_t s_tail : 1;
10078 #endif
10079 } s;
10080 struct cvmx_pko_mem_queue_ptrs_s cn30xx;
10081 struct cvmx_pko_mem_queue_ptrs_s cn31xx;
10082 struct cvmx_pko_mem_queue_ptrs_s cn38xx;
10083 struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
10084 struct cvmx_pko_mem_queue_ptrs_s cn50xx;
10085 struct cvmx_pko_mem_queue_ptrs_s cn52xx;
10086 struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
10087 struct cvmx_pko_mem_queue_ptrs_s cn56xx;
10088 struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
10089 struct cvmx_pko_mem_queue_ptrs_s cn58xx;
10090 struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
10091 struct cvmx_pko_mem_queue_ptrs_s cn61xx;
10092 struct cvmx_pko_mem_queue_ptrs_s cn63xx;
10093 struct cvmx_pko_mem_queue_ptrs_s cn63xxp1;
10094 struct cvmx_pko_mem_queue_ptrs_s cn66xx;
10095 struct cvmx_pko_mem_queue_ptrs_s cn70xx;
10096 struct cvmx_pko_mem_queue_ptrs_s cn70xxp1;
10097 struct cvmx_pko_mem_queue_ptrs_s cnf71xx;
10098 };
10099 typedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t;
10100
10101
10102
10103
10104
10105
10106
10107
10108
10109
10110
10111
10112
10113
10114 union cvmx_pko_mem_queue_qos {
10115 uint64_t u64;
10116 struct cvmx_pko_mem_queue_qos_s {
10117 #ifdef __BIG_ENDIAN_BITFIELD
10118 uint64_t reserved_61_63 : 3;
10119 uint64_t qos_mask : 8;
10120 uint64_t reserved_13_52 : 40;
10121 uint64_t pid : 6;
10122 uint64_t qid : 7;
10123 #else
10124 uint64_t qid : 7;
10125 uint64_t pid : 6;
10126 uint64_t reserved_13_52 : 40;
10127 uint64_t qos_mask : 8;
10128 uint64_t reserved_61_63 : 3;
10129 #endif
10130 } s;
10131 struct cvmx_pko_mem_queue_qos_s cn30xx;
10132 struct cvmx_pko_mem_queue_qos_s cn31xx;
10133 struct cvmx_pko_mem_queue_qos_s cn38xx;
10134 struct cvmx_pko_mem_queue_qos_s cn38xxp2;
10135 struct cvmx_pko_mem_queue_qos_s cn50xx;
10136 struct cvmx_pko_mem_queue_qos_s cn52xx;
10137 struct cvmx_pko_mem_queue_qos_s cn52xxp1;
10138 struct cvmx_pko_mem_queue_qos_s cn56xx;
10139 struct cvmx_pko_mem_queue_qos_s cn56xxp1;
10140 struct cvmx_pko_mem_queue_qos_s cn58xx;
10141 struct cvmx_pko_mem_queue_qos_s cn58xxp1;
10142 struct cvmx_pko_mem_queue_qos_s cn61xx;
10143 struct cvmx_pko_mem_queue_qos_s cn63xx;
10144 struct cvmx_pko_mem_queue_qos_s cn63xxp1;
10145 struct cvmx_pko_mem_queue_qos_s cn66xx;
10146 struct cvmx_pko_mem_queue_qos_s cn70xx;
10147 struct cvmx_pko_mem_queue_qos_s cn70xxp1;
10148 struct cvmx_pko_mem_queue_qos_s cnf71xx;
10149 };
10150 typedef union cvmx_pko_mem_queue_qos cvmx_pko_mem_queue_qos_t;
10151
10152
10153
10154
10155
10156
10157
10158
10159
10160
10161
10162
10163
10164
10165
10166
10167
10168
10169
10170
10171
10172
10173
10174 union cvmx_pko_mem_throttle_int {
10175 uint64_t u64;
10176 struct cvmx_pko_mem_throttle_int_s {
10177 #ifdef __BIG_ENDIAN_BITFIELD
10178 uint64_t reserved_47_63 : 17;
10179 uint64_t word : 15;
10180
10181
10182
10183 uint64_t reserved_14_31 : 18;
10184 uint64_t packet : 6;
10185
10186
10187
10188 uint64_t reserved_5_7 : 3;
10189 uint64_t intr : 5;
10190
10191 #else
10192 uint64_t intr : 5;
10193 uint64_t reserved_5_7 : 3;
10194 uint64_t packet : 6;
10195 uint64_t reserved_14_31 : 18;
10196 uint64_t word : 15;
10197 uint64_t reserved_47_63 : 17;
10198 #endif
10199 } s;
10200 struct cvmx_pko_mem_throttle_int_s cn68xx;
10201 struct cvmx_pko_mem_throttle_int_s cn68xxp1;
10202 };
10203 typedef union cvmx_pko_mem_throttle_int cvmx_pko_mem_throttle_int_t;
10204
10205
10206
10207
10208
10209
10210
10211
10212
10213
10214
10215
10216
10217
10218
10219
10220
10221
10222
10223
10224
10225
10226
10227 union cvmx_pko_mem_throttle_pipe {
10228 uint64_t u64;
10229 struct cvmx_pko_mem_throttle_pipe_s {
10230 #ifdef __BIG_ENDIAN_BITFIELD
10231 uint64_t reserved_47_63 : 17;
10232 uint64_t word : 15;
10233
10234
10235
10236 uint64_t reserved_14_31 : 18;
10237 uint64_t packet : 6;
10238
10239
10240
10241 uint64_t reserved_7_7 : 1;
10242 uint64_t pipe : 7;
10243 #else
10244 uint64_t pipe : 7;
10245 uint64_t reserved_7_7 : 1;
10246 uint64_t packet : 6;
10247 uint64_t reserved_14_31 : 18;
10248 uint64_t word : 15;
10249 uint64_t reserved_47_63 : 17;
10250 #endif
10251 } s;
10252 struct cvmx_pko_mem_throttle_pipe_s cn68xx;
10253 struct cvmx_pko_mem_throttle_pipe_s cn68xxp1;
10254 };
10255 typedef union cvmx_pko_mem_throttle_pipe cvmx_pko_mem_throttle_pipe_t;
10256
10257
10258
10259
10260
10261
10262
10263 union cvmx_pko_ncb_bist_status {
10264 uint64_t u64;
10265 struct cvmx_pko_ncb_bist_status_s {
10266 #ifdef __BIG_ENDIAN_BITFIELD
10267 uint64_t ncbi_l2_out_ram_bist_status : 1;
10268 uint64_t ncbi_pp_out_ram_bist_status : 1;
10269 uint64_t ncbo_pdm_cmd_dat_ram_bist_status : 1;
10270 uint64_t ncbi_l2_pdm_pref_ram_bist_status : 1;
10271 uint64_t ncbo_pp_fif_ram_bist_status : 1;
10272 uint64_t ncbo_skid_fif_ram_bist_status : 1;
10273 uint64_t reserved_0_57 : 58;
10274 #else
10275 uint64_t reserved_0_57 : 58;
10276 uint64_t ncbo_skid_fif_ram_bist_status : 1;
10277 uint64_t ncbo_pp_fif_ram_bist_status : 1;
10278 uint64_t ncbi_l2_pdm_pref_ram_bist_status : 1;
10279 uint64_t ncbo_pdm_cmd_dat_ram_bist_status : 1;
10280 uint64_t ncbi_pp_out_ram_bist_status : 1;
10281 uint64_t ncbi_l2_out_ram_bist_status : 1;
10282 #endif
10283 } s;
10284 struct cvmx_pko_ncb_bist_status_s cn73xx;
10285 struct cvmx_pko_ncb_bist_status_s cn78xx;
10286 struct cvmx_pko_ncb_bist_status_s cn78xxp1;
10287 struct cvmx_pko_ncb_bist_status_s cnf75xx;
10288 };
10289 typedef union cvmx_pko_ncb_bist_status cvmx_pko_ncb_bist_status_t;
10290
10291
10292
10293
10294 union cvmx_pko_ncb_ecc_ctl0 {
10295 uint64_t u64;
10296 struct cvmx_pko_ncb_ecc_ctl0_s {
10297 #ifdef __BIG_ENDIAN_BITFIELD
10298 uint64_t ncbi_l2_out_ram_flip : 2;
10299 uint64_t ncbi_l2_out_ram_cdis : 1;
10300 uint64_t ncbi_pp_out_ram_flip : 2;
10301 uint64_t ncbi_pp_out_ram_cdis : 1;
10302 uint64_t ncbo_pdm_cmd_dat_ram_flip : 2;
10303 uint64_t ncbo_pdm_cmd_dat_ram_cdis : 1;
10304 uint64_t ncbi_l2_pdm_pref_ram_flip : 2;
10305 uint64_t ncbi_l2_pdm_pref_ram_cdis : 1;
10306 uint64_t ncbo_pp_fif_ram_flip : 2;
10307 uint64_t ncbo_pp_fif_ram_cdis : 1;
10308 uint64_t ncbo_skid_fif_ram_flip : 2;
10309 uint64_t ncbo_skid_fif_ram_cdis : 1;
10310 uint64_t reserved_0_45 : 46;
10311 #else
10312 uint64_t reserved_0_45 : 46;
10313 uint64_t ncbo_skid_fif_ram_cdis : 1;
10314 uint64_t ncbo_skid_fif_ram_flip : 2;
10315 uint64_t ncbo_pp_fif_ram_cdis : 1;
10316 uint64_t ncbo_pp_fif_ram_flip : 2;
10317 uint64_t ncbi_l2_pdm_pref_ram_cdis : 1;
10318 uint64_t ncbi_l2_pdm_pref_ram_flip : 2;
10319 uint64_t ncbo_pdm_cmd_dat_ram_cdis : 1;
10320 uint64_t ncbo_pdm_cmd_dat_ram_flip : 2;
10321 uint64_t ncbi_pp_out_ram_cdis : 1;
10322 uint64_t ncbi_pp_out_ram_flip : 2;
10323 uint64_t ncbi_l2_out_ram_cdis : 1;
10324 uint64_t ncbi_l2_out_ram_flip : 2;
10325 #endif
10326 } s;
10327 struct cvmx_pko_ncb_ecc_ctl0_s cn73xx;
10328 struct cvmx_pko_ncb_ecc_ctl0_s cn78xx;
10329 struct cvmx_pko_ncb_ecc_ctl0_s cn78xxp1;
10330 struct cvmx_pko_ncb_ecc_ctl0_s cnf75xx;
10331 };
10332 typedef union cvmx_pko_ncb_ecc_ctl0 cvmx_pko_ncb_ecc_ctl0_t;
10333
10334
10335
10336
10337 union cvmx_pko_ncb_ecc_dbe_sts0 {
10338 uint64_t u64;
10339 struct cvmx_pko_ncb_ecc_dbe_sts0_s {
10340 #ifdef __BIG_ENDIAN_BITFIELD
10341 uint64_t ncbi_l2_out_ram_dbe : 1;
10342 uint64_t ncbi_pp_out_ram_dbe : 1;
10343 uint64_t ncbo_pdm_cmd_dat_ram_dbe : 1;
10344 uint64_t ncbi_l2_pdm_pref_ram_dbe : 1;
10345 uint64_t ncbo_pp_fif_ram_dbe : 1;
10346 uint64_t ncbo_skid_fif_ram_dbe : 1;
10347 uint64_t reserved_0_57 : 58;
10348 #else
10349 uint64_t reserved_0_57 : 58;
10350 uint64_t ncbo_skid_fif_ram_dbe : 1;
10351 uint64_t ncbo_pp_fif_ram_dbe : 1;
10352 uint64_t ncbi_l2_pdm_pref_ram_dbe : 1;
10353 uint64_t ncbo_pdm_cmd_dat_ram_dbe : 1;
10354 uint64_t ncbi_pp_out_ram_dbe : 1;
10355 uint64_t ncbi_l2_out_ram_dbe : 1;
10356 #endif
10357 } s;
10358 struct cvmx_pko_ncb_ecc_dbe_sts0_s cn73xx;
10359 struct cvmx_pko_ncb_ecc_dbe_sts0_s cn78xx;
10360 struct cvmx_pko_ncb_ecc_dbe_sts0_s cn78xxp1;
10361 struct cvmx_pko_ncb_ecc_dbe_sts0_s cnf75xx;
10362 };
10363 typedef union cvmx_pko_ncb_ecc_dbe_sts0 cvmx_pko_ncb_ecc_dbe_sts0_t;
10364
10365
10366
10367
10368 union cvmx_pko_ncb_ecc_dbe_sts_cmb0 {
10369 uint64_t u64;
10370 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s {
10371 #ifdef __BIG_ENDIAN_BITFIELD
10372 uint64_t ncb_dbe_cmb0 : 1;
10373
10374
10375
10376 uint64_t reserved_0_62 : 63;
10377 #else
10378 uint64_t reserved_0_62 : 63;
10379 uint64_t ncb_dbe_cmb0 : 1;
10380 #endif
10381 } s;
10382 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s cn73xx;
10383 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s cn78xx;
10384 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s cn78xxp1;
10385 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s cnf75xx;
10386 };
10387 typedef union cvmx_pko_ncb_ecc_dbe_sts_cmb0 cvmx_pko_ncb_ecc_dbe_sts_cmb0_t;
10388
10389
10390
10391
10392 union cvmx_pko_ncb_ecc_sbe_sts0 {
10393 uint64_t u64;
10394 struct cvmx_pko_ncb_ecc_sbe_sts0_s {
10395 #ifdef __BIG_ENDIAN_BITFIELD
10396 uint64_t ncbi_l2_out_ram_sbe : 1;
10397 uint64_t ncbi_pp_out_ram_sbe : 1;
10398 uint64_t ncbo_pdm_cmd_dat_ram_sbe : 1;
10399 uint64_t ncbi_l2_pdm_pref_ram_sbe : 1;
10400 uint64_t ncbo_pp_fif_ram_sbe : 1;
10401 uint64_t ncbo_skid_fif_ram_sbe : 1;
10402 uint64_t reserved_0_57 : 58;
10403 #else
10404 uint64_t reserved_0_57 : 58;
10405 uint64_t ncbo_skid_fif_ram_sbe : 1;
10406 uint64_t ncbo_pp_fif_ram_sbe : 1;
10407 uint64_t ncbi_l2_pdm_pref_ram_sbe : 1;
10408 uint64_t ncbo_pdm_cmd_dat_ram_sbe : 1;
10409 uint64_t ncbi_pp_out_ram_sbe : 1;
10410 uint64_t ncbi_l2_out_ram_sbe : 1;
10411 #endif
10412 } s;
10413 struct cvmx_pko_ncb_ecc_sbe_sts0_s cn73xx;
10414 struct cvmx_pko_ncb_ecc_sbe_sts0_s cn78xx;
10415 struct cvmx_pko_ncb_ecc_sbe_sts0_s cn78xxp1;
10416 struct cvmx_pko_ncb_ecc_sbe_sts0_s cnf75xx;
10417 };
10418 typedef union cvmx_pko_ncb_ecc_sbe_sts0 cvmx_pko_ncb_ecc_sbe_sts0_t;
10419
10420
10421
10422
10423 union cvmx_pko_ncb_ecc_sbe_sts_cmb0 {
10424 uint64_t u64;
10425 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s {
10426 #ifdef __BIG_ENDIAN_BITFIELD
10427 uint64_t ncb_sbe_cmb0 : 1;
10428
10429
10430
10431 uint64_t reserved_0_62 : 63;
10432 #else
10433 uint64_t reserved_0_62 : 63;
10434 uint64_t ncb_sbe_cmb0 : 1;
10435 #endif
10436 } s;
10437 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s cn73xx;
10438 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s cn78xx;
10439 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s cn78xxp1;
10440 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s cnf75xx;
10441 };
10442 typedef union cvmx_pko_ncb_ecc_sbe_sts_cmb0 cvmx_pko_ncb_ecc_sbe_sts_cmb0_t;
10443
10444
10445
10446
10447 union cvmx_pko_ncb_int {
10448 uint64_t u64;
10449 struct cvmx_pko_ncb_int_s {
10450 #ifdef __BIG_ENDIAN_BITFIELD
10451 uint64_t reserved_2_63 : 62;
10452 uint64_t tso_segment_cnt : 1;
10453
10454
10455
10456
10457
10458
10459
10460
10461
10462
10463
10464
10465 uint64_t ncb_tx_error : 1;
10466
10467 #else
10468 uint64_t ncb_tx_error : 1;
10469 uint64_t tso_segment_cnt : 1;
10470 uint64_t reserved_2_63 : 62;
10471 #endif
10472 } s;
10473 struct cvmx_pko_ncb_int_s cn73xx;
10474 struct cvmx_pko_ncb_int_s cn78xx;
10475 struct cvmx_pko_ncb_int_s cn78xxp1;
10476 struct cvmx_pko_ncb_int_s cnf75xx;
10477 };
10478 typedef union cvmx_pko_ncb_int cvmx_pko_ncb_int_t;
10479
10480
10481
10482
10483 union cvmx_pko_ncb_tx_err_info {
10484 uint64_t u64;
10485 struct cvmx_pko_ncb_tx_err_info_s {
10486 #ifdef __BIG_ENDIAN_BITFIELD
10487 uint64_t reserved_32_63 : 32;
10488 uint64_t wcnt : 5;
10489 uint64_t src : 12;
10490 uint64_t dst : 8;
10491 uint64_t tag : 4;
10492 uint64_t eot : 1;
10493 uint64_t sot : 1;
10494 uint64_t valid : 1;
10495 #else
10496 uint64_t valid : 1;
10497 uint64_t sot : 1;
10498 uint64_t eot : 1;
10499 uint64_t tag : 4;
10500 uint64_t dst : 8;
10501 uint64_t src : 12;
10502 uint64_t wcnt : 5;
10503 uint64_t reserved_32_63 : 32;
10504 #endif
10505 } s;
10506 struct cvmx_pko_ncb_tx_err_info_s cn73xx;
10507 struct cvmx_pko_ncb_tx_err_info_s cn78xx;
10508 struct cvmx_pko_ncb_tx_err_info_s cn78xxp1;
10509 struct cvmx_pko_ncb_tx_err_info_s cnf75xx;
10510 };
10511 typedef union cvmx_pko_ncb_tx_err_info cvmx_pko_ncb_tx_err_info_t;
10512
10513
10514
10515
10516 union cvmx_pko_ncb_tx_err_word {
10517 uint64_t u64;
10518 struct cvmx_pko_ncb_tx_err_word_s {
10519 #ifdef __BIG_ENDIAN_BITFIELD
10520 uint64_t err_word : 64;
10521
10522
10523 #else
10524 uint64_t err_word : 64;
10525 #endif
10526 } s;
10527 struct cvmx_pko_ncb_tx_err_word_s cn73xx;
10528 struct cvmx_pko_ncb_tx_err_word_s cn78xx;
10529 struct cvmx_pko_ncb_tx_err_word_s cn78xxp1;
10530 struct cvmx_pko_ncb_tx_err_word_s cnf75xx;
10531 };
10532 typedef union cvmx_pko_ncb_tx_err_word cvmx_pko_ncb_tx_err_word_t;
10533
10534
10535
10536
10537
10538
10539
10540 union cvmx_pko_pdm_bist_status {
10541 uint64_t u64;
10542 struct cvmx_pko_pdm_bist_status_s {
10543 #ifdef __BIG_ENDIAN_BITFIELD
10544 uint64_t flshb_cache_lo_ram_bist_status : 1;
10545 uint64_t flshb_cache_hi_ram_bist_status : 1;
10546 uint64_t isrm_ca_iinst_ram_bist_status : 1;
10547 uint64_t isrm_ca_cm_ram_bist_status : 1;
10548 uint64_t isrm_st_ram2_bist_status : 1;
10549 uint64_t isrm_st_ram1_bist_status : 1;
10550 uint64_t isrm_st_ram0_bist_status : 1;
10551 uint64_t isrd_st_ram3_bist_status : 1;
10552 uint64_t isrd_st_ram2_bist_status : 1;
10553 uint64_t isrd_st_ram1_bist_status : 1;
10554 uint64_t isrd_st_ram0_bist_status : 1;
10555 uint64_t drp_hi_ram_bist_status : 1;
10556 uint64_t drp_lo_ram_bist_status : 1;
10557 uint64_t dwp_hi_ram_bist_status : 1;
10558 uint64_t dwp_lo_ram_bist_status : 1;
10559 uint64_t mwp_hi_ram_bist_status : 1;
10560 uint64_t mwp_lo_ram_bist_status : 1;
10561 uint64_t fillb_m_rsp_ram_hi_bist_status : 1;
10562 uint64_t fillb_m_rsp_ram_lo_bist_status : 1;
10563 uint64_t fillb_d_rsp_ram_hi_bist_status : 1;
10564 uint64_t fillb_d_rsp_ram_lo_bist_status : 1;
10565 uint64_t fillb_d_rsp_dat_fifo_bist_status : 1;
10566 uint64_t fillb_m_rsp_dat_fifo_bist_status : 1;
10567 uint64_t flshb_m_dat_ram_bist_status : 1;
10568 uint64_t flshb_d_dat_ram_bist_status : 1;
10569 uint64_t minpad_ram_bist_status : 1;
10570 uint64_t mwp_hi_spt_ram_bist_status : 1;
10571 uint64_t mwp_lo_spt_ram_bist_status : 1;
10572 uint64_t buf_wm_ram_bist_status : 1;
10573 uint64_t reserved_0_34 : 35;
10574 #else
10575 uint64_t reserved_0_34 : 35;
10576 uint64_t buf_wm_ram_bist_status : 1;
10577 uint64_t mwp_lo_spt_ram_bist_status : 1;
10578 uint64_t mwp_hi_spt_ram_bist_status : 1;
10579 uint64_t minpad_ram_bist_status : 1;
10580 uint64_t flshb_d_dat_ram_bist_status : 1;
10581 uint64_t flshb_m_dat_ram_bist_status : 1;
10582 uint64_t fillb_m_rsp_dat_fifo_bist_status : 1;
10583 uint64_t fillb_d_rsp_dat_fifo_bist_status : 1;
10584 uint64_t fillb_d_rsp_ram_lo_bist_status : 1;
10585 uint64_t fillb_d_rsp_ram_hi_bist_status : 1;
10586 uint64_t fillb_m_rsp_ram_lo_bist_status : 1;
10587 uint64_t fillb_m_rsp_ram_hi_bist_status : 1;
10588 uint64_t mwp_lo_ram_bist_status : 1;
10589 uint64_t mwp_hi_ram_bist_status : 1;
10590 uint64_t dwp_lo_ram_bist_status : 1;
10591 uint64_t dwp_hi_ram_bist_status : 1;
10592 uint64_t drp_lo_ram_bist_status : 1;
10593 uint64_t drp_hi_ram_bist_status : 1;
10594 uint64_t isrd_st_ram0_bist_status : 1;
10595 uint64_t isrd_st_ram1_bist_status : 1;
10596 uint64_t isrd_st_ram2_bist_status : 1;
10597 uint64_t isrd_st_ram3_bist_status : 1;
10598 uint64_t isrm_st_ram0_bist_status : 1;
10599 uint64_t isrm_st_ram1_bist_status : 1;
10600 uint64_t isrm_st_ram2_bist_status : 1;
10601 uint64_t isrm_ca_cm_ram_bist_status : 1;
10602 uint64_t isrm_ca_iinst_ram_bist_status : 1;
10603 uint64_t flshb_cache_hi_ram_bist_status : 1;
10604 uint64_t flshb_cache_lo_ram_bist_status : 1;
10605 #endif
10606 } s;
10607 struct cvmx_pko_pdm_bist_status_s cn73xx;
10608 struct cvmx_pko_pdm_bist_status_s cn78xx;
10609 struct cvmx_pko_pdm_bist_status_s cn78xxp1;
10610 struct cvmx_pko_pdm_bist_status_s cnf75xx;
10611 };
10612 typedef union cvmx_pko_pdm_bist_status cvmx_pko_pdm_bist_status_t;
10613
10614
10615
10616
10617 union cvmx_pko_pdm_cfg {
10618 uint64_t u64;
10619 struct cvmx_pko_pdm_cfg_s {
10620 #ifdef __BIG_ENDIAN_BITFIELD
10621 uint64_t reserved_13_63 : 51;
10622 uint64_t dis_lpd_w2r_fill : 1;
10623
10624
10625 uint64_t en_fr_w2r_ptr_swp : 1;
10626
10627 uint64_t dis_flsh_cache : 1;
10628
10629 uint64_t pko_pad_minlen : 7;
10630
10631
10632
10633
10634
10635
10636
10637 uint64_t diag_mode : 1;
10638 uint64_t alloc_lds : 1;
10639
10640
10641 uint64_t alloc_sts : 1;
10642
10643
10644 #else
10645 uint64_t alloc_sts : 1;
10646 uint64_t alloc_lds : 1;
10647 uint64_t diag_mode : 1;
10648 uint64_t pko_pad_minlen : 7;
10649 uint64_t dis_flsh_cache : 1;
10650 uint64_t en_fr_w2r_ptr_swp : 1;
10651 uint64_t dis_lpd_w2r_fill : 1;
10652 uint64_t reserved_13_63 : 51;
10653 #endif
10654 } s;
10655 struct cvmx_pko_pdm_cfg_s cn73xx;
10656 struct cvmx_pko_pdm_cfg_s cn78xx;
10657 struct cvmx_pko_pdm_cfg_s cn78xxp1;
10658 struct cvmx_pko_pdm_cfg_s cnf75xx;
10659 };
10660 typedef union cvmx_pko_pdm_cfg cvmx_pko_pdm_cfg_t;
10661
10662
10663
10664
10665 union cvmx_pko_pdm_cfg_dbg {
10666 uint64_t u64;
10667 struct cvmx_pko_pdm_cfg_dbg_s {
10668 #ifdef __BIG_ENDIAN_BITFIELD
10669 uint64_t reserved_32_63 : 32;
10670 uint64_t cp_stall_thrshld : 32;
10671
10672
10673 #else
10674 uint64_t cp_stall_thrshld : 32;
10675 uint64_t reserved_32_63 : 32;
10676 #endif
10677 } s;
10678 struct cvmx_pko_pdm_cfg_dbg_s cn73xx;
10679 struct cvmx_pko_pdm_cfg_dbg_s cn78xx;
10680 struct cvmx_pko_pdm_cfg_dbg_s cn78xxp1;
10681 struct cvmx_pko_pdm_cfg_dbg_s cnf75xx;
10682 };
10683 typedef union cvmx_pko_pdm_cfg_dbg cvmx_pko_pdm_cfg_dbg_t;
10684
10685
10686
10687
10688 union cvmx_pko_pdm_cp_dbg {
10689 uint64_t u64;
10690 struct cvmx_pko_pdm_cp_dbg_s {
10691 #ifdef __BIG_ENDIAN_BITFIELD
10692 uint64_t reserved_16_63 : 48;
10693 uint64_t stateless_fif_cnt : 6;
10694 uint64_t reserved_5_9 : 5;
10695 uint64_t op_fif_not_full : 5;
10696
10697
10698
10699
10700
10701 #else
10702 uint64_t op_fif_not_full : 5;
10703 uint64_t reserved_5_9 : 5;
10704 uint64_t stateless_fif_cnt : 6;
10705 uint64_t reserved_16_63 : 48;
10706 #endif
10707 } s;
10708 struct cvmx_pko_pdm_cp_dbg_s cn73xx;
10709 struct cvmx_pko_pdm_cp_dbg_s cn78xx;
10710 struct cvmx_pko_pdm_cp_dbg_s cn78xxp1;
10711 struct cvmx_pko_pdm_cp_dbg_s cnf75xx;
10712 };
10713 typedef union cvmx_pko_pdm_cp_dbg cvmx_pko_pdm_cp_dbg_t;
10714
10715
10716
10717
10718 union cvmx_pko_pdm_dqx_minpad {
10719 uint64_t u64;
10720 struct cvmx_pko_pdm_dqx_minpad_s {
10721 #ifdef __BIG_ENDIAN_BITFIELD
10722 uint64_t reserved_1_63 : 63;
10723 uint64_t minpad : 1;
10724
10725
10726
10727
10728
10729
10730
10731
10732
10733
10734
10735
10736
10737 #else
10738 uint64_t minpad : 1;
10739 uint64_t reserved_1_63 : 63;
10740 #endif
10741 } s;
10742 struct cvmx_pko_pdm_dqx_minpad_s cn73xx;
10743 struct cvmx_pko_pdm_dqx_minpad_s cn78xx;
10744 struct cvmx_pko_pdm_dqx_minpad_s cn78xxp1;
10745 struct cvmx_pko_pdm_dqx_minpad_s cnf75xx;
10746 };
10747 typedef union cvmx_pko_pdm_dqx_minpad cvmx_pko_pdm_dqx_minpad_t;
10748
10749
10750
10751
10752 union cvmx_pko_pdm_drpbuf_dbg {
10753 uint64_t u64;
10754 struct cvmx_pko_pdm_drpbuf_dbg_s {
10755 #ifdef __BIG_ENDIAN_BITFIELD
10756 uint64_t reserved_43_63 : 21;
10757 uint64_t sel_nxt_ptr : 1;
10758 uint64_t load_val : 1;
10759 uint64_t rdy : 1;
10760 uint64_t cur_state : 3;
10761 uint64_t reserved_33_36 : 4;
10762 uint64_t track_rd_cnt : 6;
10763 uint64_t track_wr_cnt : 6;
10764 uint64_t reserved_17_20 : 4;
10765 uint64_t mem_addr : 13;
10766 uint64_t mem_en : 4;
10767
10768
10769
10770
10771 #else
10772 uint64_t mem_en : 4;
10773 uint64_t mem_addr : 13;
10774 uint64_t reserved_17_20 : 4;
10775 uint64_t track_wr_cnt : 6;
10776 uint64_t track_rd_cnt : 6;
10777 uint64_t reserved_33_36 : 4;
10778 uint64_t cur_state : 3;
10779 uint64_t rdy : 1;
10780 uint64_t load_val : 1;
10781 uint64_t sel_nxt_ptr : 1;
10782 uint64_t reserved_43_63 : 21;
10783 #endif
10784 } s;
10785 struct cvmx_pko_pdm_drpbuf_dbg_s cn73xx;
10786 struct cvmx_pko_pdm_drpbuf_dbg_s cn78xx;
10787 struct cvmx_pko_pdm_drpbuf_dbg_s cn78xxp1;
10788 struct cvmx_pko_pdm_drpbuf_dbg_s cnf75xx;
10789 };
10790 typedef union cvmx_pko_pdm_drpbuf_dbg cvmx_pko_pdm_drpbuf_dbg_t;
10791
10792
10793
10794
10795 union cvmx_pko_pdm_dwpbuf_dbg {
10796 uint64_t u64;
10797 struct cvmx_pko_pdm_dwpbuf_dbg_s {
10798 #ifdef __BIG_ENDIAN_BITFIELD
10799 uint64_t reserved_48_63 : 16;
10800 uint64_t cmd_proc : 1;
10801 uint64_t reserved_46_46 : 1;
10802 uint64_t mem_data_val : 1;
10803 uint64_t insert_np : 1;
10804 uint64_t reserved_43_43 : 1;
10805 uint64_t sel_nxt_ptr : 1;
10806 uint64_t load_val : 1;
10807 uint64_t rdy : 1;
10808 uint64_t cur_state : 3;
10809 uint64_t mem_rdy : 1;
10810 uint64_t reserved_33_35 : 3;
10811 uint64_t track_rd_cnt : 6;
10812 uint64_t track_wr_cnt : 6;
10813 uint64_t reserved_19_20 : 2;
10814 uint64_t insert_dp : 2;
10815 uint64_t mem_addr : 13;
10816 uint64_t mem_en : 4;
10817
10818
10819
10820
10821 #else
10822 uint64_t mem_en : 4;
10823 uint64_t mem_addr : 13;
10824 uint64_t insert_dp : 2;
10825 uint64_t reserved_19_20 : 2;
10826 uint64_t track_wr_cnt : 6;
10827 uint64_t track_rd_cnt : 6;
10828 uint64_t reserved_33_35 : 3;
10829 uint64_t mem_rdy : 1;
10830 uint64_t cur_state : 3;
10831 uint64_t rdy : 1;
10832 uint64_t load_val : 1;
10833 uint64_t sel_nxt_ptr : 1;
10834 uint64_t reserved_43_43 : 1;
10835 uint64_t insert_np : 1;
10836 uint64_t mem_data_val : 1;
10837 uint64_t reserved_46_46 : 1;
10838 uint64_t cmd_proc : 1;
10839 uint64_t reserved_48_63 : 16;
10840 #endif
10841 } s;
10842 struct cvmx_pko_pdm_dwpbuf_dbg_cn73xx {
10843 #ifdef __BIG_ENDIAN_BITFIELD
10844 uint64_t reserved_48_63 : 16;
10845 uint64_t cmd_proc : 1;
10846 uint64_t reserved_46_46 : 1;
10847 uint64_t mem_data_val : 1;
10848 uint64_t insert_np : 1;
10849 uint64_t reserved_43_43 : 1;
10850 uint64_t sel_nxt_ptr : 1;
10851 uint64_t load_val : 1;
10852 uint64_t rdy : 1;
10853 uint64_t reserved_37_39 : 3;
10854 uint64_t mem_rdy : 1;
10855 uint64_t reserved_19_35 : 17;
10856 uint64_t insert_dp : 2;
10857 uint64_t reserved_15_16 : 2;
10858 uint64_t mem_addr : 11;
10859 uint64_t mem_en : 4;
10860
10861
10862
10863
10864 #else
10865 uint64_t mem_en : 4;
10866 uint64_t mem_addr : 11;
10867 uint64_t reserved_15_16 : 2;
10868 uint64_t insert_dp : 2;
10869 uint64_t reserved_19_35 : 17;
10870 uint64_t mem_rdy : 1;
10871 uint64_t reserved_37_39 : 3;
10872 uint64_t rdy : 1;
10873 uint64_t load_val : 1;
10874 uint64_t sel_nxt_ptr : 1;
10875 uint64_t reserved_43_43 : 1;
10876 uint64_t insert_np : 1;
10877 uint64_t mem_data_val : 1;
10878 uint64_t reserved_46_46 : 1;
10879 uint64_t cmd_proc : 1;
10880 uint64_t reserved_48_63 : 16;
10881 #endif
10882 } cn73xx;
10883 struct cvmx_pko_pdm_dwpbuf_dbg_s cn78xx;
10884 struct cvmx_pko_pdm_dwpbuf_dbg_s cn78xxp1;
10885 struct cvmx_pko_pdm_dwpbuf_dbg_cn73xx cnf75xx;
10886 };
10887 typedef union cvmx_pko_pdm_dwpbuf_dbg cvmx_pko_pdm_dwpbuf_dbg_t;
10888
10889
10890
10891
10892 union cvmx_pko_pdm_ecc_ctl0 {
10893 uint64_t u64;
10894 struct cvmx_pko_pdm_ecc_ctl0_s {
10895 #ifdef __BIG_ENDIAN_BITFIELD
10896 uint64_t flshb_cache_lo_ram_flip : 2;
10897 uint64_t flshb_cache_lo_ram_cdis : 1;
10898 uint64_t flshb_cache_hi_ram_flip : 2;
10899 uint64_t flshb_cache_hi_ram_cdis : 1;
10900 uint64_t isrm_ca_iinst_ram_flip : 2;
10901 uint64_t isrm_ca_iinst_ram_cdis : 1;
10902 uint64_t isrm_ca_cm_ram_flip : 2;
10903 uint64_t isrm_ca_cm_ram_cdis : 1;
10904 uint64_t isrm_st_ram2_flip : 2;
10905 uint64_t isrm_st_ram2_cdis : 1;
10906 uint64_t isrm_st_ram1_flip : 2;
10907 uint64_t isrm_st_ram1_cdis : 1;
10908 uint64_t isrm_st_ram0_flip : 2;
10909 uint64_t isrm_st_ram0_cdis : 1;
10910 uint64_t isrd_st_ram3_flip : 2;
10911 uint64_t isrd_st_ram3_cdis : 1;
10912 uint64_t isrd_st_ram2_flip : 2;
10913 uint64_t isrd_st_ram2_cdis : 1;
10914 uint64_t isrd_st_ram1_flip : 2;
10915 uint64_t isrd_st_ram1_cdis : 1;
10916 uint64_t isrd_st_ram0_flip : 2;
10917 uint64_t isrd_st_ram0_cdis : 1;
10918 uint64_t drp_hi_ram_flip : 2;
10919 uint64_t drp_hi_ram_cdis : 1;
10920 uint64_t drp_lo_ram_flip : 2;
10921 uint64_t drp_lo_ram_cdis : 1;
10922 uint64_t dwp_hi_ram_flip : 2;
10923 uint64_t dwp_hi_ram_cdis : 1;
10924 uint64_t dwp_lo_ram_flip : 2;
10925 uint64_t dwp_lo_ram_cdis : 1;
10926 uint64_t mwp_hi_ram_flip : 2;
10927 uint64_t mwp_hi_ram_cdis : 1;
10928 uint64_t mwp_lo_ram_flip : 2;
10929 uint64_t mwp_lo_ram_cdis : 1;
10930 uint64_t fillb_m_rsp_ram_hi_flip : 2;
10931 uint64_t fillb_m_rsp_ram_hi_cdis : 1;
10932 uint64_t fillb_m_rsp_ram_lo_flip : 2;
10933 uint64_t fillb_m_rsp_ram_lo_cdis : 1;
10934 uint64_t fillb_d_rsp_ram_hi_flip : 2;
10935 uint64_t fillb_d_rsp_ram_hi_cdis : 1;
10936 uint64_t fillb_d_rsp_ram_lo_flip : 2;
10937 uint64_t fillb_d_rsp_ram_lo_cdis : 1;
10938 uint64_t reserved_0_0 : 1;
10939 #else
10940 uint64_t reserved_0_0 : 1;
10941 uint64_t fillb_d_rsp_ram_lo_cdis : 1;
10942 uint64_t fillb_d_rsp_ram_lo_flip : 2;
10943 uint64_t fillb_d_rsp_ram_hi_cdis : 1;
10944 uint64_t fillb_d_rsp_ram_hi_flip : 2;
10945 uint64_t fillb_m_rsp_ram_lo_cdis : 1;
10946 uint64_t fillb_m_rsp_ram_lo_flip : 2;
10947 uint64_t fillb_m_rsp_ram_hi_cdis : 1;
10948 uint64_t fillb_m_rsp_ram_hi_flip : 2;
10949 uint64_t mwp_lo_ram_cdis : 1;
10950 uint64_t mwp_lo_ram_flip : 2;
10951 uint64_t mwp_hi_ram_cdis : 1;
10952 uint64_t mwp_hi_ram_flip : 2;
10953 uint64_t dwp_lo_ram_cdis : 1;
10954 uint64_t dwp_lo_ram_flip : 2;
10955 uint64_t dwp_hi_ram_cdis : 1;
10956 uint64_t dwp_hi_ram_flip : 2;
10957 uint64_t drp_lo_ram_cdis : 1;
10958 uint64_t drp_lo_ram_flip : 2;
10959 uint64_t drp_hi_ram_cdis : 1;
10960 uint64_t drp_hi_ram_flip : 2;
10961 uint64_t isrd_st_ram0_cdis : 1;
10962 uint64_t isrd_st_ram0_flip : 2;
10963 uint64_t isrd_st_ram1_cdis : 1;
10964 uint64_t isrd_st_ram1_flip : 2;
10965 uint64_t isrd_st_ram2_cdis : 1;
10966 uint64_t isrd_st_ram2_flip : 2;
10967 uint64_t isrd_st_ram3_cdis : 1;
10968 uint64_t isrd_st_ram3_flip : 2;
10969 uint64_t isrm_st_ram0_cdis : 1;
10970 uint64_t isrm_st_ram0_flip : 2;
10971 uint64_t isrm_st_ram1_cdis : 1;
10972 uint64_t isrm_st_ram1_flip : 2;
10973 uint64_t isrm_st_ram2_cdis : 1;
10974 uint64_t isrm_st_ram2_flip : 2;
10975 uint64_t isrm_ca_cm_ram_cdis : 1;
10976 uint64_t isrm_ca_cm_ram_flip : 2;
10977 uint64_t isrm_ca_iinst_ram_cdis : 1;
10978 uint64_t isrm_ca_iinst_ram_flip : 2;
10979 uint64_t flshb_cache_hi_ram_cdis : 1;
10980 uint64_t flshb_cache_hi_ram_flip : 2;
10981 uint64_t flshb_cache_lo_ram_cdis : 1;
10982 uint64_t flshb_cache_lo_ram_flip : 2;
10983 #endif
10984 } s;
10985 struct cvmx_pko_pdm_ecc_ctl0_cn73xx {
10986 #ifdef __BIG_ENDIAN_BITFIELD
10987 uint64_t flshb_cache_lo_ram_flip : 2;
10988 uint64_t flshb_cache_lo_ram_cdis : 1;
10989 uint64_t flshb_cache_hi_ram_flip : 2;
10990 uint64_t flshb_cache_hi_ram_cdis : 1;
10991 uint64_t isrm_ca_iinst_ram_flip : 2;
10992 uint64_t isrm_ca_iinst_ram_cdis : 1;
10993 uint64_t isrm_ca_cm_ram_flip : 2;
10994 uint64_t isrm_ca_cm_ram_cdis : 1;
10995 uint64_t isrm_st_ram2_flip : 2;
10996 uint64_t isrm_st_ram2_cdis : 1;
10997 uint64_t isrm_st_ram1_flip : 2;
10998 uint64_t isrm_st_ram1_cdis : 1;
10999 uint64_t isrm_st_ram0_flip : 2;
11000 uint64_t isrm_st_ram0_cdis : 1;
11001 uint64_t isrd_st_ram3_flip : 2;
11002 uint64_t isrd_st_ram3_cdis : 1;
11003 uint64_t isrd_st_ram2_flip : 2;
11004 uint64_t isrd_st_ram2_cdis : 1;
11005 uint64_t isrd_st_ram1_flip : 2;
11006 uint64_t isrd_st_ram1_cdis : 1;
11007 uint64_t isrd_st_ram0_flip : 2;
11008 uint64_t isrd_st_ram0_cdis : 1;
11009 uint64_t drp_hi_ram_flip : 2;
11010 uint64_t drp_hi_ram_cdis : 1;
11011 uint64_t drp_lo_ram_flip : 2;
11012 uint64_t drp_lo_ram_cdis : 1;
11013 uint64_t dwp_hi_ram_flip : 2;
11014 uint64_t dwp_hi_ram_cdis : 1;
11015 uint64_t dwp_lo_ram_flip : 2;
11016 uint64_t dwp_lo_ram_cdis : 1;
11017 uint64_t reserved_13_18 : 6;
11018 uint64_t fillb_m_rsp_ram_hi_flip : 2;
11019 uint64_t fillb_m_rsp_ram_hi_cdis : 1;
11020 uint64_t fillb_m_rsp_ram_lo_flip : 2;
11021 uint64_t fillb_m_rsp_ram_lo_cdis : 1;
11022 uint64_t fillb_d_rsp_ram_hi_flip : 2;
11023 uint64_t fillb_d_rsp_ram_hi_cdis : 1;
11024 uint64_t fillb_d_rsp_ram_lo_flip : 2;
11025 uint64_t fillb_d_rsp_ram_lo_cdis : 1;
11026 uint64_t reserved_0_0 : 1;
11027 #else
11028 uint64_t reserved_0_0 : 1;
11029 uint64_t fillb_d_rsp_ram_lo_cdis : 1;
11030 uint64_t fillb_d_rsp_ram_lo_flip : 2;
11031 uint64_t fillb_d_rsp_ram_hi_cdis : 1;
11032 uint64_t fillb_d_rsp_ram_hi_flip : 2;
11033 uint64_t fillb_m_rsp_ram_lo_cdis : 1;
11034 uint64_t fillb_m_rsp_ram_lo_flip : 2;
11035 uint64_t fillb_m_rsp_ram_hi_cdis : 1;
11036 uint64_t fillb_m_rsp_ram_hi_flip : 2;
11037 uint64_t reserved_13_18 : 6;
11038 uint64_t dwp_lo_ram_cdis : 1;
11039 uint64_t dwp_lo_ram_flip : 2;
11040 uint64_t dwp_hi_ram_cdis : 1;
11041 uint64_t dwp_hi_ram_flip : 2;
11042 uint64_t drp_lo_ram_cdis : 1;
11043 uint64_t drp_lo_ram_flip : 2;
11044 uint64_t drp_hi_ram_cdis : 1;
11045 uint64_t drp_hi_ram_flip : 2;
11046 uint64_t isrd_st_ram0_cdis : 1;
11047 uint64_t isrd_st_ram0_flip : 2;
11048 uint64_t isrd_st_ram1_cdis : 1;
11049 uint64_t isrd_st_ram1_flip : 2;
11050 uint64_t isrd_st_ram2_cdis : 1;
11051 uint64_t isrd_st_ram2_flip : 2;
11052 uint64_t isrd_st_ram3_cdis : 1;
11053 uint64_t isrd_st_ram3_flip : 2;
11054 uint64_t isrm_st_ram0_cdis : 1;
11055 uint64_t isrm_st_ram0_flip : 2;
11056 uint64_t isrm_st_ram1_cdis : 1;
11057 uint64_t isrm_st_ram1_flip : 2;
11058 uint64_t isrm_st_ram2_cdis : 1;
11059 uint64_t isrm_st_ram2_flip : 2;
11060 uint64_t isrm_ca_cm_ram_cdis : 1;
11061 uint64_t isrm_ca_cm_ram_flip : 2;
11062 uint64_t isrm_ca_iinst_ram_cdis : 1;
11063 uint64_t isrm_ca_iinst_ram_flip : 2;
11064 uint64_t flshb_cache_hi_ram_cdis : 1;
11065 uint64_t flshb_cache_hi_ram_flip : 2;
11066 uint64_t flshb_cache_lo_ram_cdis : 1;
11067 uint64_t flshb_cache_lo_ram_flip : 2;
11068 #endif
11069 } cn73xx;
11070 struct cvmx_pko_pdm_ecc_ctl0_s cn78xx;
11071 struct cvmx_pko_pdm_ecc_ctl0_s cn78xxp1;
11072 struct cvmx_pko_pdm_ecc_ctl0_cn73xx cnf75xx;
11073 };
11074 typedef union cvmx_pko_pdm_ecc_ctl0 cvmx_pko_pdm_ecc_ctl0_t;
11075
11076
11077
11078
11079 union cvmx_pko_pdm_ecc_ctl1 {
11080 uint64_t u64;
11081 struct cvmx_pko_pdm_ecc_ctl1_s {
11082 #ifdef __BIG_ENDIAN_BITFIELD
11083 uint64_t reserved_15_63 : 49;
11084 uint64_t buf_wm_ram_flip : 2;
11085 uint64_t buf_wm_ram_cdis : 1;
11086 uint64_t mwp_mem0_ram_flip : 2;
11087 uint64_t mwp_mem1_ram_flip : 2;
11088 uint64_t mwp_mem2_ram_flip : 2;
11089 uint64_t mwp_mem3_ram_flip : 2;
11090 uint64_t mwp_ram_cdis : 1;
11091 uint64_t minpad_ram_flip : 2;
11092 uint64_t minpad_ram_cdis : 1;
11093 #else
11094 uint64_t minpad_ram_cdis : 1;
11095 uint64_t minpad_ram_flip : 2;
11096 uint64_t mwp_ram_cdis : 1;
11097 uint64_t mwp_mem3_ram_flip : 2;
11098 uint64_t mwp_mem2_ram_flip : 2;
11099 uint64_t mwp_mem1_ram_flip : 2;
11100 uint64_t mwp_mem0_ram_flip : 2;
11101 uint64_t buf_wm_ram_cdis : 1;
11102 uint64_t buf_wm_ram_flip : 2;
11103 uint64_t reserved_15_63 : 49;
11104 #endif
11105 } s;
11106 struct cvmx_pko_pdm_ecc_ctl1_s cn73xx;
11107 struct cvmx_pko_pdm_ecc_ctl1_s cn78xx;
11108 struct cvmx_pko_pdm_ecc_ctl1_s cn78xxp1;
11109 struct cvmx_pko_pdm_ecc_ctl1_s cnf75xx;
11110 };
11111 typedef union cvmx_pko_pdm_ecc_ctl1 cvmx_pko_pdm_ecc_ctl1_t;
11112
11113
11114
11115
11116 union cvmx_pko_pdm_ecc_dbe_sts0 {
11117 uint64_t u64;
11118 struct cvmx_pko_pdm_ecc_dbe_sts0_s {
11119 #ifdef __BIG_ENDIAN_BITFIELD
11120 uint64_t flshb_cache_lo_ram_dbe : 1;
11121 uint64_t flshb_cache_hi_ram_dbe : 1;
11122 uint64_t isrm_ca_iinst_ram_dbe : 1;
11123 uint64_t isrm_ca_cm_ram_dbe : 1;
11124 uint64_t isrm_st_ram2_dbe : 1;
11125 uint64_t isrm_st_ram1_dbe : 1;
11126 uint64_t isrm_st_ram0_dbe : 1;
11127 uint64_t isrd_st_ram3_dbe : 1;
11128 uint64_t isrd_st_ram2_dbe : 1;
11129 uint64_t isrd_st_ram1_dbe : 1;
11130 uint64_t isrd_st_ram0_dbe : 1;
11131 uint64_t drp_hi_ram_dbe : 1;
11132 uint64_t drp_lo_ram_dbe : 1;
11133 uint64_t dwp_hi_ram_dbe : 1;
11134 uint64_t dwp_lo_ram_dbe : 1;
11135 uint64_t mwp_hi_ram_dbe : 1;
11136 uint64_t mwp_lo_ram_dbe : 1;
11137 uint64_t fillb_m_rsp_ram_hi_dbe : 1;
11138 uint64_t fillb_m_rsp_ram_lo_dbe : 1;
11139 uint64_t fillb_d_rsp_ram_hi_dbe : 1;
11140 uint64_t fillb_d_rsp_ram_lo_dbe : 1;
11141 uint64_t minpad_ram_dbe : 1;
11142 uint64_t mwp_hi_spt_ram_dbe : 1;
11143 uint64_t mwp_lo_spt_ram_dbe : 1;
11144 uint64_t buf_wm_ram_dbe : 1;
11145 uint64_t reserved_0_38 : 39;
11146 #else
11147 uint64_t reserved_0_38 : 39;
11148 uint64_t buf_wm_ram_dbe : 1;
11149 uint64_t mwp_lo_spt_ram_dbe : 1;
11150 uint64_t mwp_hi_spt_ram_dbe : 1;
11151 uint64_t minpad_ram_dbe : 1;
11152 uint64_t fillb_d_rsp_ram_lo_dbe : 1;
11153 uint64_t fillb_d_rsp_ram_hi_dbe : 1;
11154 uint64_t fillb_m_rsp_ram_lo_dbe : 1;
11155 uint64_t fillb_m_rsp_ram_hi_dbe : 1;
11156 uint64_t mwp_lo_ram_dbe : 1;
11157 uint64_t mwp_hi_ram_dbe : 1;
11158 uint64_t dwp_lo_ram_dbe : 1;
11159 uint64_t dwp_hi_ram_dbe : 1;
11160 uint64_t drp_lo_ram_dbe : 1;
11161 uint64_t drp_hi_ram_dbe : 1;
11162 uint64_t isrd_st_ram0_dbe : 1;
11163 uint64_t isrd_st_ram1_dbe : 1;
11164 uint64_t isrd_st_ram2_dbe : 1;
11165 uint64_t isrd_st_ram3_dbe : 1;
11166 uint64_t isrm_st_ram0_dbe : 1;
11167 uint64_t isrm_st_ram1_dbe : 1;
11168 uint64_t isrm_st_ram2_dbe : 1;
11169 uint64_t isrm_ca_cm_ram_dbe : 1;
11170 uint64_t isrm_ca_iinst_ram_dbe : 1;
11171 uint64_t flshb_cache_hi_ram_dbe : 1;
11172 uint64_t flshb_cache_lo_ram_dbe : 1;
11173 #endif
11174 } s;
11175 struct cvmx_pko_pdm_ecc_dbe_sts0_s cn73xx;
11176 struct cvmx_pko_pdm_ecc_dbe_sts0_s cn78xx;
11177 struct cvmx_pko_pdm_ecc_dbe_sts0_s cn78xxp1;
11178 struct cvmx_pko_pdm_ecc_dbe_sts0_s cnf75xx;
11179 };
11180 typedef union cvmx_pko_pdm_ecc_dbe_sts0 cvmx_pko_pdm_ecc_dbe_sts0_t;
11181
11182
11183
11184
11185 union cvmx_pko_pdm_ecc_dbe_sts_cmb0 {
11186 uint64_t u64;
11187 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s {
11188 #ifdef __BIG_ENDIAN_BITFIELD
11189 uint64_t pdm_dbe_cmb0 : 1;
11190
11191
11192
11193 uint64_t reserved_0_62 : 63;
11194 #else
11195 uint64_t reserved_0_62 : 63;
11196 uint64_t pdm_dbe_cmb0 : 1;
11197 #endif
11198 } s;
11199 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s cn73xx;
11200 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s cn78xx;
11201 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s cn78xxp1;
11202 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s cnf75xx;
11203 };
11204 typedef union cvmx_pko_pdm_ecc_dbe_sts_cmb0 cvmx_pko_pdm_ecc_dbe_sts_cmb0_t;
11205
11206
11207
11208
11209 union cvmx_pko_pdm_ecc_sbe_sts0 {
11210 uint64_t u64;
11211 struct cvmx_pko_pdm_ecc_sbe_sts0_s {
11212 #ifdef __BIG_ENDIAN_BITFIELD
11213 uint64_t flshb_cache_lo_ram_sbe : 1;
11214 uint64_t flshb_cache_hi_ram_sbe : 1;
11215 uint64_t isrm_ca_iinst_ram_sbe : 1;
11216 uint64_t isrm_ca_cm_ram_sbe : 1;
11217 uint64_t isrm_st_ram2_sbe : 1;
11218 uint64_t isrm_st_ram1_sbe : 1;
11219 uint64_t isrm_st_ram0_sbe : 1;
11220 uint64_t isrd_st_ram3_sbe : 1;
11221 uint64_t isrd_st_ram2_sbe : 1;
11222 uint64_t isrd_st_ram1_sbe : 1;
11223 uint64_t isrd_st_ram0_sbe : 1;
11224 uint64_t drp_hi_ram_sbe : 1;
11225 uint64_t drp_lo_ram_sbe : 1;
11226 uint64_t dwp_hi_ram_sbe : 1;
11227 uint64_t dwp_lo_ram_sbe : 1;
11228 uint64_t mwp_hi_ram_sbe : 1;
11229 uint64_t mwp_lo_ram_sbe : 1;
11230 uint64_t fillb_m_rsp_ram_hi_sbe : 1;
11231 uint64_t fillb_m_rsp_ram_lo_sbe : 1;
11232 uint64_t fillb_d_rsp_ram_hi_sbe : 1;
11233 uint64_t fillb_d_rsp_ram_lo_sbe : 1;
11234 uint64_t minpad_ram_sbe : 1;
11235 uint64_t mwp_hi_spt_ram_sbe : 1;
11236 uint64_t mwp_lo_spt_ram_sbe : 1;
11237 uint64_t buf_wm_ram_sbe : 1;
11238 uint64_t reserved_0_38 : 39;
11239 #else
11240 uint64_t reserved_0_38 : 39;
11241 uint64_t buf_wm_ram_sbe : 1;
11242 uint64_t mwp_lo_spt_ram_sbe : 1;
11243 uint64_t mwp_hi_spt_ram_sbe : 1;
11244 uint64_t minpad_ram_sbe : 1;
11245 uint64_t fillb_d_rsp_ram_lo_sbe : 1;
11246 uint64_t fillb_d_rsp_ram_hi_sbe : 1;
11247 uint64_t fillb_m_rsp_ram_lo_sbe : 1;
11248 uint64_t fillb_m_rsp_ram_hi_sbe : 1;
11249 uint64_t mwp_lo_ram_sbe : 1;
11250 uint64_t mwp_hi_ram_sbe : 1;
11251 uint64_t dwp_lo_ram_sbe : 1;
11252 uint64_t dwp_hi_ram_sbe : 1;
11253 uint64_t drp_lo_ram_sbe : 1;
11254 uint64_t drp_hi_ram_sbe : 1;
11255 uint64_t isrd_st_ram0_sbe : 1;
11256 uint64_t isrd_st_ram1_sbe : 1;
11257 uint64_t isrd_st_ram2_sbe : 1;
11258 uint64_t isrd_st_ram3_sbe : 1;
11259 uint64_t isrm_st_ram0_sbe : 1;
11260 uint64_t isrm_st_ram1_sbe : 1;
11261 uint64_t isrm_st_ram2_sbe : 1;
11262 uint64_t isrm_ca_cm_ram_sbe : 1;
11263 uint64_t isrm_ca_iinst_ram_sbe : 1;
11264 uint64_t flshb_cache_hi_ram_sbe : 1;
11265 uint64_t flshb_cache_lo_ram_sbe : 1;
11266 #endif
11267 } s;
11268 struct cvmx_pko_pdm_ecc_sbe_sts0_s cn73xx;
11269 struct cvmx_pko_pdm_ecc_sbe_sts0_s cn78xx;
11270 struct cvmx_pko_pdm_ecc_sbe_sts0_s cn78xxp1;
11271 struct cvmx_pko_pdm_ecc_sbe_sts0_s cnf75xx;
11272 };
11273 typedef union cvmx_pko_pdm_ecc_sbe_sts0 cvmx_pko_pdm_ecc_sbe_sts0_t;
11274
11275
11276
11277
11278 union cvmx_pko_pdm_ecc_sbe_sts_cmb0 {
11279 uint64_t u64;
11280 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s {
11281 #ifdef __BIG_ENDIAN_BITFIELD
11282 uint64_t pdm_sbe_cmb0 : 1;
11283
11284
11285
11286 uint64_t reserved_0_62 : 63;
11287 #else
11288 uint64_t reserved_0_62 : 63;
11289 uint64_t pdm_sbe_cmb0 : 1;
11290 #endif
11291 } s;
11292 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s cn73xx;
11293 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s cn78xx;
11294 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s cn78xxp1;
11295 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s cnf75xx;
11296 };
11297 typedef union cvmx_pko_pdm_ecc_sbe_sts_cmb0 cvmx_pko_pdm_ecc_sbe_sts_cmb0_t;
11298
11299
11300
11301
11302 union cvmx_pko_pdm_fillb_dbg0 {
11303 uint64_t u64;
11304 struct cvmx_pko_pdm_fillb_dbg0_s {
11305 #ifdef __BIG_ENDIAN_BITFIELD
11306 uint64_t reserved_57_63 : 7;
11307 uint64_t pd_seq : 5;
11308 uint64_t resp_pd_seq : 5;
11309 uint64_t d_rsp_lo_ram_addr_sel : 2;
11310
11311
11312
11313
11314 uint64_t d_rsp_hi_ram_addr_sel : 2;
11315
11316
11317
11318
11319 uint64_t d_rsp_rd_seq : 5;
11320 uint64_t d_rsp_fifo_rd_seq : 5;
11321 uint64_t d_fill_req_fifo_val : 1;
11322 uint64_t d_rsp_ram_valid : 32;
11323 #else
11324 uint64_t d_rsp_ram_valid : 32;
11325 uint64_t d_fill_req_fifo_val : 1;
11326 uint64_t d_rsp_fifo_rd_seq : 5;
11327 uint64_t d_rsp_rd_seq : 5;
11328 uint64_t d_rsp_hi_ram_addr_sel : 2;
11329 uint64_t d_rsp_lo_ram_addr_sel : 2;
11330 uint64_t resp_pd_seq : 5;
11331 uint64_t pd_seq : 5;
11332 uint64_t reserved_57_63 : 7;
11333 #endif
11334 } s;
11335 struct cvmx_pko_pdm_fillb_dbg0_s cn73xx;
11336 struct cvmx_pko_pdm_fillb_dbg0_s cn78xx;
11337 struct cvmx_pko_pdm_fillb_dbg0_s cn78xxp1;
11338 struct cvmx_pko_pdm_fillb_dbg0_s cnf75xx;
11339 };
11340 typedef union cvmx_pko_pdm_fillb_dbg0 cvmx_pko_pdm_fillb_dbg0_t;
11341
11342
11343
11344
11345 union cvmx_pko_pdm_fillb_dbg1 {
11346 uint64_t u64;
11347 struct cvmx_pko_pdm_fillb_dbg1_s {
11348 #ifdef __BIG_ENDIAN_BITFIELD
11349 uint64_t reserved_57_63 : 7;
11350 uint64_t mp_seq : 5;
11351 uint64_t resp_mp_seq : 5;
11352 uint64_t m_rsp_lo_ram_addr_sel : 2;
11353
11354
11355
11356
11357 uint64_t m_rsp_hi_ram_addr_sel : 2;
11358
11359
11360
11361
11362 uint64_t m_rsp_rd_seq : 5;
11363 uint64_t m_rsp_fifo_rd_seq : 5;
11364 uint64_t m_fill_req_fifo_val : 1;
11365 uint64_t m_rsp_ram_valid : 32;
11366 #else
11367 uint64_t m_rsp_ram_valid : 32;
11368 uint64_t m_fill_req_fifo_val : 1;
11369 uint64_t m_rsp_fifo_rd_seq : 5;
11370 uint64_t m_rsp_rd_seq : 5;
11371 uint64_t m_rsp_hi_ram_addr_sel : 2;
11372 uint64_t m_rsp_lo_ram_addr_sel : 2;
11373 uint64_t resp_mp_seq : 5;
11374 uint64_t mp_seq : 5;
11375 uint64_t reserved_57_63 : 7;
11376 #endif
11377 } s;
11378 struct cvmx_pko_pdm_fillb_dbg1_s cn73xx;
11379 struct cvmx_pko_pdm_fillb_dbg1_s cn78xx;
11380 struct cvmx_pko_pdm_fillb_dbg1_s cn78xxp1;
11381 struct cvmx_pko_pdm_fillb_dbg1_s cnf75xx;
11382 };
11383 typedef union cvmx_pko_pdm_fillb_dbg1 cvmx_pko_pdm_fillb_dbg1_t;
11384
11385
11386
11387
11388 union cvmx_pko_pdm_fillb_dbg2 {
11389 uint64_t u64;
11390 struct cvmx_pko_pdm_fillb_dbg2_s {
11391 #ifdef __BIG_ENDIAN_BITFIELD
11392 uint64_t reserved_9_63 : 55;
11393 uint64_t fillb_sm : 5;
11394 uint64_t reserved_3_3 : 1;
11395 uint64_t iobp0_credit_cntr : 3;
11396 #else
11397 uint64_t iobp0_credit_cntr : 3;
11398 uint64_t reserved_3_3 : 1;
11399 uint64_t fillb_sm : 5;
11400 uint64_t reserved_9_63 : 55;
11401 #endif
11402 } s;
11403 struct cvmx_pko_pdm_fillb_dbg2_s cn73xx;
11404 struct cvmx_pko_pdm_fillb_dbg2_s cn78xx;
11405 struct cvmx_pko_pdm_fillb_dbg2_s cn78xxp1;
11406 struct cvmx_pko_pdm_fillb_dbg2_s cnf75xx;
11407 };
11408 typedef union cvmx_pko_pdm_fillb_dbg2 cvmx_pko_pdm_fillb_dbg2_t;
11409
11410
11411
11412
11413 union cvmx_pko_pdm_flshb_dbg0 {
11414 uint64_t u64;
11415 struct cvmx_pko_pdm_flshb_dbg0_s {
11416 #ifdef __BIG_ENDIAN_BITFIELD
11417 uint64_t reserved_44_63 : 20;
11418 uint64_t flshb_sm : 7;
11419 uint64_t flshb_ctl_sm : 9;
11420 uint64_t cam_hptr : 5;
11421 uint64_t cam_tptr : 5;
11422 uint64_t expected_stdns : 6;
11423 uint64_t d_flshb_eot_cntr : 3;
11424 uint64_t m_flshb_eot_cntr : 3;
11425 uint64_t ncbi_credit_cntr : 6;
11426 #else
11427 uint64_t ncbi_credit_cntr : 6;
11428 uint64_t m_flshb_eot_cntr : 3;
11429 uint64_t d_flshb_eot_cntr : 3;
11430 uint64_t expected_stdns : 6;
11431 uint64_t cam_tptr : 5;
11432 uint64_t cam_hptr : 5;
11433 uint64_t flshb_ctl_sm : 9;
11434 uint64_t flshb_sm : 7;
11435 uint64_t reserved_44_63 : 20;
11436 #endif
11437 } s;
11438 struct cvmx_pko_pdm_flshb_dbg0_s cn73xx;
11439 struct cvmx_pko_pdm_flshb_dbg0_s cn78xx;
11440 struct cvmx_pko_pdm_flshb_dbg0_s cn78xxp1;
11441 struct cvmx_pko_pdm_flshb_dbg0_s cnf75xx;
11442 };
11443 typedef union cvmx_pko_pdm_flshb_dbg0 cvmx_pko_pdm_flshb_dbg0_t;
11444
11445
11446
11447
11448 union cvmx_pko_pdm_flshb_dbg1 {
11449 uint64_t u64;
11450 struct cvmx_pko_pdm_flshb_dbg1_s {
11451 #ifdef __BIG_ENDIAN_BITFIELD
11452 uint64_t cam_stdn : 32;
11453 uint64_t cam_valid : 32;
11454 #else
11455 uint64_t cam_valid : 32;
11456 uint64_t cam_stdn : 32;
11457 #endif
11458 } s;
11459 struct cvmx_pko_pdm_flshb_dbg1_s cn73xx;
11460 struct cvmx_pko_pdm_flshb_dbg1_s cn78xx;
11461 struct cvmx_pko_pdm_flshb_dbg1_s cn78xxp1;
11462 struct cvmx_pko_pdm_flshb_dbg1_s cnf75xx;
11463 };
11464 typedef union cvmx_pko_pdm_flshb_dbg1 cvmx_pko_pdm_flshb_dbg1_t;
11465
11466
11467
11468
11469
11470
11471
11472 union cvmx_pko_pdm_intf_dbg_rd {
11473 uint64_t u64;
11474 struct cvmx_pko_pdm_intf_dbg_rd_s {
11475 #ifdef __BIG_ENDIAN_BITFIELD
11476 uint64_t reserved_48_63 : 16;
11477 uint64_t in_flight : 8;
11478 uint64_t pdm_req_cred_cnt : 8;
11479 uint64_t pse_buf_waddr : 8;
11480 uint64_t pse_buf_raddr : 8;
11481 uint64_t resp_buf_waddr : 8;
11482 uint64_t resp_buf_raddr : 8;
11483 #else
11484 uint64_t resp_buf_raddr : 8;
11485 uint64_t resp_buf_waddr : 8;
11486 uint64_t pse_buf_raddr : 8;
11487 uint64_t pse_buf_waddr : 8;
11488 uint64_t pdm_req_cred_cnt : 8;
11489 uint64_t in_flight : 8;
11490 uint64_t reserved_48_63 : 16;
11491 #endif
11492 } s;
11493 struct cvmx_pko_pdm_intf_dbg_rd_s cn73xx;
11494 struct cvmx_pko_pdm_intf_dbg_rd_s cn78xx;
11495 struct cvmx_pko_pdm_intf_dbg_rd_s cn78xxp1;
11496 struct cvmx_pko_pdm_intf_dbg_rd_s cnf75xx;
11497 };
11498 typedef union cvmx_pko_pdm_intf_dbg_rd cvmx_pko_pdm_intf_dbg_rd_t;
11499
11500
11501
11502
11503 union cvmx_pko_pdm_isrd_dbg {
11504 uint64_t u64;
11505 struct cvmx_pko_pdm_isrd_dbg_s {
11506 #ifdef __BIG_ENDIAN_BITFIELD
11507 uint64_t isrd_vals_in : 4;
11508
11509
11510
11511
11512 uint64_t reserved_59_59 : 1;
11513 uint64_t req_hptr : 6;
11514 uint64_t rdy_hptr : 6;
11515 uint64_t reserved_44_46 : 3;
11516 uint64_t in_arb_reqs : 8;
11517
11518
11519
11520
11521
11522
11523
11524
11525 uint64_t in_arb_gnts : 7;
11526
11527
11528
11529
11530
11531
11532
11533 uint64_t cmt_arb_reqs : 7;
11534
11535
11536
11537
11538
11539
11540
11541 uint64_t cmt_arb_gnts : 7;
11542
11543
11544
11545
11546
11547
11548
11549 uint64_t in_use : 4;
11550
11551
11552
11553
11554 uint64_t has_cred : 4;
11555
11556
11557
11558
11559
11560 uint64_t val_exec : 7;
11561
11562
11563
11564
11565
11566
11567
11568
11569 #else
11570 uint64_t val_exec : 7;
11571 uint64_t has_cred : 4;
11572 uint64_t in_use : 4;
11573 uint64_t cmt_arb_gnts : 7;
11574 uint64_t cmt_arb_reqs : 7;
11575 uint64_t in_arb_gnts : 7;
11576 uint64_t in_arb_reqs : 8;
11577 uint64_t reserved_44_46 : 3;
11578 uint64_t rdy_hptr : 6;
11579 uint64_t req_hptr : 6;
11580 uint64_t reserved_59_59 : 1;
11581 uint64_t isrd_vals_in : 4;
11582 #endif
11583 } s;
11584 struct cvmx_pko_pdm_isrd_dbg_s cn73xx;
11585 struct cvmx_pko_pdm_isrd_dbg_s cn78xx;
11586 struct cvmx_pko_pdm_isrd_dbg_cn78xxp1 {
11587 #ifdef __BIG_ENDIAN_BITFIELD
11588 uint64_t reserved_44_63 : 20;
11589 uint64_t in_arb_reqs : 8;
11590
11591
11592
11593
11594
11595
11596
11597
11598 uint64_t in_arb_gnts : 7;
11599
11600
11601
11602
11603
11604
11605
11606 uint64_t cmt_arb_reqs : 7;
11607
11608
11609
11610
11611
11612
11613
11614 uint64_t cmt_arb_gnts : 7;
11615
11616
11617
11618
11619
11620
11621
11622 uint64_t in_use : 4;
11623
11624
11625
11626
11627 uint64_t has_cred : 4;
11628
11629
11630
11631
11632
11633 uint64_t val_exec : 7;
11634
11635
11636
11637
11638
11639
11640
11641
11642 #else
11643 uint64_t val_exec : 7;
11644 uint64_t has_cred : 4;
11645 uint64_t in_use : 4;
11646 uint64_t cmt_arb_gnts : 7;
11647 uint64_t cmt_arb_reqs : 7;
11648 uint64_t in_arb_gnts : 7;
11649 uint64_t in_arb_reqs : 8;
11650 uint64_t reserved_44_63 : 20;
11651 #endif
11652 } cn78xxp1;
11653 struct cvmx_pko_pdm_isrd_dbg_s cnf75xx;
11654 };
11655 typedef union cvmx_pko_pdm_isrd_dbg cvmx_pko_pdm_isrd_dbg_t;
11656
11657
11658
11659
11660 union cvmx_pko_pdm_isrd_dbg_dq {
11661 uint64_t u64;
11662 struct cvmx_pko_pdm_isrd_dbg_dq_s {
11663 #ifdef __BIG_ENDIAN_BITFIELD
11664 uint64_t reserved_46_63 : 18;
11665 uint64_t pebrd_sic_dq : 10;
11666 uint64_t reserved_34_35 : 2;
11667 uint64_t pebfill_sic_dq : 10;
11668 uint64_t reserved_22_23 : 2;
11669 uint64_t fr_sic_dq : 10;
11670 uint64_t reserved_10_11 : 2;
11671 uint64_t cp_sic_dq : 10;
11672 #else
11673 uint64_t cp_sic_dq : 10;
11674 uint64_t reserved_10_11 : 2;
11675 uint64_t fr_sic_dq : 10;
11676 uint64_t reserved_22_23 : 2;
11677 uint64_t pebfill_sic_dq : 10;
11678 uint64_t reserved_34_35 : 2;
11679 uint64_t pebrd_sic_dq : 10;
11680 uint64_t reserved_46_63 : 18;
11681 #endif
11682 } s;
11683 struct cvmx_pko_pdm_isrd_dbg_dq_s cn73xx;
11684 struct cvmx_pko_pdm_isrd_dbg_dq_s cn78xx;
11685 struct cvmx_pko_pdm_isrd_dbg_dq_s cn78xxp1;
11686 struct cvmx_pko_pdm_isrd_dbg_dq_s cnf75xx;
11687 };
11688 typedef union cvmx_pko_pdm_isrd_dbg_dq cvmx_pko_pdm_isrd_dbg_dq_t;
11689
11690
11691
11692
11693 union cvmx_pko_pdm_isrm_dbg {
11694 uint64_t u64;
11695 struct cvmx_pko_pdm_isrm_dbg_s {
11696 #ifdef __BIG_ENDIAN_BITFIELD
11697 uint64_t val_in : 3;
11698
11699
11700
11701 uint64_t reserved_34_60 : 27;
11702 uint64_t in_arb_reqs : 7;
11703
11704
11705
11706
11707
11708
11709
11710 uint64_t in_arb_gnts : 6;
11711
11712
11713
11714
11715
11716
11717 uint64_t cmt_arb_reqs : 6;
11718
11719
11720
11721
11722
11723
11724 uint64_t cmt_arb_gnts : 6;
11725
11726
11727
11728
11729
11730
11731 uint64_t in_use : 3;
11732
11733
11734
11735 uint64_t has_cred : 3;
11736
11737
11738
11739
11740 uint64_t val_exec : 3;
11741
11742
11743
11744
11745 #else
11746 uint64_t val_exec : 3;
11747 uint64_t has_cred : 3;
11748 uint64_t in_use : 3;
11749 uint64_t cmt_arb_gnts : 6;
11750 uint64_t cmt_arb_reqs : 6;
11751 uint64_t in_arb_gnts : 6;
11752 uint64_t in_arb_reqs : 7;
11753 uint64_t reserved_34_60 : 27;
11754 uint64_t val_in : 3;
11755 #endif
11756 } s;
11757 struct cvmx_pko_pdm_isrm_dbg_s cn73xx;
11758 struct cvmx_pko_pdm_isrm_dbg_s cn78xx;
11759 struct cvmx_pko_pdm_isrm_dbg_cn78xxp1 {
11760 #ifdef __BIG_ENDIAN_BITFIELD
11761 uint64_t reserved_34_63 : 30;
11762 uint64_t in_arb_reqs : 7;
11763
11764
11765
11766
11767
11768
11769
11770 uint64_t in_arb_gnts : 6;
11771
11772
11773
11774
11775
11776
11777 uint64_t cmt_arb_reqs : 6;
11778
11779
11780
11781
11782
11783
11784 uint64_t cmt_arb_gnts : 6;
11785
11786
11787
11788
11789
11790
11791 uint64_t in_use : 3;
11792
11793
11794
11795 uint64_t has_cred : 3;
11796
11797
11798
11799
11800 uint64_t val_exec : 3;
11801
11802
11803
11804
11805 #else
11806 uint64_t val_exec : 3;
11807 uint64_t has_cred : 3;
11808 uint64_t in_use : 3;
11809 uint64_t cmt_arb_gnts : 6;
11810 uint64_t cmt_arb_reqs : 6;
11811 uint64_t in_arb_gnts : 6;
11812 uint64_t in_arb_reqs : 7;
11813 uint64_t reserved_34_63 : 30;
11814 #endif
11815 } cn78xxp1;
11816 struct cvmx_pko_pdm_isrm_dbg_s cnf75xx;
11817 };
11818 typedef union cvmx_pko_pdm_isrm_dbg cvmx_pko_pdm_isrm_dbg_t;
11819
11820
11821
11822
11823 union cvmx_pko_pdm_isrm_dbg_dq {
11824 uint64_t u64;
11825 struct cvmx_pko_pdm_isrm_dbg_dq_s {
11826 #ifdef __BIG_ENDIAN_BITFIELD
11827 uint64_t reserved_34_63 : 30;
11828 uint64_t ack_sic_dq : 10;
11829 uint64_t reserved_22_23 : 2;
11830 uint64_t fr_sic_dq : 10;
11831 uint64_t reserved_10_11 : 2;
11832 uint64_t cp_sic_dq : 10;
11833 #else
11834 uint64_t cp_sic_dq : 10;
11835 uint64_t reserved_10_11 : 2;
11836 uint64_t fr_sic_dq : 10;
11837 uint64_t reserved_22_23 : 2;
11838 uint64_t ack_sic_dq : 10;
11839 uint64_t reserved_34_63 : 30;
11840 #endif
11841 } s;
11842 struct cvmx_pko_pdm_isrm_dbg_dq_s cn73xx;
11843 struct cvmx_pko_pdm_isrm_dbg_dq_s cn78xx;
11844 struct cvmx_pko_pdm_isrm_dbg_dq_s cn78xxp1;
11845 struct cvmx_pko_pdm_isrm_dbg_dq_s cnf75xx;
11846 };
11847 typedef union cvmx_pko_pdm_isrm_dbg_dq cvmx_pko_pdm_isrm_dbg_dq_t;
11848
11849
11850
11851
11852 union cvmx_pko_pdm_mem_addr {
11853 uint64_t u64;
11854 struct cvmx_pko_pdm_mem_addr_s {
11855 #ifdef __BIG_ENDIAN_BITFIELD
11856 uint64_t memsel : 3;
11857
11858
11859
11860
11861
11862
11863 uint64_t reserved_17_60 : 44;
11864 uint64_t memaddr : 14;
11865 uint64_t reserved_2_2 : 1;
11866 uint64_t membanksel : 2;
11867
11868
11869 #else
11870 uint64_t membanksel : 2;
11871 uint64_t reserved_2_2 : 1;
11872 uint64_t memaddr : 14;
11873 uint64_t reserved_17_60 : 44;
11874 uint64_t memsel : 3;
11875 #endif
11876 } s;
11877 struct cvmx_pko_pdm_mem_addr_s cn73xx;
11878 struct cvmx_pko_pdm_mem_addr_s cn78xx;
11879 struct cvmx_pko_pdm_mem_addr_s cn78xxp1;
11880 struct cvmx_pko_pdm_mem_addr_s cnf75xx;
11881 };
11882 typedef union cvmx_pko_pdm_mem_addr cvmx_pko_pdm_mem_addr_t;
11883
11884
11885
11886
11887 union cvmx_pko_pdm_mem_data {
11888 uint64_t u64;
11889 struct cvmx_pko_pdm_mem_data_s {
11890 #ifdef __BIG_ENDIAN_BITFIELD
11891 uint64_t data : 64;
11892
11893
11894 #else
11895 uint64_t data : 64;
11896 #endif
11897 } s;
11898 struct cvmx_pko_pdm_mem_data_s cn73xx;
11899 struct cvmx_pko_pdm_mem_data_s cn78xx;
11900 struct cvmx_pko_pdm_mem_data_s cn78xxp1;
11901 struct cvmx_pko_pdm_mem_data_s cnf75xx;
11902 };
11903 typedef union cvmx_pko_pdm_mem_data cvmx_pko_pdm_mem_data_t;
11904
11905
11906
11907
11908 union cvmx_pko_pdm_mem_rw_ctl {
11909 uint64_t u64;
11910 struct cvmx_pko_pdm_mem_rw_ctl_s {
11911 #ifdef __BIG_ENDIAN_BITFIELD
11912 uint64_t reserved_2_63 : 62;
11913 uint64_t read : 1;
11914 uint64_t write : 1;
11915 #else
11916 uint64_t write : 1;
11917 uint64_t read : 1;
11918 uint64_t reserved_2_63 : 62;
11919 #endif
11920 } s;
11921 struct cvmx_pko_pdm_mem_rw_ctl_s cn73xx;
11922 struct cvmx_pko_pdm_mem_rw_ctl_s cn78xx;
11923 struct cvmx_pko_pdm_mem_rw_ctl_s cn78xxp1;
11924 struct cvmx_pko_pdm_mem_rw_ctl_s cnf75xx;
11925 };
11926 typedef union cvmx_pko_pdm_mem_rw_ctl cvmx_pko_pdm_mem_rw_ctl_t;
11927
11928
11929
11930
11931 union cvmx_pko_pdm_mem_rw_sts {
11932 uint64_t u64;
11933 struct cvmx_pko_pdm_mem_rw_sts_s {
11934 #ifdef __BIG_ENDIAN_BITFIELD
11935 uint64_t reserved_1_63 : 63;
11936 uint64_t readdone : 1;
11937 #else
11938 uint64_t readdone : 1;
11939 uint64_t reserved_1_63 : 63;
11940 #endif
11941 } s;
11942 struct cvmx_pko_pdm_mem_rw_sts_s cn73xx;
11943 struct cvmx_pko_pdm_mem_rw_sts_s cn78xx;
11944 struct cvmx_pko_pdm_mem_rw_sts_s cn78xxp1;
11945 struct cvmx_pko_pdm_mem_rw_sts_s cnf75xx;
11946 };
11947 typedef union cvmx_pko_pdm_mem_rw_sts cvmx_pko_pdm_mem_rw_sts_t;
11948
11949
11950
11951
11952 union cvmx_pko_pdm_mwpbuf_dbg {
11953 uint64_t u64;
11954 struct cvmx_pko_pdm_mwpbuf_dbg_s {
11955 #ifdef __BIG_ENDIAN_BITFIELD
11956 uint64_t reserved_49_63 : 15;
11957 uint64_t str_proc : 1;
11958 uint64_t cmd_proc : 1;
11959 uint64_t str_val : 1;
11960 uint64_t mem_data_val : 1;
11961 uint64_t insert_np : 1;
11962 uint64_t insert_mp : 1;
11963 uint64_t sel_nxt_ptr : 1;
11964 uint64_t load_val : 1;
11965 uint64_t rdy : 1;
11966 uint64_t cur_state : 3;
11967 uint64_t mem_rdy : 1;
11968 uint64_t str_rdy : 1;
11969 uint64_t contention_type : 2;
11970
11971 uint64_t track_rd_cnt : 6;
11972 uint64_t track_wr_cnt : 6;
11973 uint64_t mem_wen : 4;
11974
11975
11976
11977
11978 uint64_t mem_addr : 13;
11979 uint64_t mem_en : 4;
11980
11981
11982
11983
11984 #else
11985 uint64_t mem_en : 4;
11986 uint64_t mem_addr : 13;
11987 uint64_t mem_wen : 4;
11988 uint64_t track_wr_cnt : 6;
11989 uint64_t track_rd_cnt : 6;
11990 uint64_t contention_type : 2;
11991 uint64_t str_rdy : 1;
11992 uint64_t mem_rdy : 1;
11993 uint64_t cur_state : 3;
11994 uint64_t rdy : 1;
11995 uint64_t load_val : 1;
11996 uint64_t sel_nxt_ptr : 1;
11997 uint64_t insert_mp : 1;
11998 uint64_t insert_np : 1;
11999 uint64_t mem_data_val : 1;
12000 uint64_t str_val : 1;
12001 uint64_t cmd_proc : 1;
12002 uint64_t str_proc : 1;
12003 uint64_t reserved_49_63 : 15;
12004 #endif
12005 } s;
12006 struct cvmx_pko_pdm_mwpbuf_dbg_cn73xx {
12007 #ifdef __BIG_ENDIAN_BITFIELD
12008 uint64_t reserved_49_63 : 15;
12009 uint64_t str_proc : 1;
12010 uint64_t cmd_proc : 1;
12011 uint64_t str_val : 1;
12012 uint64_t mem_data_val : 1;
12013 uint64_t insert_np : 1;
12014 uint64_t insert_mp : 1;
12015 uint64_t sel_nxt_ptr : 1;
12016 uint64_t load_val : 1;
12017 uint64_t rdy : 1;
12018 uint64_t cur_state : 3;
12019 uint64_t mem_rdy : 1;
12020 uint64_t str_rdy : 1;
12021 uint64_t contention_type : 2;
12022
12023 uint64_t reserved_21_32 : 12;
12024 uint64_t mem_wen : 4;
12025
12026
12027
12028
12029 uint64_t reserved_15_16 : 2;
12030 uint64_t mem_addr : 11;
12031 uint64_t mem_en : 4;
12032
12033
12034
12035
12036 #else
12037 uint64_t mem_en : 4;
12038 uint64_t mem_addr : 11;
12039 uint64_t reserved_15_16 : 2;
12040 uint64_t mem_wen : 4;
12041 uint64_t reserved_21_32 : 12;
12042 uint64_t contention_type : 2;
12043 uint64_t str_rdy : 1;
12044 uint64_t mem_rdy : 1;
12045 uint64_t cur_state : 3;
12046 uint64_t rdy : 1;
12047 uint64_t load_val : 1;
12048 uint64_t sel_nxt_ptr : 1;
12049 uint64_t insert_mp : 1;
12050 uint64_t insert_np : 1;
12051 uint64_t mem_data_val : 1;
12052 uint64_t str_val : 1;
12053 uint64_t cmd_proc : 1;
12054 uint64_t str_proc : 1;
12055 uint64_t reserved_49_63 : 15;
12056 #endif
12057 } cn73xx;
12058 struct cvmx_pko_pdm_mwpbuf_dbg_s cn78xx;
12059 struct cvmx_pko_pdm_mwpbuf_dbg_s cn78xxp1;
12060 struct cvmx_pko_pdm_mwpbuf_dbg_cn73xx cnf75xx;
12061 };
12062 typedef union cvmx_pko_pdm_mwpbuf_dbg cvmx_pko_pdm_mwpbuf_dbg_t;
12063
12064
12065
12066
12067 union cvmx_pko_pdm_sts {
12068 uint64_t u64;
12069 struct cvmx_pko_pdm_sts_s {
12070 #ifdef __BIG_ENDIAN_BITFIELD
12071 uint64_t reserved_38_63 : 26;
12072 uint64_t cp_stalled_thrshld_hit : 1;
12073 uint64_t reserved_35_36 : 2;
12074 uint64_t mwpbuf_data_val_err : 1;
12075
12076 uint64_t drpbuf_data_val_err : 1;
12077
12078 uint64_t dwpbuf_data_val_err : 1;
12079
12080 uint64_t reserved_30_31 : 2;
12081 uint64_t qcmd_iobx_err_sts : 4;
12082
12083
12084
12085 uint64_t qcmd_iobx_err : 1;
12086
12087
12088
12089 uint64_t sendpkt_lmtdma_err_sts : 4;
12090
12091
12092
12093 uint64_t sendpkt_lmtdma_err : 1;
12094
12095
12096
12097 uint64_t sendpkt_lmtst_err_sts : 4;
12098
12099
12100
12101 uint64_t sendpkt_lmtst_err : 1;
12102
12103
12104
12105 uint64_t fpa_no_ptrs : 1;
12106
12107 uint64_t reserved_12_13 : 2;
12108 uint64_t cp_sendpkt_err_no_drp_code : 2;
12109
12110
12111
12112 uint64_t cp_sendpkt_err_no_drp : 1;
12113
12114
12115 uint64_t reserved_7_8 : 2;
12116 uint64_t cp_sendpkt_err_drop_code : 3;
12117
12118
12119
12120 uint64_t cp_sendpkt_err_drop : 1;
12121
12122 uint64_t reserved_1_2 : 2;
12123 uint64_t desc_crc_err : 1;
12124
12125 #else
12126 uint64_t desc_crc_err : 1;
12127 uint64_t reserved_1_2 : 2;
12128 uint64_t cp_sendpkt_err_drop : 1;
12129 uint64_t cp_sendpkt_err_drop_code : 3;
12130 uint64_t reserved_7_8 : 2;
12131 uint64_t cp_sendpkt_err_no_drp : 1;
12132 uint64_t cp_sendpkt_err_no_drp_code : 2;
12133 uint64_t reserved_12_13 : 2;
12134 uint64_t fpa_no_ptrs : 1;
12135 uint64_t sendpkt_lmtst_err : 1;
12136 uint64_t sendpkt_lmtst_err_sts : 4;
12137 uint64_t sendpkt_lmtdma_err : 1;
12138 uint64_t sendpkt_lmtdma_err_sts : 4;
12139 uint64_t qcmd_iobx_err : 1;
12140 uint64_t qcmd_iobx_err_sts : 4;
12141 uint64_t reserved_30_31 : 2;
12142 uint64_t dwpbuf_data_val_err : 1;
12143 uint64_t drpbuf_data_val_err : 1;
12144 uint64_t mwpbuf_data_val_err : 1;
12145 uint64_t reserved_35_36 : 2;
12146 uint64_t cp_stalled_thrshld_hit : 1;
12147 uint64_t reserved_38_63 : 26;
12148 #endif
12149 } s;
12150 struct cvmx_pko_pdm_sts_s cn73xx;
12151 struct cvmx_pko_pdm_sts_s cn78xx;
12152 struct cvmx_pko_pdm_sts_s cn78xxp1;
12153 struct cvmx_pko_pdm_sts_s cnf75xx;
12154 };
12155 typedef union cvmx_pko_pdm_sts cvmx_pko_pdm_sts_t;
12156
12157
12158
12159
12160
12161
12162
12163 union cvmx_pko_peb_bist_status {
12164 uint64_t u64;
12165 struct cvmx_pko_peb_bist_status_s {
12166 #ifdef __BIG_ENDIAN_BITFIELD
12167 uint64_t reserved_26_63 : 38;
12168 uint64_t add_work_fifo : 1;
12169 uint64_t pdm_pse_buf_ram : 1;
12170 uint64_t iobp0_fifo_ram : 1;
12171 uint64_t iobp1_fifo_ram : 1;
12172 uint64_t state_mem0 : 1;
12173 uint64_t reserved_19_20 : 2;
12174 uint64_t state_mem3 : 1;
12175 uint64_t iobp1_uid_fifo_ram : 1;
12176 uint64_t nxt_link_ptr_ram : 1;
12177 uint64_t pd_bank0_ram : 1;
12178 uint64_t pd_bank1_ram : 1;
12179 uint64_t pd_bank2_ram : 1;
12180 uint64_t pd_bank3_ram : 1;
12181 uint64_t pd_var_bank_ram : 1;
12182 uint64_t pdm_resp_buf_ram : 1;
12183 uint64_t tx_fifo_pkt_ram : 1;
12184 uint64_t tx_fifo_hdr_ram : 1;
12185 uint64_t tx_fifo_crc_ram : 1;
12186 uint64_t ts_addwork_ram : 1;
12187 uint64_t send_mem_ts_fifo : 1;
12188 uint64_t send_mem_stdn_fifo : 1;
12189 uint64_t send_mem_fifo : 1;
12190 uint64_t pkt_mrk_ram : 1;
12191 uint64_t peb_st_inf_ram : 1;
12192 uint64_t peb_sm_jmp_ram : 1;
12193 #else
12194 uint64_t peb_sm_jmp_ram : 1;
12195 uint64_t peb_st_inf_ram : 1;
12196 uint64_t pkt_mrk_ram : 1;
12197 uint64_t send_mem_fifo : 1;
12198 uint64_t send_mem_stdn_fifo : 1;
12199 uint64_t send_mem_ts_fifo : 1;
12200 uint64_t ts_addwork_ram : 1;
12201 uint64_t tx_fifo_crc_ram : 1;
12202 uint64_t tx_fifo_hdr_ram : 1;
12203 uint64_t tx_fifo_pkt_ram : 1;
12204 uint64_t pdm_resp_buf_ram : 1;
12205 uint64_t pd_var_bank_ram : 1;
12206 uint64_t pd_bank3_ram : 1;
12207 uint64_t pd_bank2_ram : 1;
12208 uint64_t pd_bank1_ram : 1;
12209 uint64_t pd_bank0_ram : 1;
12210 uint64_t nxt_link_ptr_ram : 1;
12211 uint64_t iobp1_uid_fifo_ram : 1;
12212 uint64_t state_mem3 : 1;
12213 uint64_t reserved_19_20 : 2;
12214 uint64_t state_mem0 : 1;
12215 uint64_t iobp1_fifo_ram : 1;
12216 uint64_t iobp0_fifo_ram : 1;
12217 uint64_t pdm_pse_buf_ram : 1;
12218 uint64_t add_work_fifo : 1;
12219 uint64_t reserved_26_63 : 38;
12220 #endif
12221 } s;
12222 struct cvmx_pko_peb_bist_status_cn73xx {
12223 #ifdef __BIG_ENDIAN_BITFIELD
12224 uint64_t reserved_26_63 : 38;
12225 uint64_t add_work_fifo : 1;
12226 uint64_t pdm_pse_buf_ram : 1;
12227 uint64_t iobp0_fifo_ram : 1;
12228 uint64_t iobp1_fifo_ram : 1;
12229 uint64_t state_mem0 : 1;
12230 uint64_t reserved_19_20 : 2;
12231 uint64_t state_mem3 : 1;
12232 uint64_t iobp1_uid_fifo_ram : 1;
12233 uint64_t nxt_link_ptr_ram : 1;
12234 uint64_t pd_bank0_ram : 1;
12235 uint64_t reserved_13_14 : 2;
12236 uint64_t pd_bank3_ram : 1;
12237 uint64_t pd_var_bank_ram : 1;
12238 uint64_t pdm_resp_buf_ram : 1;
12239 uint64_t tx_fifo_pkt_ram : 1;
12240 uint64_t tx_fifo_hdr_ram : 1;
12241 uint64_t tx_fifo_crc_ram : 1;
12242 uint64_t ts_addwork_ram : 1;
12243 uint64_t send_mem_ts_fifo : 1;
12244 uint64_t send_mem_stdn_fifo : 1;
12245 uint64_t send_mem_fifo : 1;
12246 uint64_t pkt_mrk_ram : 1;
12247 uint64_t peb_st_inf_ram : 1;
12248 uint64_t reserved_0_0 : 1;
12249 #else
12250 uint64_t reserved_0_0 : 1;
12251 uint64_t peb_st_inf_ram : 1;
12252 uint64_t pkt_mrk_ram : 1;
12253 uint64_t send_mem_fifo : 1;
12254 uint64_t send_mem_stdn_fifo : 1;
12255 uint64_t send_mem_ts_fifo : 1;
12256 uint64_t ts_addwork_ram : 1;
12257 uint64_t tx_fifo_crc_ram : 1;
12258 uint64_t tx_fifo_hdr_ram : 1;
12259 uint64_t tx_fifo_pkt_ram : 1;
12260 uint64_t pdm_resp_buf_ram : 1;
12261 uint64_t pd_var_bank_ram : 1;
12262 uint64_t pd_bank3_ram : 1;
12263 uint64_t reserved_13_14 : 2;
12264 uint64_t pd_bank0_ram : 1;
12265 uint64_t nxt_link_ptr_ram : 1;
12266 uint64_t iobp1_uid_fifo_ram : 1;
12267 uint64_t state_mem3 : 1;
12268 uint64_t reserved_19_20 : 2;
12269 uint64_t state_mem0 : 1;
12270 uint64_t iobp1_fifo_ram : 1;
12271 uint64_t iobp0_fifo_ram : 1;
12272 uint64_t pdm_pse_buf_ram : 1;
12273 uint64_t add_work_fifo : 1;
12274 uint64_t reserved_26_63 : 38;
12275 #endif
12276 } cn73xx;
12277 struct cvmx_pko_peb_bist_status_cn73xx cn78xx;
12278 struct cvmx_pko_peb_bist_status_s cn78xxp1;
12279 struct cvmx_pko_peb_bist_status_cn73xx cnf75xx;
12280 };
12281 typedef union cvmx_pko_peb_bist_status cvmx_pko_peb_bist_status_t;
12282
12283
12284
12285
12286 union cvmx_pko_peb_ecc_ctl0 {
12287 uint64_t u64;
12288 struct cvmx_pko_peb_ecc_ctl0_s {
12289 #ifdef __BIG_ENDIAN_BITFIELD
12290 uint64_t iobp1_uid_fifo_ram_flip : 2;
12291 uint64_t iobp1_uid_fifo_ram_cdis : 1;
12292 uint64_t iobp0_fifo_ram_flip : 2;
12293 uint64_t iobp0_fifo_ram_cdis : 1;
12294 uint64_t iobp1_fifo_ram_flip : 2;
12295 uint64_t iobp1_fifo_ram_cdis : 1;
12296 uint64_t pdm_resp_buf_ram_flip : 2;
12297 uint64_t pdm_resp_buf_ram_cdis : 1;
12298 uint64_t pdm_pse_buf_ram_flip : 2;
12299 uint64_t pdm_pse_buf_ram_cdis : 1;
12300 uint64_t peb_sm_jmp_ram_flip : 2;
12301 uint64_t peb_sm_jmp_ram_cdis : 1;
12302 uint64_t peb_st_inf_ram_flip : 2;
12303 uint64_t peb_st_inf_ram_cdis : 1;
12304 uint64_t pd_bank3_ram_flip : 2;
12305 uint64_t pd_bank3_ram_cdis : 1;
12306 uint64_t pd_bank2_ram_flip : 2;
12307 uint64_t pd_bank2_ram_cdis : 1;
12308 uint64_t pd_bank1_ram_flip : 2;
12309 uint64_t pd_bank1_ram_cdis : 1;
12310 uint64_t pd_bank0_ram_flip : 2;
12311 uint64_t pd_bank0_ram_cdis : 1;
12312 uint64_t pd_var_bank_ram_flip : 2;
12313 uint64_t pd_var_bank_ram_cdis : 1;
12314 uint64_t tx_fifo_crc_ram_flip : 2;
12315 uint64_t tx_fifo_crc_ram_cdis : 1;
12316 uint64_t tx_fifo_hdr_ram_flip : 2;
12317 uint64_t tx_fifo_hdr_ram_cdis : 1;
12318 uint64_t tx_fifo_pkt_ram_flip : 2;
12319 uint64_t tx_fifo_pkt_ram_cdis : 1;
12320 uint64_t add_work_fifo_flip : 2;
12321 uint64_t add_work_fifo_cdis : 1;
12322 uint64_t send_mem_fifo_flip : 2;
12323 uint64_t send_mem_fifo_cdis : 1;
12324 uint64_t send_mem_stdn_fifo_flip : 2;
12325 uint64_t send_mem_stdn_fifo_cdis : 1;
12326 uint64_t send_mem_ts_fifo_flip : 2;
12327 uint64_t send_mem_ts_fifo_cdis : 1;
12328 uint64_t nxt_link_ptr_ram_flip : 2;
12329 uint64_t nxt_link_ptr_ram_cdis : 1;
12330 uint64_t pkt_mrk_ram_flip : 2;
12331 uint64_t pkt_mrk_ram_cdis : 1;
12332 uint64_t reserved_0_0 : 1;
12333 #else
12334 uint64_t reserved_0_0 : 1;
12335 uint64_t pkt_mrk_ram_cdis : 1;
12336 uint64_t pkt_mrk_ram_flip : 2;
12337 uint64_t nxt_link_ptr_ram_cdis : 1;
12338 uint64_t nxt_link_ptr_ram_flip : 2;
12339 uint64_t send_mem_ts_fifo_cdis : 1;
12340 uint64_t send_mem_ts_fifo_flip : 2;
12341 uint64_t send_mem_stdn_fifo_cdis : 1;
12342 uint64_t send_mem_stdn_fifo_flip : 2;
12343 uint64_t send_mem_fifo_cdis : 1;
12344 uint64_t send_mem_fifo_flip : 2;
12345 uint64_t add_work_fifo_cdis : 1;
12346 uint64_t add_work_fifo_flip : 2;
12347 uint64_t tx_fifo_pkt_ram_cdis : 1;
12348 uint64_t tx_fifo_pkt_ram_flip : 2;
12349 uint64_t tx_fifo_hdr_ram_cdis : 1;
12350 uint64_t tx_fifo_hdr_ram_flip : 2;
12351 uint64_t tx_fifo_crc_ram_cdis : 1;
12352 uint64_t tx_fifo_crc_ram_flip : 2;
12353 uint64_t pd_var_bank_ram_cdis : 1;
12354 uint64_t pd_var_bank_ram_flip : 2;
12355 uint64_t pd_bank0_ram_cdis : 1;
12356 uint64_t pd_bank0_ram_flip : 2;
12357 uint64_t pd_bank1_ram_cdis : 1;
12358 uint64_t pd_bank1_ram_flip : 2;
12359 uint64_t pd_bank2_ram_cdis : 1;
12360 uint64_t pd_bank2_ram_flip : 2;
12361 uint64_t pd_bank3_ram_cdis : 1;
12362 uint64_t pd_bank3_ram_flip : 2;
12363 uint64_t peb_st_inf_ram_cdis : 1;
12364 uint64_t peb_st_inf_ram_flip : 2;
12365 uint64_t peb_sm_jmp_ram_cdis : 1;
12366 uint64_t peb_sm_jmp_ram_flip : 2;
12367 uint64_t pdm_pse_buf_ram_cdis : 1;
12368 uint64_t pdm_pse_buf_ram_flip : 2;
12369 uint64_t pdm_resp_buf_ram_cdis : 1;
12370 uint64_t pdm_resp_buf_ram_flip : 2;
12371 uint64_t iobp1_fifo_ram_cdis : 1;
12372 uint64_t iobp1_fifo_ram_flip : 2;
12373 uint64_t iobp0_fifo_ram_cdis : 1;
12374 uint64_t iobp0_fifo_ram_flip : 2;
12375 uint64_t iobp1_uid_fifo_ram_cdis : 1;
12376 uint64_t iobp1_uid_fifo_ram_flip : 2;
12377 #endif
12378 } s;
12379 struct cvmx_pko_peb_ecc_ctl0_cn73xx {
12380 #ifdef __BIG_ENDIAN_BITFIELD
12381 uint64_t iobp1_uid_fifo_ram_flip : 2;
12382 uint64_t iobp1_uid_fifo_ram_cdis : 1;
12383 uint64_t iobp0_fifo_ram_flip : 2;
12384 uint64_t iobp0_fifo_ram_cdis : 1;
12385 uint64_t iobp1_fifo_ram_flip : 2;
12386 uint64_t iobp1_fifo_ram_cdis : 1;
12387 uint64_t pdm_resp_buf_ram_flip : 2;
12388 uint64_t pdm_resp_buf_ram_cdis : 1;
12389 uint64_t pdm_pse_buf_ram_flip : 2;
12390 uint64_t pdm_pse_buf_ram_cdis : 1;
12391 uint64_t reserved_46_48 : 3;
12392 uint64_t peb_st_inf_ram_flip : 2;
12393 uint64_t peb_st_inf_ram_cdis : 1;
12394 uint64_t pd_bank3_ram_flip : 2;
12395 uint64_t pd_bank3_ram_cdis : 1;
12396 uint64_t reserved_34_39 : 6;
12397 uint64_t pd_bank0_ram_flip : 2;
12398 uint64_t pd_bank0_ram_cdis : 1;
12399 uint64_t pd_var_bank_ram_flip : 2;
12400 uint64_t pd_var_bank_ram_cdis : 1;
12401 uint64_t tx_fifo_crc_ram_flip : 2;
12402 uint64_t tx_fifo_crc_ram_cdis : 1;
12403 uint64_t tx_fifo_hdr_ram_flip : 2;
12404 uint64_t tx_fifo_hdr_ram_cdis : 1;
12405 uint64_t tx_fifo_pkt_ram_flip : 2;
12406 uint64_t tx_fifo_pkt_ram_cdis : 1;
12407 uint64_t add_work_fifo_flip : 2;
12408 uint64_t add_work_fifo_cdis : 1;
12409 uint64_t send_mem_fifo_flip : 2;
12410 uint64_t send_mem_fifo_cdis : 1;
12411 uint64_t send_mem_stdn_fifo_flip : 2;
12412 uint64_t send_mem_stdn_fifo_cdis : 1;
12413 uint64_t send_mem_ts_fifo_flip : 2;
12414 uint64_t send_mem_ts_fifo_cdis : 1;
12415 uint64_t nxt_link_ptr_ram_flip : 2;
12416 uint64_t nxt_link_ptr_ram_cdis : 1;
12417 uint64_t pkt_mrk_ram_flip : 2;
12418 uint64_t pkt_mrk_ram_cdis : 1;
12419 uint64_t reserved_0_0 : 1;
12420 #else
12421 uint64_t reserved_0_0 : 1;
12422 uint64_t pkt_mrk_ram_cdis : 1;
12423 uint64_t pkt_mrk_ram_flip : 2;
12424 uint64_t nxt_link_ptr_ram_cdis : 1;
12425 uint64_t nxt_link_ptr_ram_flip : 2;
12426 uint64_t send_mem_ts_fifo_cdis : 1;
12427 uint64_t send_mem_ts_fifo_flip : 2;
12428 uint64_t send_mem_stdn_fifo_cdis : 1;
12429 uint64_t send_mem_stdn_fifo_flip : 2;
12430 uint64_t send_mem_fifo_cdis : 1;
12431 uint64_t send_mem_fifo_flip : 2;
12432 uint64_t add_work_fifo_cdis : 1;
12433 uint64_t add_work_fifo_flip : 2;
12434 uint64_t tx_fifo_pkt_ram_cdis : 1;
12435 uint64_t tx_fifo_pkt_ram_flip : 2;
12436 uint64_t tx_fifo_hdr_ram_cdis : 1;
12437 uint64_t tx_fifo_hdr_ram_flip : 2;
12438 uint64_t tx_fifo_crc_ram_cdis : 1;
12439 uint64_t tx_fifo_crc_ram_flip : 2;
12440 uint64_t pd_var_bank_ram_cdis : 1;
12441 uint64_t pd_var_bank_ram_flip : 2;
12442 uint64_t pd_bank0_ram_cdis : 1;
12443 uint64_t pd_bank0_ram_flip : 2;
12444 uint64_t reserved_34_39 : 6;
12445 uint64_t pd_bank3_ram_cdis : 1;
12446 uint64_t pd_bank3_ram_flip : 2;
12447 uint64_t peb_st_inf_ram_cdis : 1;
12448 uint64_t peb_st_inf_ram_flip : 2;
12449 uint64_t reserved_46_48 : 3;
12450 uint64_t pdm_pse_buf_ram_cdis : 1;
12451 uint64_t pdm_pse_buf_ram_flip : 2;
12452 uint64_t pdm_resp_buf_ram_cdis : 1;
12453 uint64_t pdm_resp_buf_ram_flip : 2;
12454 uint64_t iobp1_fifo_ram_cdis : 1;
12455 uint64_t iobp1_fifo_ram_flip : 2;
12456 uint64_t iobp0_fifo_ram_cdis : 1;
12457 uint64_t iobp0_fifo_ram_flip : 2;
12458 uint64_t iobp1_uid_fifo_ram_cdis : 1;
12459 uint64_t iobp1_uid_fifo_ram_flip : 2;
12460 #endif
12461 } cn73xx;
12462 struct cvmx_pko_peb_ecc_ctl0_cn73xx cn78xx;
12463 struct cvmx_pko_peb_ecc_ctl0_s cn78xxp1;
12464 struct cvmx_pko_peb_ecc_ctl0_cn73xx cnf75xx;
12465 };
12466 typedef union cvmx_pko_peb_ecc_ctl0 cvmx_pko_peb_ecc_ctl0_t;
12467
12468
12469
12470
12471 union cvmx_pko_peb_ecc_ctl1 {
12472 uint64_t u64;
12473 struct cvmx_pko_peb_ecc_ctl1_s {
12474 #ifdef __BIG_ENDIAN_BITFIELD
12475 uint64_t ts_addwork_ram_flip : 2;
12476 uint64_t ts_addwork_ram_cdis : 1;
12477 uint64_t state_mem0_flip : 2;
12478 uint64_t state_mem0_cdis : 1;
12479 uint64_t reserved_52_57 : 6;
12480 uint64_t state_mem3_flip : 2;
12481 uint64_t state_mem3_cdis : 1;
12482 uint64_t reserved_0_48 : 49;
12483 #else
12484 uint64_t reserved_0_48 : 49;
12485 uint64_t state_mem3_cdis : 1;
12486 uint64_t state_mem3_flip : 2;
12487 uint64_t reserved_52_57 : 6;
12488 uint64_t state_mem0_cdis : 1;
12489 uint64_t state_mem0_flip : 2;
12490 uint64_t ts_addwork_ram_cdis : 1;
12491 uint64_t ts_addwork_ram_flip : 2;
12492 #endif
12493 } s;
12494 struct cvmx_pko_peb_ecc_ctl1_s cn73xx;
12495 struct cvmx_pko_peb_ecc_ctl1_cn78xx {
12496 #ifdef __BIG_ENDIAN_BITFIELD
12497 uint64_t ts_addwork_ram_flip : 2;
12498 uint64_t ts_addwork_ram_cdis : 1;
12499 uint64_t reserved_0_60 : 61;
12500 #else
12501 uint64_t reserved_0_60 : 61;
12502 uint64_t ts_addwork_ram_cdis : 1;
12503 uint64_t ts_addwork_ram_flip : 2;
12504 #endif
12505 } cn78xx;
12506 struct cvmx_pko_peb_ecc_ctl1_cn78xx cn78xxp1;
12507 struct cvmx_pko_peb_ecc_ctl1_s cnf75xx;
12508 };
12509 typedef union cvmx_pko_peb_ecc_ctl1 cvmx_pko_peb_ecc_ctl1_t;
12510
12511
12512
12513
12514 union cvmx_pko_peb_ecc_dbe_sts0 {
12515 uint64_t u64;
12516 struct cvmx_pko_peb_ecc_dbe_sts0_s {
12517 #ifdef __BIG_ENDIAN_BITFIELD
12518 uint64_t iobp1_uid_fifo_ram_dbe : 1;
12519 uint64_t iobp0_fifo_ram_dbe : 1;
12520 uint64_t iobp1_fifo_ram_dbe : 1;
12521 uint64_t pdm_resp_buf_ram_dbe : 1;
12522 uint64_t pdm_pse_buf_ram_dbe : 1;
12523 uint64_t peb_sm_jmp_ram_dbe : 1;
12524 uint64_t peb_st_inf_ram_dbe : 1;
12525 uint64_t pd_bank3_ram_dbe : 1;
12526 uint64_t pd_bank2_ram_dbe : 1;
12527 uint64_t pd_bank1_ram_dbe : 1;
12528 uint64_t pd_bank0_ram_dbe : 1;
12529 uint64_t pd_var_bank_ram_dbe : 1;
12530 uint64_t tx_fifo_crc_ram_dbe : 1;
12531 uint64_t tx_fifo_hdr_ram_dbe : 1;
12532 uint64_t tx_fifo_pkt_ram_dbe : 1;
12533 uint64_t add_work_fifo_dbe : 1;
12534 uint64_t send_mem_fifo_dbe : 1;
12535 uint64_t send_mem_stdn_fifo_dbe : 1;
12536 uint64_t send_mem_ts_fifo_dbe : 1;
12537 uint64_t nxt_link_ptr_ram_dbe : 1;
12538 uint64_t pkt_mrk_ram_dbe : 1;
12539 uint64_t ts_addwork_ram_dbe : 1;
12540 uint64_t state_mem0_dbe : 1;
12541 uint64_t reserved_39_40 : 2;
12542 uint64_t state_mem3_dbe : 1;
12543 uint64_t reserved_0_37 : 38;
12544 #else
12545 uint64_t reserved_0_37 : 38;
12546 uint64_t state_mem3_dbe : 1;
12547 uint64_t reserved_39_40 : 2;
12548 uint64_t state_mem0_dbe : 1;
12549 uint64_t ts_addwork_ram_dbe : 1;
12550 uint64_t pkt_mrk_ram_dbe : 1;
12551 uint64_t nxt_link_ptr_ram_dbe : 1;
12552 uint64_t send_mem_ts_fifo_dbe : 1;
12553 uint64_t send_mem_stdn_fifo_dbe : 1;
12554 uint64_t send_mem_fifo_dbe : 1;
12555 uint64_t add_work_fifo_dbe : 1;
12556 uint64_t tx_fifo_pkt_ram_dbe : 1;
12557 uint64_t tx_fifo_hdr_ram_dbe : 1;
12558 uint64_t tx_fifo_crc_ram_dbe : 1;
12559 uint64_t pd_var_bank_ram_dbe : 1;
12560 uint64_t pd_bank0_ram_dbe : 1;
12561 uint64_t pd_bank1_ram_dbe : 1;
12562 uint64_t pd_bank2_ram_dbe : 1;
12563 uint64_t pd_bank3_ram_dbe : 1;
12564 uint64_t peb_st_inf_ram_dbe : 1;
12565 uint64_t peb_sm_jmp_ram_dbe : 1;
12566 uint64_t pdm_pse_buf_ram_dbe : 1;
12567 uint64_t pdm_resp_buf_ram_dbe : 1;
12568 uint64_t iobp1_fifo_ram_dbe : 1;
12569 uint64_t iobp0_fifo_ram_dbe : 1;
12570 uint64_t iobp1_uid_fifo_ram_dbe : 1;
12571 #endif
12572 } s;
12573 struct cvmx_pko_peb_ecc_dbe_sts0_cn73xx {
12574 #ifdef __BIG_ENDIAN_BITFIELD
12575 uint64_t iobp1_uid_fifo_ram_dbe : 1;
12576 uint64_t iobp0_fifo_ram_dbe : 1;
12577 uint64_t iobp1_fifo_ram_dbe : 1;
12578 uint64_t pdm_resp_buf_ram_dbe : 1;
12579 uint64_t pdm_pse_buf_ram_dbe : 1;
12580 uint64_t reserved_58_58 : 1;
12581 uint64_t peb_st_inf_ram_dbe : 1;
12582 uint64_t pd_bank3_ram_dbe : 1;
12583 uint64_t reserved_54_55 : 2;
12584 uint64_t pd_bank0_ram_dbe : 1;
12585 uint64_t pd_var_bank_ram_dbe : 1;
12586 uint64_t tx_fifo_crc_ram_dbe : 1;
12587 uint64_t tx_fifo_hdr_ram_dbe : 1;
12588 uint64_t tx_fifo_pkt_ram_dbe : 1;
12589 uint64_t add_work_fifo_dbe : 1;
12590 uint64_t send_mem_fifo_dbe : 1;
12591 uint64_t send_mem_stdn_fifo_dbe : 1;
12592 uint64_t send_mem_ts_fifo_dbe : 1;
12593 uint64_t nxt_link_ptr_ram_dbe : 1;
12594 uint64_t pkt_mrk_ram_dbe : 1;
12595 uint64_t ts_addwork_ram_dbe : 1;
12596 uint64_t state_mem0_dbe : 1;
12597 uint64_t reserved_39_40 : 2;
12598 uint64_t state_mem3_dbe : 1;
12599 uint64_t reserved_0_37 : 38;
12600 #else
12601 uint64_t reserved_0_37 : 38;
12602 uint64_t state_mem3_dbe : 1;
12603 uint64_t reserved_39_40 : 2;
12604 uint64_t state_mem0_dbe : 1;
12605 uint64_t ts_addwork_ram_dbe : 1;
12606 uint64_t pkt_mrk_ram_dbe : 1;
12607 uint64_t nxt_link_ptr_ram_dbe : 1;
12608 uint64_t send_mem_ts_fifo_dbe : 1;
12609 uint64_t send_mem_stdn_fifo_dbe : 1;
12610 uint64_t send_mem_fifo_dbe : 1;
12611 uint64_t add_work_fifo_dbe : 1;
12612 uint64_t tx_fifo_pkt_ram_dbe : 1;
12613 uint64_t tx_fifo_hdr_ram_dbe : 1;
12614 uint64_t tx_fifo_crc_ram_dbe : 1;
12615 uint64_t pd_var_bank_ram_dbe : 1;
12616 uint64_t pd_bank0_ram_dbe : 1;
12617 uint64_t reserved_54_55 : 2;
12618 uint64_t pd_bank3_ram_dbe : 1;
12619 uint64_t peb_st_inf_ram_dbe : 1;
12620 uint64_t reserved_58_58 : 1;
12621 uint64_t pdm_pse_buf_ram_dbe : 1;
12622 uint64_t pdm_resp_buf_ram_dbe : 1;
12623 uint64_t iobp1_fifo_ram_dbe : 1;
12624 uint64_t iobp0_fifo_ram_dbe : 1;
12625 uint64_t iobp1_uid_fifo_ram_dbe : 1;
12626 #endif
12627 } cn73xx;
12628 struct cvmx_pko_peb_ecc_dbe_sts0_cn78xx {
12629 #ifdef __BIG_ENDIAN_BITFIELD
12630 uint64_t iobp1_uid_fifo_ram_dbe : 1;
12631 uint64_t iobp0_fifo_ram_dbe : 1;
12632 uint64_t iobp1_fifo_ram_dbe : 1;
12633 uint64_t pdm_resp_buf_ram_dbe : 1;
12634 uint64_t pdm_pse_buf_ram_dbe : 1;
12635 uint64_t reserved_58_58 : 1;
12636 uint64_t peb_st_inf_ram_dbe : 1;
12637 uint64_t pd_bank3_ram_dbe : 1;
12638 uint64_t reserved_54_55 : 2;
12639 uint64_t pd_bank0_ram_dbe : 1;
12640 uint64_t pd_var_bank_ram_dbe : 1;
12641 uint64_t tx_fifo_crc_ram_dbe : 1;
12642 uint64_t tx_fifo_hdr_ram_dbe : 1;
12643 uint64_t tx_fifo_pkt_ram_dbe : 1;
12644 uint64_t add_work_fifo_dbe : 1;
12645 uint64_t send_mem_fifo_dbe : 1;
12646 uint64_t send_mem_stdn_fifo_dbe : 1;
12647 uint64_t send_mem_ts_fifo_dbe : 1;
12648 uint64_t nxt_link_ptr_ram_dbe : 1;
12649 uint64_t pkt_mrk_ram_dbe : 1;
12650 uint64_t ts_addwork_ram_dbe : 1;
12651 uint64_t reserved_0_41 : 42;
12652 #else
12653 uint64_t reserved_0_41 : 42;
12654 uint64_t ts_addwork_ram_dbe : 1;
12655 uint64_t pkt_mrk_ram_dbe : 1;
12656 uint64_t nxt_link_ptr_ram_dbe : 1;
12657 uint64_t send_mem_ts_fifo_dbe : 1;
12658 uint64_t send_mem_stdn_fifo_dbe : 1;
12659 uint64_t send_mem_fifo_dbe : 1;
12660 uint64_t add_work_fifo_dbe : 1;
12661 uint64_t tx_fifo_pkt_ram_dbe : 1;
12662 uint64_t tx_fifo_hdr_ram_dbe : 1;
12663 uint64_t tx_fifo_crc_ram_dbe : 1;
12664 uint64_t pd_var_bank_ram_dbe : 1;
12665 uint64_t pd_bank0_ram_dbe : 1;
12666 uint64_t reserved_54_55 : 2;
12667 uint64_t pd_bank3_ram_dbe : 1;
12668 uint64_t peb_st_inf_ram_dbe : 1;
12669 uint64_t reserved_58_58 : 1;
12670 uint64_t pdm_pse_buf_ram_dbe : 1;
12671 uint64_t pdm_resp_buf_ram_dbe : 1;
12672 uint64_t iobp1_fifo_ram_dbe : 1;
12673 uint64_t iobp0_fifo_ram_dbe : 1;
12674 uint64_t iobp1_uid_fifo_ram_dbe : 1;
12675 #endif
12676 } cn78xx;
12677 struct cvmx_pko_peb_ecc_dbe_sts0_cn78xxp1 {
12678 #ifdef __BIG_ENDIAN_BITFIELD
12679 uint64_t iobp1_uid_fifo_ram_dbe : 1;
12680 uint64_t iobp0_fifo_ram_dbe : 1;
12681 uint64_t iobp1_fifo_ram_dbe : 1;
12682 uint64_t pdm_resp_buf_ram_dbe : 1;
12683 uint64_t pdm_pse_buf_ram_dbe : 1;
12684 uint64_t peb_sm_jmp_ram_dbe : 1;
12685 uint64_t peb_st_inf_ram_dbe : 1;
12686 uint64_t pd_bank3_ram_dbe : 1;
12687 uint64_t pd_bank2_ram_dbe : 1;
12688 uint64_t pd_bank1_ram_dbe : 1;
12689 uint64_t pd_bank0_ram_dbe : 1;
12690 uint64_t pd_var_bank_ram_dbe : 1;
12691 uint64_t tx_fifo_crc_ram_dbe : 1;
12692 uint64_t tx_fifo_hdr_ram_dbe : 1;
12693 uint64_t tx_fifo_pkt_ram_dbe : 1;
12694 uint64_t add_work_fifo_dbe : 1;
12695 uint64_t send_mem_fifo_dbe : 1;
12696 uint64_t send_mem_stdn_fifo_dbe : 1;
12697 uint64_t send_mem_ts_fifo_dbe : 1;
12698 uint64_t nxt_link_ptr_ram_dbe : 1;
12699 uint64_t pkt_mrk_ram_dbe : 1;
12700 uint64_t ts_addwork_ram_dbe : 1;
12701 uint64_t reserved_0_41 : 42;
12702 #else
12703 uint64_t reserved_0_41 : 42;
12704 uint64_t ts_addwork_ram_dbe : 1;
12705 uint64_t pkt_mrk_ram_dbe : 1;
12706 uint64_t nxt_link_ptr_ram_dbe : 1;
12707 uint64_t send_mem_ts_fifo_dbe : 1;
12708 uint64_t send_mem_stdn_fifo_dbe : 1;
12709 uint64_t send_mem_fifo_dbe : 1;
12710 uint64_t add_work_fifo_dbe : 1;
12711 uint64_t tx_fifo_pkt_ram_dbe : 1;
12712 uint64_t tx_fifo_hdr_ram_dbe : 1;
12713 uint64_t tx_fifo_crc_ram_dbe : 1;
12714 uint64_t pd_var_bank_ram_dbe : 1;
12715 uint64_t pd_bank0_ram_dbe : 1;
12716 uint64_t pd_bank1_ram_dbe : 1;
12717 uint64_t pd_bank2_ram_dbe : 1;
12718 uint64_t pd_bank3_ram_dbe : 1;
12719 uint64_t peb_st_inf_ram_dbe : 1;
12720 uint64_t peb_sm_jmp_ram_dbe : 1;
12721 uint64_t pdm_pse_buf_ram_dbe : 1;
12722 uint64_t pdm_resp_buf_ram_dbe : 1;
12723 uint64_t iobp1_fifo_ram_dbe : 1;
12724 uint64_t iobp0_fifo_ram_dbe : 1;
12725 uint64_t iobp1_uid_fifo_ram_dbe : 1;
12726 #endif
12727 } cn78xxp1;
12728 struct cvmx_pko_peb_ecc_dbe_sts0_cn73xx cnf75xx;
12729 };
12730 typedef union cvmx_pko_peb_ecc_dbe_sts0 cvmx_pko_peb_ecc_dbe_sts0_t;
12731
12732
12733
12734
12735 union cvmx_pko_peb_ecc_dbe_sts_cmb0 {
12736 uint64_t u64;
12737 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s {
12738 #ifdef __BIG_ENDIAN_BITFIELD
12739 uint64_t peb_dbe_cmb0 : 1;
12740
12741
12742
12743 uint64_t reserved_0_62 : 63;
12744 #else
12745 uint64_t reserved_0_62 : 63;
12746 uint64_t peb_dbe_cmb0 : 1;
12747 #endif
12748 } s;
12749 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s cn73xx;
12750 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s cn78xx;
12751 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s cn78xxp1;
12752 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s cnf75xx;
12753 };
12754 typedef union cvmx_pko_peb_ecc_dbe_sts_cmb0 cvmx_pko_peb_ecc_dbe_sts_cmb0_t;
12755
12756
12757
12758
12759 union cvmx_pko_peb_ecc_sbe_sts0 {
12760 uint64_t u64;
12761 struct cvmx_pko_peb_ecc_sbe_sts0_s {
12762 #ifdef __BIG_ENDIAN_BITFIELD
12763 uint64_t iobp1_uid_fifo_ram_sbe : 1;
12764 uint64_t iobp0_fifo_ram_sbe : 1;
12765 uint64_t iobp1_fifo_ram_sbe : 1;
12766 uint64_t pdm_resp_buf_ram_sbe : 1;
12767 uint64_t pdm_pse_buf_ram_sbe : 1;
12768 uint64_t peb_sm_jmp_ram_sbe : 1;
12769 uint64_t peb_st_inf_ram_sbe : 1;
12770 uint64_t pd_bank3_ram_sbe : 1;
12771 uint64_t pd_bank2_ram_sbe : 1;
12772 uint64_t pd_bank1_ram_sbe : 1;
12773 uint64_t pd_bank0_ram_sbe : 1;
12774 uint64_t pd_var_bank_ram_sbe : 1;
12775 uint64_t tx_fifo_crc_ram_sbe : 1;
12776 uint64_t tx_fifo_hdr_ram_sbe : 1;
12777 uint64_t tx_fifo_pkt_ram_sbe : 1;
12778 uint64_t add_work_fifo_sbe : 1;
12779 uint64_t send_mem_fifo_sbe : 1;
12780 uint64_t send_mem_stdn_fifo_sbe : 1;
12781 uint64_t send_mem_ts_fifo_sbe : 1;
12782 uint64_t nxt_link_ptr_ram_sbe : 1;
12783 uint64_t pkt_mrk_ram_sbe : 1;
12784 uint64_t ts_addwork_ram_sbe : 1;
12785 uint64_t state_mem0_sbe : 1;
12786 uint64_t reserved_39_40 : 2;
12787 uint64_t state_mem3_sbe : 1;
12788 uint64_t reserved_0_37 : 38;
12789 #else
12790 uint64_t reserved_0_37 : 38;
12791 uint64_t state_mem3_sbe : 1;
12792 uint64_t reserved_39_40 : 2;
12793 uint64_t state_mem0_sbe : 1;
12794 uint64_t ts_addwork_ram_sbe : 1;
12795 uint64_t pkt_mrk_ram_sbe : 1;
12796 uint64_t nxt_link_ptr_ram_sbe : 1;
12797 uint64_t send_mem_ts_fifo_sbe : 1;
12798 uint64_t send_mem_stdn_fifo_sbe : 1;
12799 uint64_t send_mem_fifo_sbe : 1;
12800 uint64_t add_work_fifo_sbe : 1;
12801 uint64_t tx_fifo_pkt_ram_sbe : 1;
12802 uint64_t tx_fifo_hdr_ram_sbe : 1;
12803 uint64_t tx_fifo_crc_ram_sbe : 1;
12804 uint64_t pd_var_bank_ram_sbe : 1;
12805 uint64_t pd_bank0_ram_sbe : 1;
12806 uint64_t pd_bank1_ram_sbe : 1;
12807 uint64_t pd_bank2_ram_sbe : 1;
12808 uint64_t pd_bank3_ram_sbe : 1;
12809 uint64_t peb_st_inf_ram_sbe : 1;
12810 uint64_t peb_sm_jmp_ram_sbe : 1;
12811 uint64_t pdm_pse_buf_ram_sbe : 1;
12812 uint64_t pdm_resp_buf_ram_sbe : 1;
12813 uint64_t iobp1_fifo_ram_sbe : 1;
12814 uint64_t iobp0_fifo_ram_sbe : 1;
12815 uint64_t iobp1_uid_fifo_ram_sbe : 1;
12816 #endif
12817 } s;
12818 struct cvmx_pko_peb_ecc_sbe_sts0_cn73xx {
12819 #ifdef __BIG_ENDIAN_BITFIELD
12820 uint64_t iobp1_uid_fifo_ram_sbe : 1;
12821 uint64_t iobp0_fifo_ram_sbe : 1;
12822 uint64_t iobp1_fifo_ram_sbe : 1;
12823 uint64_t pdm_resp_buf_ram_sbe : 1;
12824 uint64_t pdm_pse_buf_ram_sbe : 1;
12825 uint64_t reserved_58_58 : 1;
12826 uint64_t peb_st_inf_ram_sbe : 1;
12827 uint64_t pd_bank3_ram_sbe : 1;
12828 uint64_t reserved_54_55 : 2;
12829 uint64_t pd_bank0_ram_sbe : 1;
12830 uint64_t pd_var_bank_ram_sbe : 1;
12831 uint64_t tx_fifo_crc_ram_sbe : 1;
12832 uint64_t tx_fifo_hdr_ram_sbe : 1;
12833 uint64_t tx_fifo_pkt_ram_sbe : 1;
12834 uint64_t add_work_fifo_sbe : 1;
12835 uint64_t send_mem_fifo_sbe : 1;
12836 uint64_t send_mem_stdn_fifo_sbe : 1;
12837 uint64_t send_mem_ts_fifo_sbe : 1;
12838 uint64_t nxt_link_ptr_ram_sbe : 1;
12839 uint64_t pkt_mrk_ram_sbe : 1;
12840 uint64_t ts_addwork_ram_sbe : 1;
12841 uint64_t state_mem0_sbe : 1;
12842 uint64_t reserved_39_40 : 2;
12843 uint64_t state_mem3_sbe : 1;
12844 uint64_t reserved_0_37 : 38;
12845 #else
12846 uint64_t reserved_0_37 : 38;
12847 uint64_t state_mem3_sbe : 1;
12848 uint64_t reserved_39_40 : 2;
12849 uint64_t state_mem0_sbe : 1;
12850 uint64_t ts_addwork_ram_sbe : 1;
12851 uint64_t pkt_mrk_ram_sbe : 1;
12852 uint64_t nxt_link_ptr_ram_sbe : 1;
12853 uint64_t send_mem_ts_fifo_sbe : 1;
12854 uint64_t send_mem_stdn_fifo_sbe : 1;
12855 uint64_t send_mem_fifo_sbe : 1;
12856 uint64_t add_work_fifo_sbe : 1;
12857 uint64_t tx_fifo_pkt_ram_sbe : 1;
12858 uint64_t tx_fifo_hdr_ram_sbe : 1;
12859 uint64_t tx_fifo_crc_ram_sbe : 1;
12860 uint64_t pd_var_bank_ram_sbe : 1;
12861 uint64_t pd_bank0_ram_sbe : 1;
12862 uint64_t reserved_54_55 : 2;
12863 uint64_t pd_bank3_ram_sbe : 1;
12864 uint64_t peb_st_inf_ram_sbe : 1;
12865 uint64_t reserved_58_58 : 1;
12866 uint64_t pdm_pse_buf_ram_sbe : 1;
12867 uint64_t pdm_resp_buf_ram_sbe : 1;
12868 uint64_t iobp1_fifo_ram_sbe : 1;
12869 uint64_t iobp0_fifo_ram_sbe : 1;
12870 uint64_t iobp1_uid_fifo_ram_sbe : 1;
12871 #endif
12872 } cn73xx;
12873 struct cvmx_pko_peb_ecc_sbe_sts0_cn78xx {
12874 #ifdef __BIG_ENDIAN_BITFIELD
12875 uint64_t iobp1_uid_fifo_ram_sbe : 1;
12876 uint64_t iobp0_fifo_ram_sbe : 1;
12877 uint64_t iobp1_fifo_ram_sbe : 1;
12878 uint64_t pdm_resp_buf_ram_sbe : 1;
12879 uint64_t pdm_pse_buf_ram_sbe : 1;
12880 uint64_t reserved_58_58 : 1;
12881 uint64_t peb_st_inf_ram_sbe : 1;
12882 uint64_t pd_bank3_ram_sbe : 1;
12883 uint64_t reserved_54_55 : 2;
12884 uint64_t pd_bank0_ram_sbe : 1;
12885 uint64_t pd_var_bank_ram_sbe : 1;
12886 uint64_t tx_fifo_crc_ram_sbe : 1;
12887 uint64_t tx_fifo_hdr_ram_sbe : 1;
12888 uint64_t tx_fifo_pkt_ram_sbe : 1;
12889 uint64_t add_work_fifo_sbe : 1;
12890 uint64_t send_mem_fifo_sbe : 1;
12891 uint64_t send_mem_stdn_fifo_sbe : 1;
12892 uint64_t send_mem_ts_fifo_sbe : 1;
12893 uint64_t nxt_link_ptr_ram_sbe : 1;
12894 uint64_t pkt_mrk_ram_sbe : 1;
12895 uint64_t ts_addwork_ram_sbe : 1;
12896 uint64_t reserved_0_41 : 42;
12897 #else
12898 uint64_t reserved_0_41 : 42;
12899 uint64_t ts_addwork_ram_sbe : 1;
12900 uint64_t pkt_mrk_ram_sbe : 1;
12901 uint64_t nxt_link_ptr_ram_sbe : 1;
12902 uint64_t send_mem_ts_fifo_sbe : 1;
12903 uint64_t send_mem_stdn_fifo_sbe : 1;
12904 uint64_t send_mem_fifo_sbe : 1;
12905 uint64_t add_work_fifo_sbe : 1;
12906 uint64_t tx_fifo_pkt_ram_sbe : 1;
12907 uint64_t tx_fifo_hdr_ram_sbe : 1;
12908 uint64_t tx_fifo_crc_ram_sbe : 1;
12909 uint64_t pd_var_bank_ram_sbe : 1;
12910 uint64_t pd_bank0_ram_sbe : 1;
12911 uint64_t reserved_54_55 : 2;
12912 uint64_t pd_bank3_ram_sbe : 1;
12913 uint64_t peb_st_inf_ram_sbe : 1;
12914 uint64_t reserved_58_58 : 1;
12915 uint64_t pdm_pse_buf_ram_sbe : 1;
12916 uint64_t pdm_resp_buf_ram_sbe : 1;
12917 uint64_t iobp1_fifo_ram_sbe : 1;
12918 uint64_t iobp0_fifo_ram_sbe : 1;
12919 uint64_t iobp1_uid_fifo_ram_sbe : 1;
12920 #endif
12921 } cn78xx;
12922 struct cvmx_pko_peb_ecc_sbe_sts0_cn78xxp1 {
12923 #ifdef __BIG_ENDIAN_BITFIELD
12924 uint64_t iobp1_uid_fifo_ram_sbe : 1;
12925 uint64_t iobp0_fifo_ram_sbe : 1;
12926 uint64_t iobp1_fifo_ram_sbe : 1;
12927 uint64_t pdm_resp_buf_ram_sbe : 1;
12928 uint64_t pdm_pse_buf_ram_sbe : 1;
12929 uint64_t peb_sm_jmp_ram_sbe : 1;
12930 uint64_t peb_st_inf_ram_sbe : 1;
12931 uint64_t pd_bank3_ram_sbe : 1;
12932 uint64_t pd_bank2_ram_sbe : 1;
12933 uint64_t pd_bank1_ram_sbe : 1;
12934 uint64_t pd_bank0_ram_sbe : 1;
12935 uint64_t pd_var_bank_ram_sbe : 1;
12936 uint64_t tx_fifo_crc_ram_sbe : 1;
12937 uint64_t tx_fifo_hdr_ram_sbe : 1;
12938 uint64_t tx_fifo_pkt_ram_sbe : 1;
12939 uint64_t add_work_fifo_sbe : 1;
12940 uint64_t send_mem_fifo_sbe : 1;
12941 uint64_t send_mem_stdn_fifo_sbe : 1;
12942 uint64_t send_mem_ts_fifo_sbe : 1;
12943 uint64_t nxt_link_ptr_ram_sbe : 1;
12944 uint64_t pkt_mrk_ram_sbe : 1;
12945 uint64_t ts_addwork_ram_sbe : 1;
12946 uint64_t reserved_0_41 : 42;
12947 #else
12948 uint64_t reserved_0_41 : 42;
12949 uint64_t ts_addwork_ram_sbe : 1;
12950 uint64_t pkt_mrk_ram_sbe : 1;
12951 uint64_t nxt_link_ptr_ram_sbe : 1;
12952 uint64_t send_mem_ts_fifo_sbe : 1;
12953 uint64_t send_mem_stdn_fifo_sbe : 1;
12954 uint64_t send_mem_fifo_sbe : 1;
12955 uint64_t add_work_fifo_sbe : 1;
12956 uint64_t tx_fifo_pkt_ram_sbe : 1;
12957 uint64_t tx_fifo_hdr_ram_sbe : 1;
12958 uint64_t tx_fifo_crc_ram_sbe : 1;
12959 uint64_t pd_var_bank_ram_sbe : 1;
12960 uint64_t pd_bank0_ram_sbe : 1;
12961 uint64_t pd_bank1_ram_sbe : 1;
12962 uint64_t pd_bank2_ram_sbe : 1;
12963 uint64_t pd_bank3_ram_sbe : 1;
12964 uint64_t peb_st_inf_ram_sbe : 1;
12965 uint64_t peb_sm_jmp_ram_sbe : 1;
12966 uint64_t pdm_pse_buf_ram_sbe : 1;
12967 uint64_t pdm_resp_buf_ram_sbe : 1;
12968 uint64_t iobp1_fifo_ram_sbe : 1;
12969 uint64_t iobp0_fifo_ram_sbe : 1;
12970 uint64_t iobp1_uid_fifo_ram_sbe : 1;
12971 #endif
12972 } cn78xxp1;
12973 struct cvmx_pko_peb_ecc_sbe_sts0_cn73xx cnf75xx;
12974 };
12975 typedef union cvmx_pko_peb_ecc_sbe_sts0 cvmx_pko_peb_ecc_sbe_sts0_t;
12976
12977
12978
12979
12980 union cvmx_pko_peb_ecc_sbe_sts_cmb0 {
12981 uint64_t u64;
12982 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s {
12983 #ifdef __BIG_ENDIAN_BITFIELD
12984 uint64_t peb_sbe_cmb0 : 1;
12985
12986
12987
12988 uint64_t reserved_0_62 : 63;
12989 #else
12990 uint64_t reserved_0_62 : 63;
12991 uint64_t peb_sbe_cmb0 : 1;
12992 #endif
12993 } s;
12994 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s cn73xx;
12995 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s cn78xx;
12996 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s cn78xxp1;
12997 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s cnf75xx;
12998 };
12999 typedef union cvmx_pko_peb_ecc_sbe_sts_cmb0 cvmx_pko_peb_ecc_sbe_sts_cmb0_t;
13000
13001
13002
13003
13004 union cvmx_pko_peb_eco {
13005 uint64_t u64;
13006 struct cvmx_pko_peb_eco_s {
13007 #ifdef __BIG_ENDIAN_BITFIELD
13008 uint64_t reserved_32_63 : 32;
13009 uint64_t eco_rw : 32;
13010 #else
13011 uint64_t eco_rw : 32;
13012 uint64_t reserved_32_63 : 32;
13013 #endif
13014 } s;
13015 struct cvmx_pko_peb_eco_s cn73xx;
13016 struct cvmx_pko_peb_eco_s cn78xx;
13017 struct cvmx_pko_peb_eco_s cnf75xx;
13018 };
13019 typedef union cvmx_pko_peb_eco cvmx_pko_peb_eco_t;
13020
13021
13022
13023
13024 union cvmx_pko_peb_err_int {
13025 uint64_t u64;
13026 struct cvmx_pko_peb_err_int_s {
13027 #ifdef __BIG_ENDIAN_BITFIELD
13028 uint64_t reserved_10_63 : 54;
13029 uint64_t peb_macx_cfg_wr_err : 1;
13030
13031 uint64_t peb_max_link_err : 1;
13032
13033 uint64_t peb_subd_size_err : 1;
13034
13035 uint64_t peb_subd_addr_err : 1;
13036
13037 uint64_t peb_trunc_err : 1;
13038 uint64_t peb_pad_err : 1;
13039
13040 uint64_t peb_pse_fifo_err : 1;
13041
13042 uint64_t peb_fcs_sop_err : 1;
13043
13044 uint64_t peb_jump_def_err : 1;
13045
13046 uint64_t peb_ext_hdr_def_err : 1;
13047
13048 #else
13049 uint64_t peb_ext_hdr_def_err : 1;
13050 uint64_t peb_jump_def_err : 1;
13051 uint64_t peb_fcs_sop_err : 1;
13052 uint64_t peb_pse_fifo_err : 1;
13053 uint64_t peb_pad_err : 1;
13054 uint64_t peb_trunc_err : 1;
13055 uint64_t peb_subd_addr_err : 1;
13056 uint64_t peb_subd_size_err : 1;
13057 uint64_t peb_max_link_err : 1;
13058 uint64_t peb_macx_cfg_wr_err : 1;
13059 uint64_t reserved_10_63 : 54;
13060 #endif
13061 } s;
13062 struct cvmx_pko_peb_err_int_s cn73xx;
13063 struct cvmx_pko_peb_err_int_s cn78xx;
13064 struct cvmx_pko_peb_err_int_s cn78xxp1;
13065 struct cvmx_pko_peb_err_int_s cnf75xx;
13066 };
13067 typedef union cvmx_pko_peb_err_int cvmx_pko_peb_err_int_t;
13068
13069
13070
13071
13072 union cvmx_pko_peb_ext_hdr_def_err_info {
13073 uint64_t u64;
13074 struct cvmx_pko_peb_ext_hdr_def_err_info_s {
13075 #ifdef __BIG_ENDIAN_BITFIELD
13076 uint64_t reserved_20_63 : 44;
13077 uint64_t val : 1;
13078 uint64_t fifo : 7;
13079 uint64_t chan : 12;
13080 #else
13081 uint64_t chan : 12;
13082 uint64_t fifo : 7;
13083 uint64_t val : 1;
13084 uint64_t reserved_20_63 : 44;
13085 #endif
13086 } s;
13087 struct cvmx_pko_peb_ext_hdr_def_err_info_s cn73xx;
13088 struct cvmx_pko_peb_ext_hdr_def_err_info_s cn78xx;
13089 struct cvmx_pko_peb_ext_hdr_def_err_info_s cn78xxp1;
13090 struct cvmx_pko_peb_ext_hdr_def_err_info_s cnf75xx;
13091 };
13092 typedef union cvmx_pko_peb_ext_hdr_def_err_info cvmx_pko_peb_ext_hdr_def_err_info_t;
13093
13094
13095
13096
13097 union cvmx_pko_peb_fcs_sop_err_info {
13098 uint64_t u64;
13099 struct cvmx_pko_peb_fcs_sop_err_info_s {
13100 #ifdef __BIG_ENDIAN_BITFIELD
13101 uint64_t reserved_20_63 : 44;
13102 uint64_t val : 1;
13103 uint64_t fifo : 7;
13104 uint64_t chan : 12;
13105 #else
13106 uint64_t chan : 12;
13107 uint64_t fifo : 7;
13108 uint64_t val : 1;
13109 uint64_t reserved_20_63 : 44;
13110 #endif
13111 } s;
13112 struct cvmx_pko_peb_fcs_sop_err_info_s cn73xx;
13113 struct cvmx_pko_peb_fcs_sop_err_info_s cn78xx;
13114 struct cvmx_pko_peb_fcs_sop_err_info_s cn78xxp1;
13115 struct cvmx_pko_peb_fcs_sop_err_info_s cnf75xx;
13116 };
13117 typedef union cvmx_pko_peb_fcs_sop_err_info cvmx_pko_peb_fcs_sop_err_info_t;
13118
13119
13120
13121
13122 union cvmx_pko_peb_jump_def_err_info {
13123 uint64_t u64;
13124 struct cvmx_pko_peb_jump_def_err_info_s {
13125 #ifdef __BIG_ENDIAN_BITFIELD
13126 uint64_t reserved_20_63 : 44;
13127 uint64_t val : 1;
13128 uint64_t fifo : 7;
13129 uint64_t chan : 12;
13130 #else
13131 uint64_t chan : 12;
13132 uint64_t fifo : 7;
13133 uint64_t val : 1;
13134 uint64_t reserved_20_63 : 44;
13135 #endif
13136 } s;
13137 struct cvmx_pko_peb_jump_def_err_info_s cn73xx;
13138 struct cvmx_pko_peb_jump_def_err_info_s cn78xx;
13139 struct cvmx_pko_peb_jump_def_err_info_s cn78xxp1;
13140 struct cvmx_pko_peb_jump_def_err_info_s cnf75xx;
13141 };
13142 typedef union cvmx_pko_peb_jump_def_err_info cvmx_pko_peb_jump_def_err_info_t;
13143
13144
13145
13146
13147 union cvmx_pko_peb_macx_cfg_wr_err_info {
13148 uint64_t u64;
13149 struct cvmx_pko_peb_macx_cfg_wr_err_info_s {
13150 #ifdef __BIG_ENDIAN_BITFIELD
13151 uint64_t reserved_8_63 : 56;
13152 uint64_t val : 1;
13153 uint64_t mac : 7;
13154 #else
13155 uint64_t mac : 7;
13156 uint64_t val : 1;
13157 uint64_t reserved_8_63 : 56;
13158 #endif
13159 } s;
13160 struct cvmx_pko_peb_macx_cfg_wr_err_info_s cn73xx;
13161 struct cvmx_pko_peb_macx_cfg_wr_err_info_s cn78xx;
13162 struct cvmx_pko_peb_macx_cfg_wr_err_info_s cn78xxp1;
13163 struct cvmx_pko_peb_macx_cfg_wr_err_info_s cnf75xx;
13164 };
13165 typedef union cvmx_pko_peb_macx_cfg_wr_err_info cvmx_pko_peb_macx_cfg_wr_err_info_t;
13166
13167
13168
13169
13170 union cvmx_pko_peb_max_link_err_info {
13171 uint64_t u64;
13172 struct cvmx_pko_peb_max_link_err_info_s {
13173 #ifdef __BIG_ENDIAN_BITFIELD
13174 uint64_t reserved_20_63 : 44;
13175 uint64_t val : 1;
13176 uint64_t fifo : 7;
13177 uint64_t chan : 12;
13178 #else
13179 uint64_t chan : 12;
13180 uint64_t fifo : 7;
13181 uint64_t val : 1;
13182 uint64_t reserved_20_63 : 44;
13183 #endif
13184 } s;
13185 struct cvmx_pko_peb_max_link_err_info_s cn73xx;
13186 struct cvmx_pko_peb_max_link_err_info_s cn78xx;
13187 struct cvmx_pko_peb_max_link_err_info_s cn78xxp1;
13188 struct cvmx_pko_peb_max_link_err_info_s cnf75xx;
13189 };
13190 typedef union cvmx_pko_peb_max_link_err_info cvmx_pko_peb_max_link_err_info_t;
13191
13192
13193
13194
13195 union cvmx_pko_peb_ncb_cfg {
13196 uint64_t u64;
13197 struct cvmx_pko_peb_ncb_cfg_s {
13198 #ifdef __BIG_ENDIAN_BITFIELD
13199 uint64_t reserved_1_63 : 63;
13200 uint64_t rstp : 1;
13201 #else
13202 uint64_t rstp : 1;
13203 uint64_t reserved_1_63 : 63;
13204 #endif
13205 } s;
13206 struct cvmx_pko_peb_ncb_cfg_s cn73xx;
13207 struct cvmx_pko_peb_ncb_cfg_s cn78xx;
13208 struct cvmx_pko_peb_ncb_cfg_s cn78xxp1;
13209 struct cvmx_pko_peb_ncb_cfg_s cnf75xx;
13210 };
13211 typedef union cvmx_pko_peb_ncb_cfg cvmx_pko_peb_ncb_cfg_t;
13212
13213
13214
13215
13216 union cvmx_pko_peb_pad_err_info {
13217 uint64_t u64;
13218 struct cvmx_pko_peb_pad_err_info_s {
13219 #ifdef __BIG_ENDIAN_BITFIELD
13220 uint64_t reserved_20_63 : 44;
13221 uint64_t val : 1;
13222 uint64_t fifo : 7;
13223 uint64_t chan : 12;
13224 #else
13225 uint64_t chan : 12;
13226 uint64_t fifo : 7;
13227 uint64_t val : 1;
13228 uint64_t reserved_20_63 : 44;
13229 #endif
13230 } s;
13231 struct cvmx_pko_peb_pad_err_info_s cn73xx;
13232 struct cvmx_pko_peb_pad_err_info_s cn78xx;
13233 struct cvmx_pko_peb_pad_err_info_s cn78xxp1;
13234 struct cvmx_pko_peb_pad_err_info_s cnf75xx;
13235 };
13236 typedef union cvmx_pko_peb_pad_err_info cvmx_pko_peb_pad_err_info_t;
13237
13238
13239
13240
13241 union cvmx_pko_peb_pse_fifo_err_info {
13242 uint64_t u64;
13243 struct cvmx_pko_peb_pse_fifo_err_info_s {
13244 #ifdef __BIG_ENDIAN_BITFIELD
13245 uint64_t reserved_25_63 : 39;
13246 uint64_t link : 5;
13247 uint64_t val : 1;
13248 uint64_t fifo : 7;
13249 uint64_t chan : 12;
13250 #else
13251 uint64_t chan : 12;
13252 uint64_t fifo : 7;
13253 uint64_t val : 1;
13254 uint64_t link : 5;
13255 uint64_t reserved_25_63 : 39;
13256 #endif
13257 } s;
13258 struct cvmx_pko_peb_pse_fifo_err_info_cn73xx {
13259 #ifdef __BIG_ENDIAN_BITFIELD
13260 uint64_t reserved_20_63 : 44;
13261 uint64_t val : 1;
13262 uint64_t fifo : 7;
13263 uint64_t chan : 12;
13264 #else
13265 uint64_t chan : 12;
13266 uint64_t fifo : 7;
13267 uint64_t val : 1;
13268 uint64_t reserved_20_63 : 44;
13269 #endif
13270 } cn73xx;
13271 struct cvmx_pko_peb_pse_fifo_err_info_s cn78xx;
13272 struct cvmx_pko_peb_pse_fifo_err_info_cn73xx cn78xxp1;
13273 struct cvmx_pko_peb_pse_fifo_err_info_s cnf75xx;
13274 };
13275 typedef union cvmx_pko_peb_pse_fifo_err_info cvmx_pko_peb_pse_fifo_err_info_t;
13276
13277
13278
13279
13280 union cvmx_pko_peb_subd_addr_err_info {
13281 uint64_t u64;
13282 struct cvmx_pko_peb_subd_addr_err_info_s {
13283 #ifdef __BIG_ENDIAN_BITFIELD
13284 uint64_t reserved_20_63 : 44;
13285 uint64_t val : 1;
13286 uint64_t fifo : 7;
13287 uint64_t chan : 12;
13288 #else
13289 uint64_t chan : 12;
13290 uint64_t fifo : 7;
13291 uint64_t val : 1;
13292 uint64_t reserved_20_63 : 44;
13293 #endif
13294 } s;
13295 struct cvmx_pko_peb_subd_addr_err_info_s cn73xx;
13296 struct cvmx_pko_peb_subd_addr_err_info_s cn78xx;
13297 struct cvmx_pko_peb_subd_addr_err_info_s cn78xxp1;
13298 struct cvmx_pko_peb_subd_addr_err_info_s cnf75xx;
13299 };
13300 typedef union cvmx_pko_peb_subd_addr_err_info cvmx_pko_peb_subd_addr_err_info_t;
13301
13302
13303
13304
13305 union cvmx_pko_peb_subd_size_err_info {
13306 uint64_t u64;
13307 struct cvmx_pko_peb_subd_size_err_info_s {
13308 #ifdef __BIG_ENDIAN_BITFIELD
13309 uint64_t reserved_20_63 : 44;
13310 uint64_t val : 1;
13311 uint64_t fifo : 7;
13312 uint64_t chan : 12;
13313 #else
13314 uint64_t chan : 12;
13315 uint64_t fifo : 7;
13316 uint64_t val : 1;
13317 uint64_t reserved_20_63 : 44;
13318 #endif
13319 } s;
13320 struct cvmx_pko_peb_subd_size_err_info_s cn73xx;
13321 struct cvmx_pko_peb_subd_size_err_info_s cn78xx;
13322 struct cvmx_pko_peb_subd_size_err_info_s cn78xxp1;
13323 struct cvmx_pko_peb_subd_size_err_info_s cnf75xx;
13324 };
13325 typedef union cvmx_pko_peb_subd_size_err_info cvmx_pko_peb_subd_size_err_info_t;
13326
13327
13328
13329
13330 union cvmx_pko_peb_trunc_err_info {
13331 uint64_t u64;
13332 struct cvmx_pko_peb_trunc_err_info_s {
13333 #ifdef __BIG_ENDIAN_BITFIELD
13334 uint64_t reserved_20_63 : 44;
13335 uint64_t val : 1;
13336 uint64_t fifo : 7;
13337 uint64_t chan : 12;
13338 #else
13339 uint64_t chan : 12;
13340 uint64_t fifo : 7;
13341 uint64_t val : 1;
13342 uint64_t reserved_20_63 : 44;
13343 #endif
13344 } s;
13345 struct cvmx_pko_peb_trunc_err_info_s cn73xx;
13346 struct cvmx_pko_peb_trunc_err_info_s cn78xx;
13347 struct cvmx_pko_peb_trunc_err_info_s cn78xxp1;
13348 struct cvmx_pko_peb_trunc_err_info_s cnf75xx;
13349 };
13350 typedef union cvmx_pko_peb_trunc_err_info cvmx_pko_peb_trunc_err_info_t;
13351
13352
13353
13354
13355 union cvmx_pko_peb_tso_cfg {
13356 uint64_t u64;
13357 struct cvmx_pko_peb_tso_cfg_s {
13358 #ifdef __BIG_ENDIAN_BITFIELD
13359 uint64_t reserved_44_63 : 20;
13360 uint64_t fsf : 12;
13361
13362
13363 uint64_t reserved_28_31 : 4;
13364 uint64_t msf : 12;
13365
13366
13367 uint64_t reserved_12_15 : 4;
13368 uint64_t lsf : 12;
13369
13370
13371 #else
13372 uint64_t lsf : 12;
13373 uint64_t reserved_12_15 : 4;
13374 uint64_t msf : 12;
13375 uint64_t reserved_28_31 : 4;
13376 uint64_t fsf : 12;
13377 uint64_t reserved_44_63 : 20;
13378 #endif
13379 } s;
13380 struct cvmx_pko_peb_tso_cfg_s cn73xx;
13381 struct cvmx_pko_peb_tso_cfg_s cn78xx;
13382 struct cvmx_pko_peb_tso_cfg_s cn78xxp1;
13383 struct cvmx_pko_peb_tso_cfg_s cnf75xx;
13384 };
13385 typedef union cvmx_pko_peb_tso_cfg cvmx_pko_peb_tso_cfg_t;
13386
13387
13388
13389
13390 union cvmx_pko_pq_csr_bus_debug {
13391 uint64_t u64;
13392 struct cvmx_pko_pq_csr_bus_debug_s {
13393 #ifdef __BIG_ENDIAN_BITFIELD
13394 uint64_t csr_bus_debug : 64;
13395 #else
13396 uint64_t csr_bus_debug : 64;
13397 #endif
13398 } s;
13399 struct cvmx_pko_pq_csr_bus_debug_s cn73xx;
13400 struct cvmx_pko_pq_csr_bus_debug_s cn78xx;
13401 struct cvmx_pko_pq_csr_bus_debug_s cn78xxp1;
13402 struct cvmx_pko_pq_csr_bus_debug_s cnf75xx;
13403 };
13404 typedef union cvmx_pko_pq_csr_bus_debug cvmx_pko_pq_csr_bus_debug_t;
13405
13406
13407
13408
13409 union cvmx_pko_pq_debug_green {
13410 uint64_t u64;
13411 struct cvmx_pko_pq_debug_green_s {
13412 #ifdef __BIG_ENDIAN_BITFIELD
13413 uint64_t g_valid : 32;
13414 uint64_t cred_ok_n : 32;
13415 #else
13416 uint64_t cred_ok_n : 32;
13417 uint64_t g_valid : 32;
13418 #endif
13419 } s;
13420 struct cvmx_pko_pq_debug_green_s cn73xx;
13421 struct cvmx_pko_pq_debug_green_s cn78xx;
13422 struct cvmx_pko_pq_debug_green_s cn78xxp1;
13423 struct cvmx_pko_pq_debug_green_s cnf75xx;
13424 };
13425 typedef union cvmx_pko_pq_debug_green cvmx_pko_pq_debug_green_t;
13426
13427
13428
13429
13430 union cvmx_pko_pq_debug_links {
13431 uint64_t u64;
13432 struct cvmx_pko_pq_debug_links_s {
13433 #ifdef __BIG_ENDIAN_BITFIELD
13434 uint64_t links_ready : 32;
13435 uint64_t peb_lnk_rdy_ir : 32;
13436 #else
13437 uint64_t peb_lnk_rdy_ir : 32;
13438 uint64_t links_ready : 32;
13439 #endif
13440 } s;
13441 struct cvmx_pko_pq_debug_links_s cn73xx;
13442 struct cvmx_pko_pq_debug_links_s cn78xx;
13443 struct cvmx_pko_pq_debug_links_s cn78xxp1;
13444 struct cvmx_pko_pq_debug_links_s cnf75xx;
13445 };
13446 typedef union cvmx_pko_pq_debug_links cvmx_pko_pq_debug_links_t;
13447
13448
13449
13450
13451 union cvmx_pko_pq_debug_yellow {
13452 uint64_t u64;
13453 struct cvmx_pko_pq_debug_yellow_s {
13454 #ifdef __BIG_ENDIAN_BITFIELD
13455 uint64_t y_valid : 32;
13456 uint64_t reserved_28_31 : 4;
13457 uint64_t link_vv : 28;
13458 #else
13459 uint64_t link_vv : 28;
13460 uint64_t reserved_28_31 : 4;
13461 uint64_t y_valid : 32;
13462 #endif
13463 } s;
13464 struct cvmx_pko_pq_debug_yellow_s cn73xx;
13465 struct cvmx_pko_pq_debug_yellow_s cn78xx;
13466 struct cvmx_pko_pq_debug_yellow_s cn78xxp1;
13467 struct cvmx_pko_pq_debug_yellow_s cnf75xx;
13468 };
13469 typedef union cvmx_pko_pq_debug_yellow cvmx_pko_pq_debug_yellow_t;
13470
13471
13472
13473
13474 union cvmx_pko_pqa_debug {
13475 uint64_t u64;
13476 struct cvmx_pko_pqa_debug_s {
13477 #ifdef __BIG_ENDIAN_BITFIELD
13478 uint64_t dbg_vec : 64;
13479 #else
13480 uint64_t dbg_vec : 64;
13481 #endif
13482 } s;
13483 struct cvmx_pko_pqa_debug_s cn73xx;
13484 struct cvmx_pko_pqa_debug_s cn78xx;
13485 struct cvmx_pko_pqa_debug_s cn78xxp1;
13486 struct cvmx_pko_pqa_debug_s cnf75xx;
13487 };
13488 typedef union cvmx_pko_pqa_debug cvmx_pko_pqa_debug_t;
13489
13490
13491
13492
13493
13494
13495
13496 union cvmx_pko_pqb_debug {
13497 uint64_t u64;
13498 struct cvmx_pko_pqb_debug_s {
13499 #ifdef __BIG_ENDIAN_BITFIELD
13500 uint64_t dbg_vec : 64;
13501 #else
13502 uint64_t dbg_vec : 64;
13503 #endif
13504 } s;
13505 struct cvmx_pko_pqb_debug_s cn73xx;
13506 struct cvmx_pko_pqb_debug_s cn78xx;
13507 struct cvmx_pko_pqb_debug_s cn78xxp1;
13508 struct cvmx_pko_pqb_debug_s cnf75xx;
13509 };
13510 typedef union cvmx_pko_pqb_debug cvmx_pko_pqb_debug_t;
13511
13512
13513
13514
13515
13516
13517
13518 union cvmx_pko_pse_dq_bist_status {
13519 uint64_t u64;
13520 struct cvmx_pko_pse_dq_bist_status_s {
13521 #ifdef __BIG_ENDIAN_BITFIELD
13522 uint64_t reserved_8_63 : 56;
13523 uint64_t rt7_sram : 1;
13524 uint64_t rt6_sram : 1;
13525 uint64_t rt5_sram : 1;
13526 uint64_t reserved_4_4 : 1;
13527 uint64_t rt3_sram : 1;
13528 uint64_t rt2_sram : 1;
13529 uint64_t rt1_sram : 1;
13530 uint64_t rt0_sram : 1;
13531 #else
13532 uint64_t rt0_sram : 1;
13533 uint64_t rt1_sram : 1;
13534 uint64_t rt2_sram : 1;
13535 uint64_t rt3_sram : 1;
13536 uint64_t reserved_4_4 : 1;
13537 uint64_t rt5_sram : 1;
13538 uint64_t rt6_sram : 1;
13539 uint64_t rt7_sram : 1;
13540 uint64_t reserved_8_63 : 56;
13541 #endif
13542 } s;
13543 struct cvmx_pko_pse_dq_bist_status_cn73xx {
13544 #ifdef __BIG_ENDIAN_BITFIELD
13545 uint64_t reserved_5_63 : 59;
13546 uint64_t wt_sram : 1;
13547 uint64_t reserved_2_3 : 2;
13548 uint64_t rt1_sram : 1;
13549 uint64_t rt0_sram : 1;
13550 #else
13551 uint64_t rt0_sram : 1;
13552 uint64_t rt1_sram : 1;
13553 uint64_t reserved_2_3 : 2;
13554 uint64_t wt_sram : 1;
13555 uint64_t reserved_5_63 : 59;
13556 #endif
13557 } cn73xx;
13558 struct cvmx_pko_pse_dq_bist_status_cn78xx {
13559 #ifdef __BIG_ENDIAN_BITFIELD
13560 uint64_t reserved_9_63 : 55;
13561 uint64_t wt_sram : 1;
13562 uint64_t rt7_sram : 1;
13563 uint64_t rt6_sram : 1;
13564 uint64_t rt5_sram : 1;
13565 uint64_t rt4_sram : 1;
13566 uint64_t rt3_sram : 1;
13567 uint64_t rt2_sram : 1;
13568 uint64_t rt1_sram : 1;
13569 uint64_t rt0_sram : 1;
13570 #else
13571 uint64_t rt0_sram : 1;
13572 uint64_t rt1_sram : 1;
13573 uint64_t rt2_sram : 1;
13574 uint64_t rt3_sram : 1;
13575 uint64_t rt4_sram : 1;
13576 uint64_t rt5_sram : 1;
13577 uint64_t rt6_sram : 1;
13578 uint64_t rt7_sram : 1;
13579 uint64_t wt_sram : 1;
13580 uint64_t reserved_9_63 : 55;
13581 #endif
13582 } cn78xx;
13583 struct cvmx_pko_pse_dq_bist_status_cn78xx cn78xxp1;
13584 struct cvmx_pko_pse_dq_bist_status_cn73xx cnf75xx;
13585 };
13586 typedef union cvmx_pko_pse_dq_bist_status cvmx_pko_pse_dq_bist_status_t;
13587
13588
13589
13590
13591 union cvmx_pko_pse_dq_ecc_ctl0 {
13592 uint64_t u64;
13593 struct cvmx_pko_pse_dq_ecc_ctl0_s {
13594 #ifdef __BIG_ENDIAN_BITFIELD
13595 uint64_t dq_wt_ram_flip : 2;
13596 uint64_t dq_wt_ram_cdis : 1;
13597 uint64_t dq_rt7_flip : 2;
13598 uint64_t dq_rt7_cdis : 1;
13599 uint64_t dq_rt6_flip : 2;
13600 uint64_t dq_rt6_cdis : 1;
13601 uint64_t dq_rt5_flip : 2;
13602 uint64_t dq_rt5_cdis : 1;
13603 uint64_t dq_rt4_flip : 2;
13604 uint64_t dq_rt4_cdis : 1;
13605 uint64_t dq_rt3_flip : 2;
13606 uint64_t dq_rt3_cdis : 1;
13607 uint64_t dq_rt2_flip : 2;
13608 uint64_t dq_rt2_cdis : 1;
13609 uint64_t dq_rt1_flip : 2;
13610 uint64_t dq_rt1_cdis : 1;
13611 uint64_t dq_rt0_flip : 2;
13612 uint64_t dq_rt0_cdis : 1;
13613 uint64_t reserved_0_36 : 37;
13614 #else
13615 uint64_t reserved_0_36 : 37;
13616 uint64_t dq_rt0_cdis : 1;
13617 uint64_t dq_rt0_flip : 2;
13618 uint64_t dq_rt1_cdis : 1;
13619 uint64_t dq_rt1_flip : 2;
13620 uint64_t dq_rt2_cdis : 1;
13621 uint64_t dq_rt2_flip : 2;
13622 uint64_t dq_rt3_cdis : 1;
13623 uint64_t dq_rt3_flip : 2;
13624 uint64_t dq_rt4_cdis : 1;
13625 uint64_t dq_rt4_flip : 2;
13626 uint64_t dq_rt5_cdis : 1;
13627 uint64_t dq_rt5_flip : 2;
13628 uint64_t dq_rt6_cdis : 1;
13629 uint64_t dq_rt6_flip : 2;
13630 uint64_t dq_rt7_cdis : 1;
13631 uint64_t dq_rt7_flip : 2;
13632 uint64_t dq_wt_ram_cdis : 1;
13633 uint64_t dq_wt_ram_flip : 2;
13634 #endif
13635 } s;
13636 struct cvmx_pko_pse_dq_ecc_ctl0_cn73xx {
13637 #ifdef __BIG_ENDIAN_BITFIELD
13638 uint64_t dq_wt_ram_flip : 2;
13639 uint64_t dq_wt_ram_cdis : 1;
13640 uint64_t reserved_43_60 : 18;
13641 uint64_t dq_rt1_flip : 2;
13642 uint64_t dq_rt1_cdis : 1;
13643 uint64_t dq_rt0_flip : 2;
13644 uint64_t dq_rt0_cdis : 1;
13645 uint64_t reserved_0_36 : 37;
13646 #else
13647 uint64_t reserved_0_36 : 37;
13648 uint64_t dq_rt0_cdis : 1;
13649 uint64_t dq_rt0_flip : 2;
13650 uint64_t dq_rt1_cdis : 1;
13651 uint64_t dq_rt1_flip : 2;
13652 uint64_t reserved_43_60 : 18;
13653 uint64_t dq_wt_ram_cdis : 1;
13654 uint64_t dq_wt_ram_flip : 2;
13655 #endif
13656 } cn73xx;
13657 struct cvmx_pko_pse_dq_ecc_ctl0_s cn78xx;
13658 struct cvmx_pko_pse_dq_ecc_ctl0_s cn78xxp1;
13659 struct cvmx_pko_pse_dq_ecc_ctl0_cn73xx cnf75xx;
13660 };
13661 typedef union cvmx_pko_pse_dq_ecc_ctl0 cvmx_pko_pse_dq_ecc_ctl0_t;
13662
13663
13664
13665
13666 union cvmx_pko_pse_dq_ecc_dbe_sts0 {
13667 uint64_t u64;
13668 struct cvmx_pko_pse_dq_ecc_dbe_sts0_s {
13669 #ifdef __BIG_ENDIAN_BITFIELD
13670 uint64_t dq_wt_ram_dbe : 1;
13671 uint64_t dq_rt7_dbe : 1;
13672 uint64_t dq_rt6_dbe : 1;
13673 uint64_t dq_rt5_dbe : 1;
13674 uint64_t dq_rt4_dbe : 1;
13675 uint64_t dq_rt3_dbe : 1;
13676 uint64_t dq_rt2_dbe : 1;
13677 uint64_t dq_rt1_dbe : 1;
13678 uint64_t dq_rt0_dbe : 1;
13679 uint64_t reserved_0_54 : 55;
13680 #else
13681 uint64_t reserved_0_54 : 55;
13682 uint64_t dq_rt0_dbe : 1;
13683 uint64_t dq_rt1_dbe : 1;
13684 uint64_t dq_rt2_dbe : 1;
13685 uint64_t dq_rt3_dbe : 1;
13686 uint64_t dq_rt4_dbe : 1;
13687 uint64_t dq_rt5_dbe : 1;
13688 uint64_t dq_rt6_dbe : 1;
13689 uint64_t dq_rt7_dbe : 1;
13690 uint64_t dq_wt_ram_dbe : 1;
13691 #endif
13692 } s;
13693 struct cvmx_pko_pse_dq_ecc_dbe_sts0_cn73xx {
13694 #ifdef __BIG_ENDIAN_BITFIELD
13695 uint64_t dq_wt_ram_dbe : 1;
13696 uint64_t reserved_57_62 : 6;
13697 uint64_t dq_rt1_dbe : 1;
13698 uint64_t dq_rt0_dbe : 1;
13699 uint64_t reserved_0_54 : 55;
13700 #else
13701 uint64_t reserved_0_54 : 55;
13702 uint64_t dq_rt0_dbe : 1;
13703 uint64_t dq_rt1_dbe : 1;
13704 uint64_t reserved_57_62 : 6;
13705 uint64_t dq_wt_ram_dbe : 1;
13706 #endif
13707 } cn73xx;
13708 struct cvmx_pko_pse_dq_ecc_dbe_sts0_s cn78xx;
13709 struct cvmx_pko_pse_dq_ecc_dbe_sts0_s cn78xxp1;
13710 struct cvmx_pko_pse_dq_ecc_dbe_sts0_cn73xx cnf75xx;
13711 };
13712 typedef union cvmx_pko_pse_dq_ecc_dbe_sts0 cvmx_pko_pse_dq_ecc_dbe_sts0_t;
13713
13714
13715
13716
13717 union cvmx_pko_pse_dq_ecc_dbe_sts_cmb0 {
13718 uint64_t u64;
13719 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s {
13720 #ifdef __BIG_ENDIAN_BITFIELD
13721 uint64_t pse_dq_dbe_cmb0 : 1;
13722
13723
13724
13725 uint64_t reserved_0_62 : 63;
13726 #else
13727 uint64_t reserved_0_62 : 63;
13728 uint64_t pse_dq_dbe_cmb0 : 1;
13729 #endif
13730 } s;
13731 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s cn73xx;
13732 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s cn78xx;
13733 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s cn78xxp1;
13734 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s cnf75xx;
13735 };
13736 typedef union cvmx_pko_pse_dq_ecc_dbe_sts_cmb0 cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_t;
13737
13738
13739
13740
13741 union cvmx_pko_pse_dq_ecc_sbe_sts0 {
13742 uint64_t u64;
13743 struct cvmx_pko_pse_dq_ecc_sbe_sts0_s {
13744 #ifdef __BIG_ENDIAN_BITFIELD
13745 uint64_t dq_wt_ram_sbe : 1;
13746 uint64_t dq_rt7_sbe : 1;
13747 uint64_t dq_rt6_sbe : 1;
13748 uint64_t dq_rt5_sbe : 1;
13749 uint64_t dq_rt4_sbe : 1;
13750 uint64_t dq_rt3_sbe : 1;
13751 uint64_t dq_rt2_sbe : 1;
13752 uint64_t dq_rt1_sbe : 1;
13753 uint64_t dq_rt0_sbe : 1;
13754 uint64_t reserved_0_54 : 55;
13755 #else
13756 uint64_t reserved_0_54 : 55;
13757 uint64_t dq_rt0_sbe : 1;
13758 uint64_t dq_rt1_sbe : 1;
13759 uint64_t dq_rt2_sbe : 1;
13760 uint64_t dq_rt3_sbe : 1;
13761 uint64_t dq_rt4_sbe : 1;
13762 uint64_t dq_rt5_sbe : 1;
13763 uint64_t dq_rt6_sbe : 1;
13764 uint64_t dq_rt7_sbe : 1;
13765 uint64_t dq_wt_ram_sbe : 1;
13766 #endif
13767 } s;
13768 struct cvmx_pko_pse_dq_ecc_sbe_sts0_cn73xx {
13769 #ifdef __BIG_ENDIAN_BITFIELD
13770 uint64_t dq_wt_ram_sbe : 1;
13771 uint64_t reserved_57_62 : 6;
13772 uint64_t dq_rt1_sbe : 1;
13773 uint64_t dq_rt0_sbe : 1;
13774 uint64_t reserved_0_54 : 55;
13775 #else
13776 uint64_t reserved_0_54 : 55;
13777 uint64_t dq_rt0_sbe : 1;
13778 uint64_t dq_rt1_sbe : 1;
13779 uint64_t reserved_57_62 : 6;
13780 uint64_t dq_wt_ram_sbe : 1;
13781 #endif
13782 } cn73xx;
13783 struct cvmx_pko_pse_dq_ecc_sbe_sts0_s cn78xx;
13784 struct cvmx_pko_pse_dq_ecc_sbe_sts0_s cn78xxp1;
13785 struct cvmx_pko_pse_dq_ecc_sbe_sts0_cn73xx cnf75xx;
13786 };
13787 typedef union cvmx_pko_pse_dq_ecc_sbe_sts0 cvmx_pko_pse_dq_ecc_sbe_sts0_t;
13788
13789
13790
13791
13792 union cvmx_pko_pse_dq_ecc_sbe_sts_cmb0 {
13793 uint64_t u64;
13794 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s {
13795 #ifdef __BIG_ENDIAN_BITFIELD
13796 uint64_t pse_dq_sbe_cmb0 : 1;
13797
13798
13799
13800 uint64_t reserved_0_62 : 63;
13801 #else
13802 uint64_t reserved_0_62 : 63;
13803 uint64_t pse_dq_sbe_cmb0 : 1;
13804 #endif
13805 } s;
13806 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s cn73xx;
13807 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s cn78xx;
13808 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s cn78xxp1;
13809 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s cnf75xx;
13810 };
13811 typedef union cvmx_pko_pse_dq_ecc_sbe_sts_cmb0 cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_t;
13812
13813
13814
13815
13816
13817
13818
13819 union cvmx_pko_pse_pq_bist_status {
13820 uint64_t u64;
13821 struct cvmx_pko_pse_pq_bist_status_s {
13822 #ifdef __BIG_ENDIAN_BITFIELD
13823 uint64_t reserved_15_63 : 49;
13824 uint64_t tp_sram : 1;
13825 uint64_t irq_fifo_sram : 1;
13826 uint64_t wmd_sram : 1;
13827 uint64_t wms_sram : 1;
13828 uint64_t cxd_sram : 1;
13829 uint64_t dqd_sram : 1;
13830 uint64_t dqs_sram : 1;
13831 uint64_t pqd_sram : 1;
13832 uint64_t pqr_sram : 1;
13833 uint64_t pqy_sram : 1;
13834 uint64_t pqg_sram : 1;
13835 uint64_t std_sram : 1;
13836 uint64_t st_sram : 1;
13837 uint64_t reserved_1_1 : 1;
13838 uint64_t cxs_sram : 1;
13839 #else
13840 uint64_t cxs_sram : 1;
13841 uint64_t reserved_1_1 : 1;
13842 uint64_t st_sram : 1;
13843 uint64_t std_sram : 1;
13844 uint64_t pqg_sram : 1;
13845 uint64_t pqy_sram : 1;
13846 uint64_t pqr_sram : 1;
13847 uint64_t pqd_sram : 1;
13848 uint64_t dqs_sram : 1;
13849 uint64_t dqd_sram : 1;
13850 uint64_t cxd_sram : 1;
13851 uint64_t wms_sram : 1;
13852 uint64_t wmd_sram : 1;
13853 uint64_t irq_fifo_sram : 1;
13854 uint64_t tp_sram : 1;
13855 uint64_t reserved_15_63 : 49;
13856 #endif
13857 } s;
13858 struct cvmx_pko_pse_pq_bist_status_cn73xx {
13859 #ifdef __BIG_ENDIAN_BITFIELD
13860 uint64_t reserved_15_63 : 49;
13861 uint64_t tp_sram : 1;
13862 uint64_t reserved_13_13 : 1;
13863 uint64_t wmd_sram : 1;
13864 uint64_t reserved_11_11 : 1;
13865 uint64_t cxd_sram : 1;
13866 uint64_t dqd_sram : 1;
13867 uint64_t dqs_sram : 1;
13868 uint64_t pqd_sram : 1;
13869 uint64_t pqr_sram : 1;
13870 uint64_t pqy_sram : 1;
13871 uint64_t pqg_sram : 1;
13872 uint64_t std_sram : 1;
13873 uint64_t st_sram : 1;
13874 uint64_t reserved_1_1 : 1;
13875 uint64_t cxs_sram : 1;
13876 #else
13877 uint64_t cxs_sram : 1;
13878 uint64_t reserved_1_1 : 1;
13879 uint64_t st_sram : 1;
13880 uint64_t std_sram : 1;
13881 uint64_t pqg_sram : 1;
13882 uint64_t pqy_sram : 1;
13883 uint64_t pqr_sram : 1;
13884 uint64_t pqd_sram : 1;
13885 uint64_t dqs_sram : 1;
13886 uint64_t dqd_sram : 1;
13887 uint64_t cxd_sram : 1;
13888 uint64_t reserved_11_11 : 1;
13889 uint64_t wmd_sram : 1;
13890 uint64_t reserved_13_13 : 1;
13891 uint64_t tp_sram : 1;
13892 uint64_t reserved_15_63 : 49;
13893 #endif
13894 } cn73xx;
13895 struct cvmx_pko_pse_pq_bist_status_s cn78xx;
13896 struct cvmx_pko_pse_pq_bist_status_s cn78xxp1;
13897 struct cvmx_pko_pse_pq_bist_status_cn73xx cnf75xx;
13898 };
13899 typedef union cvmx_pko_pse_pq_bist_status cvmx_pko_pse_pq_bist_status_t;
13900
13901
13902
13903
13904 union cvmx_pko_pse_pq_ecc_ctl0 {
13905 uint64_t u64;
13906 struct cvmx_pko_pse_pq_ecc_ctl0_s {
13907 #ifdef __BIG_ENDIAN_BITFIELD
13908 uint64_t pq_cxs_ram_flip : 2;
13909 uint64_t pq_cxs_ram_cdis : 1;
13910 uint64_t pq_cxd_ram_flip : 2;
13911 uint64_t pq_cxd_ram_cdis : 1;
13912 uint64_t irq_fifo_sram_flip : 2;
13913 uint64_t irq_fifo_sram_cdis : 1;
13914 uint64_t tp_sram_flip : 2;
13915 uint64_t tp_sram_cdis : 1;
13916 uint64_t pq_std_ram_flip : 2;
13917 uint64_t pq_std_ram_cdis : 1;
13918 uint64_t pq_st_ram_flip : 2;
13919 uint64_t pq_st_ram_cdis : 1;
13920 uint64_t pq_wmd_ram_flip : 2;
13921 uint64_t pq_wmd_ram_cdis : 1;
13922 uint64_t pq_wms_ram_flip : 2;
13923 uint64_t pq_wms_ram_cdis : 1;
13924 uint64_t reserved_0_39 : 40;
13925 #else
13926 uint64_t reserved_0_39 : 40;
13927 uint64_t pq_wms_ram_cdis : 1;
13928 uint64_t pq_wms_ram_flip : 2;
13929 uint64_t pq_wmd_ram_cdis : 1;
13930 uint64_t pq_wmd_ram_flip : 2;
13931 uint64_t pq_st_ram_cdis : 1;
13932 uint64_t pq_st_ram_flip : 2;
13933 uint64_t pq_std_ram_cdis : 1;
13934 uint64_t pq_std_ram_flip : 2;
13935 uint64_t tp_sram_cdis : 1;
13936 uint64_t tp_sram_flip : 2;
13937 uint64_t irq_fifo_sram_cdis : 1;
13938 uint64_t irq_fifo_sram_flip : 2;
13939 uint64_t pq_cxd_ram_cdis : 1;
13940 uint64_t pq_cxd_ram_flip : 2;
13941 uint64_t pq_cxs_ram_cdis : 1;
13942 uint64_t pq_cxs_ram_flip : 2;
13943 #endif
13944 } s;
13945 struct cvmx_pko_pse_pq_ecc_ctl0_cn73xx {
13946 #ifdef __BIG_ENDIAN_BITFIELD
13947 uint64_t pq_cxs_ram_flip : 2;
13948 uint64_t pq_cxs_ram_cdis : 1;
13949 uint64_t pq_cxd_ram_flip : 2;
13950 uint64_t pq_cxd_ram_cdis : 1;
13951 uint64_t reserved_55_57 : 3;
13952 uint64_t tp_sram_flip : 2;
13953 uint64_t tp_sram_cdis : 1;
13954 uint64_t pq_std_ram_flip : 2;
13955 uint64_t pq_std_ram_cdis : 1;
13956 uint64_t pq_st_ram_flip : 2;
13957 uint64_t pq_st_ram_cdis : 1;
13958 uint64_t pq_wmd_ram_flip : 2;
13959 uint64_t pq_wmd_ram_cdis : 1;
13960 uint64_t reserved_0_42 : 43;
13961 #else
13962 uint64_t reserved_0_42 : 43;
13963 uint64_t pq_wmd_ram_cdis : 1;
13964 uint64_t pq_wmd_ram_flip : 2;
13965 uint64_t pq_st_ram_cdis : 1;
13966 uint64_t pq_st_ram_flip : 2;
13967 uint64_t pq_std_ram_cdis : 1;
13968 uint64_t pq_std_ram_flip : 2;
13969 uint64_t tp_sram_cdis : 1;
13970 uint64_t tp_sram_flip : 2;
13971 uint64_t reserved_55_57 : 3;
13972 uint64_t pq_cxd_ram_cdis : 1;
13973 uint64_t pq_cxd_ram_flip : 2;
13974 uint64_t pq_cxs_ram_cdis : 1;
13975 uint64_t pq_cxs_ram_flip : 2;
13976 #endif
13977 } cn73xx;
13978 struct cvmx_pko_pse_pq_ecc_ctl0_s cn78xx;
13979 struct cvmx_pko_pse_pq_ecc_ctl0_s cn78xxp1;
13980 struct cvmx_pko_pse_pq_ecc_ctl0_cn73xx cnf75xx;
13981 };
13982 typedef union cvmx_pko_pse_pq_ecc_ctl0 cvmx_pko_pse_pq_ecc_ctl0_t;
13983
13984
13985
13986
13987 union cvmx_pko_pse_pq_ecc_dbe_sts0 {
13988 uint64_t u64;
13989 struct cvmx_pko_pse_pq_ecc_dbe_sts0_s {
13990 #ifdef __BIG_ENDIAN_BITFIELD
13991 uint64_t pq_cxs_ram_dbe : 1;
13992 uint64_t pq_cxd_ram_dbe : 1;
13993 uint64_t irq_fifo_sram_dbe : 1;
13994 uint64_t tp_sram_dbe : 1;
13995 uint64_t pq_std_ram_dbe : 1;
13996 uint64_t pq_st_ram_dbe : 1;
13997 uint64_t pq_wmd_ram_dbe : 1;
13998 uint64_t pq_wms_ram_dbe : 1;
13999 uint64_t reserved_0_55 : 56;
14000 #else
14001 uint64_t reserved_0_55 : 56;
14002 uint64_t pq_wms_ram_dbe : 1;
14003 uint64_t pq_wmd_ram_dbe : 1;
14004 uint64_t pq_st_ram_dbe : 1;
14005 uint64_t pq_std_ram_dbe : 1;
14006 uint64_t tp_sram_dbe : 1;
14007 uint64_t irq_fifo_sram_dbe : 1;
14008 uint64_t pq_cxd_ram_dbe : 1;
14009 uint64_t pq_cxs_ram_dbe : 1;
14010 #endif
14011 } s;
14012 struct cvmx_pko_pse_pq_ecc_dbe_sts0_cn73xx {
14013 #ifdef __BIG_ENDIAN_BITFIELD
14014 uint64_t pq_cxs_ram_dbe : 1;
14015 uint64_t pq_cxd_ram_dbe : 1;
14016 uint64_t reserved_61_61 : 1;
14017 uint64_t tp_sram_dbe : 1;
14018 uint64_t pq_std_ram_dbe : 1;
14019 uint64_t pq_st_ram_dbe : 1;
14020 uint64_t pq_wmd_ram_dbe : 1;
14021 uint64_t reserved_0_56 : 57;
14022 #else
14023 uint64_t reserved_0_56 : 57;
14024 uint64_t pq_wmd_ram_dbe : 1;
14025 uint64_t pq_st_ram_dbe : 1;
14026 uint64_t pq_std_ram_dbe : 1;
14027 uint64_t tp_sram_dbe : 1;
14028 uint64_t reserved_61_61 : 1;
14029 uint64_t pq_cxd_ram_dbe : 1;
14030 uint64_t pq_cxs_ram_dbe : 1;
14031 #endif
14032 } cn73xx;
14033 struct cvmx_pko_pse_pq_ecc_dbe_sts0_s cn78xx;
14034 struct cvmx_pko_pse_pq_ecc_dbe_sts0_s cn78xxp1;
14035 struct cvmx_pko_pse_pq_ecc_dbe_sts0_cn73xx cnf75xx;
14036 };
14037 typedef union cvmx_pko_pse_pq_ecc_dbe_sts0 cvmx_pko_pse_pq_ecc_dbe_sts0_t;
14038
14039
14040
14041
14042 union cvmx_pko_pse_pq_ecc_dbe_sts_cmb0 {
14043 uint64_t u64;
14044 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s {
14045 #ifdef __BIG_ENDIAN_BITFIELD
14046 uint64_t pse_pq_dbe_cmb0 : 1;
14047
14048
14049
14050 uint64_t reserved_0_62 : 63;
14051 #else
14052 uint64_t reserved_0_62 : 63;
14053 uint64_t pse_pq_dbe_cmb0 : 1;
14054 #endif
14055 } s;
14056 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s cn73xx;
14057 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s cn78xx;
14058 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s cn78xxp1;
14059 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s cnf75xx;
14060 };
14061 typedef union cvmx_pko_pse_pq_ecc_dbe_sts_cmb0 cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_t;
14062
14063
14064
14065
14066 union cvmx_pko_pse_pq_ecc_sbe_sts0 {
14067 uint64_t u64;
14068 struct cvmx_pko_pse_pq_ecc_sbe_sts0_s {
14069 #ifdef __BIG_ENDIAN_BITFIELD
14070 uint64_t pq_cxs_ram_sbe : 1;
14071 uint64_t pq_cxd_ram_sbe : 1;
14072 uint64_t irq_fifo_sram_sbe : 1;
14073 uint64_t tp_sram_sbe : 1;
14074 uint64_t pq_std_ram_sbe : 1;
14075 uint64_t pq_st_ram_sbe : 1;
14076 uint64_t pq_wmd_ram_sbe : 1;
14077 uint64_t pq_wms_ram_sbe : 1;
14078 uint64_t reserved_0_55 : 56;
14079 #else
14080 uint64_t reserved_0_55 : 56;
14081 uint64_t pq_wms_ram_sbe : 1;
14082 uint64_t pq_wmd_ram_sbe : 1;
14083 uint64_t pq_st_ram_sbe : 1;
14084 uint64_t pq_std_ram_sbe : 1;
14085 uint64_t tp_sram_sbe : 1;
14086 uint64_t irq_fifo_sram_sbe : 1;
14087 uint64_t pq_cxd_ram_sbe : 1;
14088 uint64_t pq_cxs_ram_sbe : 1;
14089 #endif
14090 } s;
14091 struct cvmx_pko_pse_pq_ecc_sbe_sts0_cn73xx {
14092 #ifdef __BIG_ENDIAN_BITFIELD
14093 uint64_t pq_cxs_ram_sbe : 1;
14094 uint64_t pq_cxd_ram_sbe : 1;
14095 uint64_t reserved_61_61 : 1;
14096 uint64_t tp_sram_sbe : 1;
14097 uint64_t pq_std_ram_sbe : 1;
14098 uint64_t pq_st_ram_sbe : 1;
14099 uint64_t pq_wmd_ram_sbe : 1;
14100 uint64_t reserved_0_56 : 57;
14101 #else
14102 uint64_t reserved_0_56 : 57;
14103 uint64_t pq_wmd_ram_sbe : 1;
14104 uint64_t pq_st_ram_sbe : 1;
14105 uint64_t pq_std_ram_sbe : 1;
14106 uint64_t tp_sram_sbe : 1;
14107 uint64_t reserved_61_61 : 1;
14108 uint64_t pq_cxd_ram_sbe : 1;
14109 uint64_t pq_cxs_ram_sbe : 1;
14110 #endif
14111 } cn73xx;
14112 struct cvmx_pko_pse_pq_ecc_sbe_sts0_s cn78xx;
14113 struct cvmx_pko_pse_pq_ecc_sbe_sts0_s cn78xxp1;
14114 struct cvmx_pko_pse_pq_ecc_sbe_sts0_cn73xx cnf75xx;
14115 };
14116 typedef union cvmx_pko_pse_pq_ecc_sbe_sts0 cvmx_pko_pse_pq_ecc_sbe_sts0_t;
14117
14118
14119
14120
14121 union cvmx_pko_pse_pq_ecc_sbe_sts_cmb0 {
14122 uint64_t u64;
14123 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s {
14124 #ifdef __BIG_ENDIAN_BITFIELD
14125 uint64_t pse_pq_sbe_cmb0 : 1;
14126
14127
14128
14129 uint64_t reserved_0_62 : 63;
14130 #else
14131 uint64_t reserved_0_62 : 63;
14132 uint64_t pse_pq_sbe_cmb0 : 1;
14133 #endif
14134 } s;
14135 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s cn73xx;
14136 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s cn78xx;
14137 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s cn78xxp1;
14138 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s cnf75xx;
14139 };
14140 typedef union cvmx_pko_pse_pq_ecc_sbe_sts_cmb0 cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_t;
14141
14142
14143
14144
14145
14146
14147
14148 union cvmx_pko_pse_sq1_bist_status {
14149 uint64_t u64;
14150 struct cvmx_pko_pse_sq1_bist_status_s {
14151 #ifdef __BIG_ENDIAN_BITFIELD
14152 uint64_t reserved_29_63 : 35;
14153 uint64_t sc_sram : 1;
14154 uint64_t pc_sram : 1;
14155 uint64_t xon_sram : 1;
14156 uint64_t cc_sram : 1;
14157 uint64_t vc1_sram : 1;
14158 uint64_t vc0_sram : 1;
14159 uint64_t reserved_21_22 : 2;
14160 uint64_t tp1_sram : 1;
14161 uint64_t tp0_sram : 1;
14162 uint64_t xo_sram : 1;
14163 uint64_t rt_sram : 1;
14164 uint64_t reserved_9_16 : 8;
14165 uint64_t tw1_cmd_fifo : 1;
14166 uint64_t std_sram : 1;
14167 uint64_t sts_sram : 1;
14168 uint64_t tw0_cmd_fifo : 1;
14169 uint64_t cxd_sram : 1;
14170 uint64_t cxs_sram : 1;
14171 uint64_t nt_sram : 1;
14172 uint64_t pt_sram : 1;
14173 uint64_t wt_sram : 1;
14174 #else
14175 uint64_t wt_sram : 1;
14176 uint64_t pt_sram : 1;
14177 uint64_t nt_sram : 1;
14178 uint64_t cxs_sram : 1;
14179 uint64_t cxd_sram : 1;
14180 uint64_t tw0_cmd_fifo : 1;
14181 uint64_t sts_sram : 1;
14182 uint64_t std_sram : 1;
14183 uint64_t tw1_cmd_fifo : 1;
14184 uint64_t reserved_9_16 : 8;
14185 uint64_t rt_sram : 1;
14186 uint64_t xo_sram : 1;
14187 uint64_t tp0_sram : 1;
14188 uint64_t tp1_sram : 1;
14189 uint64_t reserved_21_22 : 2;
14190 uint64_t vc0_sram : 1;
14191 uint64_t vc1_sram : 1;
14192 uint64_t cc_sram : 1;
14193 uint64_t xon_sram : 1;
14194 uint64_t pc_sram : 1;
14195 uint64_t sc_sram : 1;
14196 uint64_t reserved_29_63 : 35;
14197 #endif
14198 } s;
14199 struct cvmx_pko_pse_sq1_bist_status_cn73xx {
14200 #ifdef __BIG_ENDIAN_BITFIELD
14201 uint64_t reserved_29_63 : 35;
14202 uint64_t sc_sram : 1;
14203 uint64_t pc_sram : 1;
14204 uint64_t xon_sram : 1;
14205 uint64_t cc_sram : 1;
14206 uint64_t vc1_sram : 1;
14207 uint64_t vc0_sram : 1;
14208 uint64_t reserved_20_22 : 3;
14209 uint64_t tp0_sram : 1;
14210 uint64_t xo_sram : 1;
14211 uint64_t rt_sram : 1;
14212 uint64_t reserved_9_16 : 8;
14213 uint64_t tw1_cmd_fifo : 1;
14214 uint64_t std_sram : 1;
14215 uint64_t sts_sram : 1;
14216 uint64_t tw0_cmd_fifo : 1;
14217 uint64_t cxd_sram : 1;
14218 uint64_t cxs_sram : 1;
14219 uint64_t nt_sram : 1;
14220 uint64_t pt_sram : 1;
14221 uint64_t wt_sram : 1;
14222 #else
14223 uint64_t wt_sram : 1;
14224 uint64_t pt_sram : 1;
14225 uint64_t nt_sram : 1;
14226 uint64_t cxs_sram : 1;
14227 uint64_t cxd_sram : 1;
14228 uint64_t tw0_cmd_fifo : 1;
14229 uint64_t sts_sram : 1;
14230 uint64_t std_sram : 1;
14231 uint64_t tw1_cmd_fifo : 1;
14232 uint64_t reserved_9_16 : 8;
14233 uint64_t rt_sram : 1;
14234 uint64_t xo_sram : 1;
14235 uint64_t tp0_sram : 1;
14236 uint64_t reserved_20_22 : 3;
14237 uint64_t vc0_sram : 1;
14238 uint64_t vc1_sram : 1;
14239 uint64_t cc_sram : 1;
14240 uint64_t xon_sram : 1;
14241 uint64_t pc_sram : 1;
14242 uint64_t sc_sram : 1;
14243 uint64_t reserved_29_63 : 35;
14244 #endif
14245 } cn73xx;
14246 struct cvmx_pko_pse_sq1_bist_status_s cn78xx;
14247 struct cvmx_pko_pse_sq1_bist_status_s cn78xxp1;
14248 struct cvmx_pko_pse_sq1_bist_status_cn73xx cnf75xx;
14249 };
14250 typedef union cvmx_pko_pse_sq1_bist_status cvmx_pko_pse_sq1_bist_status_t;
14251
14252
14253
14254
14255 union cvmx_pko_pse_sq1_ecc_ctl0 {
14256 uint64_t u64;
14257 struct cvmx_pko_pse_sq1_ecc_ctl0_s {
14258 #ifdef __BIG_ENDIAN_BITFIELD
14259 uint64_t cxs_ram_flip : 2;
14260 uint64_t cxs_ram_cdis : 1;
14261 uint64_t cxd_ram_flip : 2;
14262 uint64_t cxd_ram_cdis : 1;
14263 uint64_t vc1_sram_flip : 2;
14264 uint64_t vc1_sram_cdis : 1;
14265 uint64_t vc0_sram_flip : 2;
14266 uint64_t vc0_sram_cdis : 1;
14267 uint64_t sq_pt_ram_flip : 2;
14268 uint64_t sq_pt_ram_cdis : 1;
14269 uint64_t sq_nt_ram_flip : 2;
14270 uint64_t sq_nt_ram_cdis : 1;
14271 uint64_t rt_ram_flip : 2;
14272 uint64_t rt_ram_cdis : 1;
14273 uint64_t pc_ram_flip : 2;
14274 uint64_t pc_ram_cdis : 1;
14275 uint64_t tw1_cmd_fifo_ram_flip : 2;
14276 uint64_t tw1_cmd_fifo_ram_cdis : 1;
14277 uint64_t tw0_cmd_fifo_ram_flip : 2;
14278 uint64_t tw0_cmd_fifo_ram_cdis : 1;
14279 uint64_t tp1_sram_flip : 2;
14280 uint64_t tp1_sram_cdis : 1;
14281 uint64_t tp0_sram_flip : 2;
14282 uint64_t tp0_sram_cdis : 1;
14283 uint64_t sts1_ram_flip : 2;
14284 uint64_t sts1_ram_cdis : 1;
14285 uint64_t sts0_ram_flip : 2;
14286 uint64_t sts0_ram_cdis : 1;
14287 uint64_t std1_ram_flip : 2;
14288 uint64_t std1_ram_cdis : 1;
14289 uint64_t std0_ram_flip : 2;
14290 uint64_t std0_ram_cdis : 1;
14291 uint64_t wt_ram_flip : 2;
14292 uint64_t wt_ram_cdis : 1;
14293 uint64_t sc_ram_flip : 2;
14294 uint64_t sc_ram_cdis : 1;
14295 uint64_t reserved_0_9 : 10;
14296 #else
14297 uint64_t reserved_0_9 : 10;
14298 uint64_t sc_ram_cdis : 1;
14299 uint64_t sc_ram_flip : 2;
14300 uint64_t wt_ram_cdis : 1;
14301 uint64_t wt_ram_flip : 2;
14302 uint64_t std0_ram_cdis : 1;
14303 uint64_t std0_ram_flip : 2;
14304 uint64_t std1_ram_cdis : 1;
14305 uint64_t std1_ram_flip : 2;
14306 uint64_t sts0_ram_cdis : 1;
14307 uint64_t sts0_ram_flip : 2;
14308 uint64_t sts1_ram_cdis : 1;
14309 uint64_t sts1_ram_flip : 2;
14310 uint64_t tp0_sram_cdis : 1;
14311 uint64_t tp0_sram_flip : 2;
14312 uint64_t tp1_sram_cdis : 1;
14313 uint64_t tp1_sram_flip : 2;
14314 uint64_t tw0_cmd_fifo_ram_cdis : 1;
14315 uint64_t tw0_cmd_fifo_ram_flip : 2;
14316 uint64_t tw1_cmd_fifo_ram_cdis : 1;
14317 uint64_t tw1_cmd_fifo_ram_flip : 2;
14318 uint64_t pc_ram_cdis : 1;
14319 uint64_t pc_ram_flip : 2;
14320 uint64_t rt_ram_cdis : 1;
14321 uint64_t rt_ram_flip : 2;
14322 uint64_t sq_nt_ram_cdis : 1;
14323 uint64_t sq_nt_ram_flip : 2;
14324 uint64_t sq_pt_ram_cdis : 1;
14325 uint64_t sq_pt_ram_flip : 2;
14326 uint64_t vc0_sram_cdis : 1;
14327 uint64_t vc0_sram_flip : 2;
14328 uint64_t vc1_sram_cdis : 1;
14329 uint64_t vc1_sram_flip : 2;
14330 uint64_t cxd_ram_cdis : 1;
14331 uint64_t cxd_ram_flip : 2;
14332 uint64_t cxs_ram_cdis : 1;
14333 uint64_t cxs_ram_flip : 2;
14334 #endif
14335 } s;
14336 struct cvmx_pko_pse_sq1_ecc_ctl0_cn73xx {
14337 #ifdef __BIG_ENDIAN_BITFIELD
14338 uint64_t cxs_ram_flip : 2;
14339 uint64_t cxs_ram_cdis : 1;
14340 uint64_t cxd_ram_flip : 2;
14341 uint64_t cxd_ram_cdis : 1;
14342 uint64_t reserved_55_57 : 3;
14343 uint64_t vc0_sram_flip : 2;
14344 uint64_t vc0_sram_cdis : 1;
14345 uint64_t sq_pt_ram_flip : 2;
14346 uint64_t sq_pt_ram_cdis : 1;
14347 uint64_t sq_nt_ram_flip : 2;
14348 uint64_t sq_nt_ram_cdis : 1;
14349 uint64_t rt_ram_flip : 2;
14350 uint64_t rt_ram_cdis : 1;
14351 uint64_t pc_ram_flip : 2;
14352 uint64_t pc_ram_cdis : 1;
14353 uint64_t reserved_37_39 : 3;
14354 uint64_t tw0_cmd_fifo_ram_flip : 2;
14355 uint64_t tw0_cmd_fifo_ram_cdis : 1;
14356 uint64_t reserved_31_33 : 3;
14357 uint64_t tp0_sram_flip : 2;
14358 uint64_t tp0_sram_cdis : 1;
14359 uint64_t reserved_25_27 : 3;
14360 uint64_t sts0_ram_flip : 2;
14361 uint64_t sts0_ram_cdis : 1;
14362 uint64_t reserved_19_21 : 3;
14363 uint64_t std0_ram_flip : 2;
14364 uint64_t std0_ram_cdis : 1;
14365 uint64_t wt_ram_flip : 2;
14366 uint64_t wt_ram_cdis : 1;
14367 uint64_t sc_ram_flip : 2;
14368 uint64_t sc_ram_cdis : 1;
14369 uint64_t reserved_0_9 : 10;
14370 #else
14371 uint64_t reserved_0_9 : 10;
14372 uint64_t sc_ram_cdis : 1;
14373 uint64_t sc_ram_flip : 2;
14374 uint64_t wt_ram_cdis : 1;
14375 uint64_t wt_ram_flip : 2;
14376 uint64_t std0_ram_cdis : 1;
14377 uint64_t std0_ram_flip : 2;
14378 uint64_t reserved_19_21 : 3;
14379 uint64_t sts0_ram_cdis : 1;
14380 uint64_t sts0_ram_flip : 2;
14381 uint64_t reserved_25_27 : 3;
14382 uint64_t tp0_sram_cdis : 1;
14383 uint64_t tp0_sram_flip : 2;
14384 uint64_t reserved_31_33 : 3;
14385 uint64_t tw0_cmd_fifo_ram_cdis : 1;
14386 uint64_t tw0_cmd_fifo_ram_flip : 2;
14387 uint64_t reserved_37_39 : 3;
14388 uint64_t pc_ram_cdis : 1;
14389 uint64_t pc_ram_flip : 2;
14390 uint64_t rt_ram_cdis : 1;
14391 uint64_t rt_ram_flip : 2;
14392 uint64_t sq_nt_ram_cdis : 1;
14393 uint64_t sq_nt_ram_flip : 2;
14394 uint64_t sq_pt_ram_cdis : 1;
14395 uint64_t sq_pt_ram_flip : 2;
14396 uint64_t vc0_sram_cdis : 1;
14397 uint64_t vc0_sram_flip : 2;
14398 uint64_t reserved_55_57 : 3;
14399 uint64_t cxd_ram_cdis : 1;
14400 uint64_t cxd_ram_flip : 2;
14401 uint64_t cxs_ram_cdis : 1;
14402 uint64_t cxs_ram_flip : 2;
14403 #endif
14404 } cn73xx;
14405 struct cvmx_pko_pse_sq1_ecc_ctl0_s cn78xx;
14406 struct cvmx_pko_pse_sq1_ecc_ctl0_s cn78xxp1;
14407 struct cvmx_pko_pse_sq1_ecc_ctl0_cn73xx cnf75xx;
14408 };
14409 typedef union cvmx_pko_pse_sq1_ecc_ctl0 cvmx_pko_pse_sq1_ecc_ctl0_t;
14410
14411
14412
14413
14414 union cvmx_pko_pse_sq1_ecc_dbe_sts0 {
14415 uint64_t u64;
14416 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_s {
14417 #ifdef __BIG_ENDIAN_BITFIELD
14418 uint64_t cxs_ram_dbe : 1;
14419 uint64_t cxd_ram_dbe : 1;
14420 uint64_t vc1_sram_dbe : 1;
14421 uint64_t vc0_sram_dbe : 1;
14422 uint64_t sq_pt_ram_dbe : 1;
14423 uint64_t sq_nt_ram_dbe : 1;
14424 uint64_t rt_ram_dbe : 1;
14425 uint64_t pc_ram_dbe : 1;
14426 uint64_t tw1_cmd_fifo_ram_dbe : 1;
14427 uint64_t tw0_cmd_fifo_ram_dbe : 1;
14428 uint64_t tp1_sram_dbe : 1;
14429 uint64_t tp0_sram_dbe : 1;
14430 uint64_t sts1_ram_dbe : 1;
14431 uint64_t sts0_ram_dbe : 1;
14432 uint64_t std1_ram_dbe : 1;
14433 uint64_t std0_ram_dbe : 1;
14434 uint64_t wt_ram_dbe : 1;
14435 uint64_t sc_ram_dbe : 1;
14436 uint64_t reserved_0_45 : 46;
14437 #else
14438 uint64_t reserved_0_45 : 46;
14439 uint64_t sc_ram_dbe : 1;
14440 uint64_t wt_ram_dbe : 1;
14441 uint64_t std0_ram_dbe : 1;
14442 uint64_t std1_ram_dbe : 1;
14443 uint64_t sts0_ram_dbe : 1;
14444 uint64_t sts1_ram_dbe : 1;
14445 uint64_t tp0_sram_dbe : 1;
14446 uint64_t tp1_sram_dbe : 1;
14447 uint64_t tw0_cmd_fifo_ram_dbe : 1;
14448 uint64_t tw1_cmd_fifo_ram_dbe : 1;
14449 uint64_t pc_ram_dbe : 1;
14450 uint64_t rt_ram_dbe : 1;
14451 uint64_t sq_nt_ram_dbe : 1;
14452 uint64_t sq_pt_ram_dbe : 1;
14453 uint64_t vc0_sram_dbe : 1;
14454 uint64_t vc1_sram_dbe : 1;
14455 uint64_t cxd_ram_dbe : 1;
14456 uint64_t cxs_ram_dbe : 1;
14457 #endif
14458 } s;
14459 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_cn73xx {
14460 #ifdef __BIG_ENDIAN_BITFIELD
14461 uint64_t cxs_ram_dbe : 1;
14462 uint64_t cxd_ram_dbe : 1;
14463 uint64_t reserved_61_61 : 1;
14464 uint64_t vc0_sram_dbe : 1;
14465 uint64_t sq_pt_ram_dbe : 1;
14466 uint64_t sq_nt_ram_dbe : 1;
14467 uint64_t rt_ram_dbe : 1;
14468 uint64_t pc_ram_dbe : 1;
14469 uint64_t reserved_55_55 : 1;
14470 uint64_t tw0_cmd_fifo_ram_dbe : 1;
14471 uint64_t reserved_53_53 : 1;
14472 uint64_t tp0_sram_dbe : 1;
14473 uint64_t reserved_51_51 : 1;
14474 uint64_t sts0_ram_dbe : 1;
14475 uint64_t reserved_49_49 : 1;
14476 uint64_t std0_ram_dbe : 1;
14477 uint64_t wt_ram_dbe : 1;
14478 uint64_t sc_ram_dbe : 1;
14479 uint64_t reserved_0_45 : 46;
14480 #else
14481 uint64_t reserved_0_45 : 46;
14482 uint64_t sc_ram_dbe : 1;
14483 uint64_t wt_ram_dbe : 1;
14484 uint64_t std0_ram_dbe : 1;
14485 uint64_t reserved_49_49 : 1;
14486 uint64_t sts0_ram_dbe : 1;
14487 uint64_t reserved_51_51 : 1;
14488 uint64_t tp0_sram_dbe : 1;
14489 uint64_t reserved_53_53 : 1;
14490 uint64_t tw0_cmd_fifo_ram_dbe : 1;
14491 uint64_t reserved_55_55 : 1;
14492 uint64_t pc_ram_dbe : 1;
14493 uint64_t rt_ram_dbe : 1;
14494 uint64_t sq_nt_ram_dbe : 1;
14495 uint64_t sq_pt_ram_dbe : 1;
14496 uint64_t vc0_sram_dbe : 1;
14497 uint64_t reserved_61_61 : 1;
14498 uint64_t cxd_ram_dbe : 1;
14499 uint64_t cxs_ram_dbe : 1;
14500 #endif
14501 } cn73xx;
14502 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_s cn78xx;
14503 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_s cn78xxp1;
14504 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_cn73xx cnf75xx;
14505 };
14506 typedef union cvmx_pko_pse_sq1_ecc_dbe_sts0 cvmx_pko_pse_sq1_ecc_dbe_sts0_t;
14507
14508
14509
14510
14511 union cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0 {
14512 uint64_t u64;
14513 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s {
14514 #ifdef __BIG_ENDIAN_BITFIELD
14515 uint64_t pse_sq1_dbe_cmb0 : 1;
14516
14517
14518
14519 uint64_t reserved_0_62 : 63;
14520 #else
14521 uint64_t reserved_0_62 : 63;
14522 uint64_t pse_sq1_dbe_cmb0 : 1;
14523 #endif
14524 } s;
14525 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s cn73xx;
14526 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s cn78xx;
14527 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s cn78xxp1;
14528 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s cnf75xx;
14529 };
14530 typedef union cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_t;
14531
14532
14533
14534
14535 union cvmx_pko_pse_sq1_ecc_sbe_sts0 {
14536 uint64_t u64;
14537 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_s {
14538 #ifdef __BIG_ENDIAN_BITFIELD
14539 uint64_t cxs_ram_sbe : 1;
14540 uint64_t cxd_ram_sbe : 1;
14541 uint64_t vc1_sram_sbe : 1;
14542 uint64_t vc0_sram_sbe : 1;
14543 uint64_t sq_pt_ram_sbe : 1;
14544 uint64_t sq_nt_ram_sbe : 1;
14545 uint64_t rt_ram_sbe : 1;
14546 uint64_t pc_ram_sbe : 1;
14547 uint64_t tw1_cmd_fifo_ram_sbe : 1;
14548 uint64_t tw0_cmd_fifo_ram_sbe : 1;
14549 uint64_t tp1_sram_sbe : 1;
14550 uint64_t tp0_sram_sbe : 1;
14551 uint64_t sts1_ram_sbe : 1;
14552 uint64_t sts0_ram_sbe : 1;
14553 uint64_t std1_ram_sbe : 1;
14554 uint64_t std0_ram_sbe : 1;
14555 uint64_t wt_ram_sbe : 1;
14556 uint64_t sc_ram_sbe : 1;
14557 uint64_t reserved_0_45 : 46;
14558 #else
14559 uint64_t reserved_0_45 : 46;
14560 uint64_t sc_ram_sbe : 1;
14561 uint64_t wt_ram_sbe : 1;
14562 uint64_t std0_ram_sbe : 1;
14563 uint64_t std1_ram_sbe : 1;
14564 uint64_t sts0_ram_sbe : 1;
14565 uint64_t sts1_ram_sbe : 1;
14566 uint64_t tp0_sram_sbe : 1;
14567 uint64_t tp1_sram_sbe : 1;
14568 uint64_t tw0_cmd_fifo_ram_sbe : 1;
14569 uint64_t tw1_cmd_fifo_ram_sbe : 1;
14570 uint64_t pc_ram_sbe : 1;
14571 uint64_t rt_ram_sbe : 1;
14572 uint64_t sq_nt_ram_sbe : 1;
14573 uint64_t sq_pt_ram_sbe : 1;
14574 uint64_t vc0_sram_sbe : 1;
14575 uint64_t vc1_sram_sbe : 1;
14576 uint64_t cxd_ram_sbe : 1;
14577 uint64_t cxs_ram_sbe : 1;
14578 #endif
14579 } s;
14580 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_cn73xx {
14581 #ifdef __BIG_ENDIAN_BITFIELD
14582 uint64_t cxs_ram_sbe : 1;
14583 uint64_t cxd_ram_sbe : 1;
14584 uint64_t reserved_61_61 : 1;
14585 uint64_t vc0_sram_sbe : 1;
14586 uint64_t sq_pt_ram_sbe : 1;
14587 uint64_t sq_nt_ram_sbe : 1;
14588 uint64_t rt_ram_sbe : 1;
14589 uint64_t pc_ram_sbe : 1;
14590 uint64_t reserved_55_55 : 1;
14591 uint64_t tw0_cmd_fifo_ram_sbe : 1;
14592 uint64_t reserved_53_53 : 1;
14593 uint64_t tp0_sram_sbe : 1;
14594 uint64_t reserved_51_51 : 1;
14595 uint64_t sts0_ram_sbe : 1;
14596 uint64_t reserved_49_49 : 1;
14597 uint64_t std0_ram_sbe : 1;
14598 uint64_t wt_ram_sbe : 1;
14599 uint64_t sc_ram_sbe : 1;
14600 uint64_t reserved_0_45 : 46;
14601 #else
14602 uint64_t reserved_0_45 : 46;
14603 uint64_t sc_ram_sbe : 1;
14604 uint64_t wt_ram_sbe : 1;
14605 uint64_t std0_ram_sbe : 1;
14606 uint64_t reserved_49_49 : 1;
14607 uint64_t sts0_ram_sbe : 1;
14608 uint64_t reserved_51_51 : 1;
14609 uint64_t tp0_sram_sbe : 1;
14610 uint64_t reserved_53_53 : 1;
14611 uint64_t tw0_cmd_fifo_ram_sbe : 1;
14612 uint64_t reserved_55_55 : 1;
14613 uint64_t pc_ram_sbe : 1;
14614 uint64_t rt_ram_sbe : 1;
14615 uint64_t sq_nt_ram_sbe : 1;
14616 uint64_t sq_pt_ram_sbe : 1;
14617 uint64_t vc0_sram_sbe : 1;
14618 uint64_t reserved_61_61 : 1;
14619 uint64_t cxd_ram_sbe : 1;
14620 uint64_t cxs_ram_sbe : 1;
14621 #endif
14622 } cn73xx;
14623 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_s cn78xx;
14624 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_s cn78xxp1;
14625 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_cn73xx cnf75xx;
14626 };
14627 typedef union cvmx_pko_pse_sq1_ecc_sbe_sts0 cvmx_pko_pse_sq1_ecc_sbe_sts0_t;
14628
14629
14630
14631
14632 union cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0 {
14633 uint64_t u64;
14634 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s {
14635 #ifdef __BIG_ENDIAN_BITFIELD
14636 uint64_t pse_sq1_sbe_cmb0 : 1;
14637
14638
14639
14640 uint64_t reserved_0_62 : 63;
14641 #else
14642 uint64_t reserved_0_62 : 63;
14643 uint64_t pse_sq1_sbe_cmb0 : 1;
14644 #endif
14645 } s;
14646 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s cn73xx;
14647 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s cn78xx;
14648 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s cn78xxp1;
14649 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s cnf75xx;
14650 };
14651 typedef union cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_t;
14652
14653
14654
14655
14656
14657
14658
14659 union cvmx_pko_pse_sq2_bist_status {
14660 uint64_t u64;
14661 struct cvmx_pko_pse_sq2_bist_status_s {
14662 #ifdef __BIG_ENDIAN_BITFIELD
14663 uint64_t reserved_29_63 : 35;
14664 uint64_t sc_sram : 1;
14665 uint64_t reserved_21_27 : 7;
14666 uint64_t tp1_sram : 1;
14667 uint64_t tp0_sram : 1;
14668 uint64_t reserved_18_18 : 1;
14669 uint64_t rt_sram : 1;
14670 uint64_t reserved_9_16 : 8;
14671 uint64_t tw1_cmd_fifo : 1;
14672 uint64_t std_sram : 1;
14673 uint64_t sts_sram : 1;
14674 uint64_t tw0_cmd_fifo : 1;
14675 uint64_t reserved_3_4 : 2;
14676 uint64_t nt_sram : 1;
14677 uint64_t pt_sram : 1;
14678 uint64_t wt_sram : 1;
14679 #else
14680 uint64_t wt_sram : 1;
14681 uint64_t pt_sram : 1;
14682 uint64_t nt_sram : 1;
14683 uint64_t reserved_3_4 : 2;
14684 uint64_t tw0_cmd_fifo : 1;
14685 uint64_t sts_sram : 1;
14686 uint64_t std_sram : 1;
14687 uint64_t tw1_cmd_fifo : 1;
14688 uint64_t reserved_9_16 : 8;
14689 uint64_t rt_sram : 1;
14690 uint64_t reserved_18_18 : 1;
14691 uint64_t tp0_sram : 1;
14692 uint64_t tp1_sram : 1;
14693 uint64_t reserved_21_27 : 7;
14694 uint64_t sc_sram : 1;
14695 uint64_t reserved_29_63 : 35;
14696 #endif
14697 } s;
14698 struct cvmx_pko_pse_sq2_bist_status_cn73xx {
14699 #ifdef __BIG_ENDIAN_BITFIELD
14700 uint64_t reserved_29_63 : 35;
14701 uint64_t sc_sram : 1;
14702 uint64_t reserved_20_27 : 8;
14703 uint64_t tp0_sram : 1;
14704 uint64_t reserved_18_18 : 1;
14705 uint64_t rt_sram : 1;
14706 uint64_t reserved_8_16 : 9;
14707 uint64_t std_sram : 1;
14708 uint64_t sts_sram : 1;
14709 uint64_t tw0_cmd_fifo : 1;
14710 uint64_t reserved_3_4 : 2;
14711 uint64_t nt_sram : 1;
14712 uint64_t pt_sram : 1;
14713 uint64_t wt_sram : 1;
14714 #else
14715 uint64_t wt_sram : 1;
14716 uint64_t pt_sram : 1;
14717 uint64_t nt_sram : 1;
14718 uint64_t reserved_3_4 : 2;
14719 uint64_t tw0_cmd_fifo : 1;
14720 uint64_t sts_sram : 1;
14721 uint64_t std_sram : 1;
14722 uint64_t reserved_8_16 : 9;
14723 uint64_t rt_sram : 1;
14724 uint64_t reserved_18_18 : 1;
14725 uint64_t tp0_sram : 1;
14726 uint64_t reserved_20_27 : 8;
14727 uint64_t sc_sram : 1;
14728 uint64_t reserved_29_63 : 35;
14729 #endif
14730 } cn73xx;
14731 struct cvmx_pko_pse_sq2_bist_status_s cn78xx;
14732 struct cvmx_pko_pse_sq2_bist_status_s cn78xxp1;
14733 struct cvmx_pko_pse_sq2_bist_status_cn73xx cnf75xx;
14734 };
14735 typedef union cvmx_pko_pse_sq2_bist_status cvmx_pko_pse_sq2_bist_status_t;
14736
14737
14738
14739
14740 union cvmx_pko_pse_sq2_ecc_ctl0 {
14741 uint64_t u64;
14742 struct cvmx_pko_pse_sq2_ecc_ctl0_s {
14743 #ifdef __BIG_ENDIAN_BITFIELD
14744 uint64_t sq_pt_ram_flip : 2;
14745 uint64_t sq_pt_ram_cdis : 1;
14746 uint64_t sq_nt_ram_flip : 2;
14747 uint64_t sq_nt_ram_cdis : 1;
14748 uint64_t rt_ram_flip : 2;
14749 uint64_t rt_ram_cdis : 1;
14750 uint64_t tw1_cmd_fifo_ram_flip : 2;
14751 uint64_t tw1_cmd_fifo_ram_cdis : 1;
14752 uint64_t tw0_cmd_fifo_ram_flip : 2;
14753 uint64_t tw0_cmd_fifo_ram_cdis : 1;
14754 uint64_t tp1_sram_flip : 2;
14755 uint64_t tp1_sram_cdis : 1;
14756 uint64_t tp0_sram_flip : 2;
14757 uint64_t tp0_sram_cdis : 1;
14758 uint64_t sts1_ram_flip : 2;
14759 uint64_t sts1_ram_cdis : 1;
14760 uint64_t sts0_ram_flip : 2;
14761 uint64_t sts0_ram_cdis : 1;
14762 uint64_t std1_ram_flip : 2;
14763 uint64_t std1_ram_cdis : 1;
14764 uint64_t std0_ram_flip : 2;
14765 uint64_t std0_ram_cdis : 1;
14766 uint64_t wt_ram_flip : 2;
14767 uint64_t wt_ram_cdis : 1;
14768 uint64_t sc_ram_flip : 2;
14769 uint64_t sc_ram_cdis : 1;
14770 uint64_t reserved_0_24 : 25;
14771 #else
14772 uint64_t reserved_0_24 : 25;
14773 uint64_t sc_ram_cdis : 1;
14774 uint64_t sc_ram_flip : 2;
14775 uint64_t wt_ram_cdis : 1;
14776 uint64_t wt_ram_flip : 2;
14777 uint64_t std0_ram_cdis : 1;
14778 uint64_t std0_ram_flip : 2;
14779 uint64_t std1_ram_cdis : 1;
14780 uint64_t std1_ram_flip : 2;
14781 uint64_t sts0_ram_cdis : 1;
14782 uint64_t sts0_ram_flip : 2;
14783 uint64_t sts1_ram_cdis : 1;
14784 uint64_t sts1_ram_flip : 2;
14785 uint64_t tp0_sram_cdis : 1;
14786 uint64_t tp0_sram_flip : 2;
14787 uint64_t tp1_sram_cdis : 1;
14788 uint64_t tp1_sram_flip : 2;
14789 uint64_t tw0_cmd_fifo_ram_cdis : 1;
14790 uint64_t tw0_cmd_fifo_ram_flip : 2;
14791 uint64_t tw1_cmd_fifo_ram_cdis : 1;
14792 uint64_t tw1_cmd_fifo_ram_flip : 2;
14793 uint64_t rt_ram_cdis : 1;
14794 uint64_t rt_ram_flip : 2;
14795 uint64_t sq_nt_ram_cdis : 1;
14796 uint64_t sq_nt_ram_flip : 2;
14797 uint64_t sq_pt_ram_cdis : 1;
14798 uint64_t sq_pt_ram_flip : 2;
14799 #endif
14800 } s;
14801 struct cvmx_pko_pse_sq2_ecc_ctl0_cn73xx {
14802 #ifdef __BIG_ENDIAN_BITFIELD
14803 uint64_t sq_pt_ram_flip : 2;
14804 uint64_t sq_pt_ram_cdis : 1;
14805 uint64_t sq_nt_ram_flip : 2;
14806 uint64_t sq_nt_ram_cdis : 1;
14807 uint64_t rt_ram_flip : 2;
14808 uint64_t rt_ram_cdis : 1;
14809 uint64_t reserved_52_54 : 3;
14810 uint64_t tw0_cmd_fifo_ram_flip : 2;
14811 uint64_t tw0_cmd_fifo_ram_cdis : 1;
14812 uint64_t reserved_46_48 : 3;
14813 uint64_t tp0_sram_flip : 2;
14814 uint64_t tp0_sram_cdis : 1;
14815 uint64_t reserved_40_42 : 3;
14816 uint64_t sts0_ram_flip : 2;
14817 uint64_t sts0_ram_cdis : 1;
14818 uint64_t reserved_34_36 : 3;
14819 uint64_t std0_ram_flip : 2;
14820 uint64_t std0_ram_cdis : 1;
14821 uint64_t wt_ram_flip : 2;
14822 uint64_t wt_ram_cdis : 1;
14823 uint64_t sc_ram_flip : 2;
14824 uint64_t sc_ram_cdis : 1;
14825 uint64_t reserved_0_24 : 25;
14826 #else
14827 uint64_t reserved_0_24 : 25;
14828 uint64_t sc_ram_cdis : 1;
14829 uint64_t sc_ram_flip : 2;
14830 uint64_t wt_ram_cdis : 1;
14831 uint64_t wt_ram_flip : 2;
14832 uint64_t std0_ram_cdis : 1;
14833 uint64_t std0_ram_flip : 2;
14834 uint64_t reserved_34_36 : 3;
14835 uint64_t sts0_ram_cdis : 1;
14836 uint64_t sts0_ram_flip : 2;
14837 uint64_t reserved_40_42 : 3;
14838 uint64_t tp0_sram_cdis : 1;
14839 uint64_t tp0_sram_flip : 2;
14840 uint64_t reserved_46_48 : 3;
14841 uint64_t tw0_cmd_fifo_ram_cdis : 1;
14842 uint64_t tw0_cmd_fifo_ram_flip : 2;
14843 uint64_t reserved_52_54 : 3;
14844 uint64_t rt_ram_cdis : 1;
14845 uint64_t rt_ram_flip : 2;
14846 uint64_t sq_nt_ram_cdis : 1;
14847 uint64_t sq_nt_ram_flip : 2;
14848 uint64_t sq_pt_ram_cdis : 1;
14849 uint64_t sq_pt_ram_flip : 2;
14850 #endif
14851 } cn73xx;
14852 struct cvmx_pko_pse_sq2_ecc_ctl0_s cn78xx;
14853 struct cvmx_pko_pse_sq2_ecc_ctl0_s cn78xxp1;
14854 struct cvmx_pko_pse_sq2_ecc_ctl0_cn73xx cnf75xx;
14855 };
14856 typedef union cvmx_pko_pse_sq2_ecc_ctl0 cvmx_pko_pse_sq2_ecc_ctl0_t;
14857
14858
14859
14860
14861 union cvmx_pko_pse_sq2_ecc_dbe_sts0 {
14862 uint64_t u64;
14863 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_s {
14864 #ifdef __BIG_ENDIAN_BITFIELD
14865 uint64_t sq_pt_ram_dbe : 1;
14866 uint64_t sq_nt_ram_dbe : 1;
14867 uint64_t rt_ram_dbe : 1;
14868 uint64_t tw1_cmd_fifo_ram_dbe : 1;
14869 uint64_t tw0_cmd_fifo_ram_dbe : 1;
14870 uint64_t tp1_sram_dbe : 1;
14871 uint64_t tp0_sram_dbe : 1;
14872 uint64_t sts1_ram_dbe : 1;
14873 uint64_t sts0_ram_dbe : 1;
14874 uint64_t std1_ram_dbe : 1;
14875 uint64_t std0_ram_dbe : 1;
14876 uint64_t wt_ram_dbe : 1;
14877 uint64_t sc_ram_dbe : 1;
14878 uint64_t reserved_0_50 : 51;
14879 #else
14880 uint64_t reserved_0_50 : 51;
14881 uint64_t sc_ram_dbe : 1;
14882 uint64_t wt_ram_dbe : 1;
14883 uint64_t std0_ram_dbe : 1;
14884 uint64_t std1_ram_dbe : 1;
14885 uint64_t sts0_ram_dbe : 1;
14886 uint64_t sts1_ram_dbe : 1;
14887 uint64_t tp0_sram_dbe : 1;
14888 uint64_t tp1_sram_dbe : 1;
14889 uint64_t tw0_cmd_fifo_ram_dbe : 1;
14890 uint64_t tw1_cmd_fifo_ram_dbe : 1;
14891 uint64_t rt_ram_dbe : 1;
14892 uint64_t sq_nt_ram_dbe : 1;
14893 uint64_t sq_pt_ram_dbe : 1;
14894 #endif
14895 } s;
14896 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_cn73xx {
14897 #ifdef __BIG_ENDIAN_BITFIELD
14898 uint64_t sq_pt_ram_dbe : 1;
14899 uint64_t sq_nt_ram_dbe : 1;
14900 uint64_t rt_ram_dbe : 1;
14901 uint64_t reserved_60_60 : 1;
14902 uint64_t tw0_cmd_fifo_ram_dbe : 1;
14903 uint64_t reserved_58_58 : 1;
14904 uint64_t tp0_sram_dbe : 1;
14905 uint64_t reserved_56_56 : 1;
14906 uint64_t sts0_ram_dbe : 1;
14907 uint64_t reserved_54_54 : 1;
14908 uint64_t std0_ram_dbe : 1;
14909 uint64_t wt_ram_dbe : 1;
14910 uint64_t sc_ram_dbe : 1;
14911 uint64_t reserved_0_50 : 51;
14912 #else
14913 uint64_t reserved_0_50 : 51;
14914 uint64_t sc_ram_dbe : 1;
14915 uint64_t wt_ram_dbe : 1;
14916 uint64_t std0_ram_dbe : 1;
14917 uint64_t reserved_54_54 : 1;
14918 uint64_t sts0_ram_dbe : 1;
14919 uint64_t reserved_56_56 : 1;
14920 uint64_t tp0_sram_dbe : 1;
14921 uint64_t reserved_58_58 : 1;
14922 uint64_t tw0_cmd_fifo_ram_dbe : 1;
14923 uint64_t reserved_60_60 : 1;
14924 uint64_t rt_ram_dbe : 1;
14925 uint64_t sq_nt_ram_dbe : 1;
14926 uint64_t sq_pt_ram_dbe : 1;
14927 #endif
14928 } cn73xx;
14929 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_s cn78xx;
14930 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_s cn78xxp1;
14931 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_cn73xx cnf75xx;
14932 };
14933 typedef union cvmx_pko_pse_sq2_ecc_dbe_sts0 cvmx_pko_pse_sq2_ecc_dbe_sts0_t;
14934
14935
14936
14937
14938 union cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0 {
14939 uint64_t u64;
14940 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s {
14941 #ifdef __BIG_ENDIAN_BITFIELD
14942 uint64_t pse_sq2_dbe_cmb0 : 1;
14943
14944
14945
14946 uint64_t reserved_0_62 : 63;
14947 #else
14948 uint64_t reserved_0_62 : 63;
14949 uint64_t pse_sq2_dbe_cmb0 : 1;
14950 #endif
14951 } s;
14952 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s cn73xx;
14953 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s cn78xx;
14954 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s cn78xxp1;
14955 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s cnf75xx;
14956 };
14957 typedef union cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_t;
14958
14959
14960
14961
14962 union cvmx_pko_pse_sq2_ecc_sbe_sts0 {
14963 uint64_t u64;
14964 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_s {
14965 #ifdef __BIG_ENDIAN_BITFIELD
14966 uint64_t sq_pt_ram_sbe : 1;
14967 uint64_t sq_nt_ram_sbe : 1;
14968 uint64_t rt_ram_sbe : 1;
14969 uint64_t tw1_cmd_fifo_ram_sbe : 1;
14970 uint64_t tw0_cmd_fifo_ram_sbe : 1;
14971 uint64_t tp1_sram_sbe : 1;
14972 uint64_t tp0_sram_sbe : 1;
14973 uint64_t sts1_ram_sbe : 1;
14974 uint64_t sts0_ram_sbe : 1;
14975 uint64_t std1_ram_sbe : 1;
14976 uint64_t std0_ram_sbe : 1;
14977 uint64_t wt_ram_sbe : 1;
14978 uint64_t sc_ram_sbe : 1;
14979 uint64_t reserved_0_50 : 51;
14980 #else
14981 uint64_t reserved_0_50 : 51;
14982 uint64_t sc_ram_sbe : 1;
14983 uint64_t wt_ram_sbe : 1;
14984 uint64_t std0_ram_sbe : 1;
14985 uint64_t std1_ram_sbe : 1;
14986 uint64_t sts0_ram_sbe : 1;
14987 uint64_t sts1_ram_sbe : 1;
14988 uint64_t tp0_sram_sbe : 1;
14989 uint64_t tp1_sram_sbe : 1;
14990 uint64_t tw0_cmd_fifo_ram_sbe : 1;
14991 uint64_t tw1_cmd_fifo_ram_sbe : 1;
14992 uint64_t rt_ram_sbe : 1;
14993 uint64_t sq_nt_ram_sbe : 1;
14994 uint64_t sq_pt_ram_sbe : 1;
14995 #endif
14996 } s;
14997 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_cn73xx {
14998 #ifdef __BIG_ENDIAN_BITFIELD
14999 uint64_t sq_pt_ram_sbe : 1;
15000 uint64_t sq_nt_ram_sbe : 1;
15001 uint64_t rt_ram_sbe : 1;
15002 uint64_t reserved_60_60 : 1;
15003 uint64_t tw0_cmd_fifo_ram_sbe : 1;
15004 uint64_t reserved_58_58 : 1;
15005 uint64_t tp0_sram_sbe : 1;
15006 uint64_t reserved_56_56 : 1;
15007 uint64_t sts0_ram_sbe : 1;
15008 uint64_t reserved_54_54 : 1;
15009 uint64_t std0_ram_sbe : 1;
15010 uint64_t wt_ram_sbe : 1;
15011 uint64_t sc_ram_sbe : 1;
15012 uint64_t reserved_0_50 : 51;
15013 #else
15014 uint64_t reserved_0_50 : 51;
15015 uint64_t sc_ram_sbe : 1;
15016 uint64_t wt_ram_sbe : 1;
15017 uint64_t std0_ram_sbe : 1;
15018 uint64_t reserved_54_54 : 1;
15019 uint64_t sts0_ram_sbe : 1;
15020 uint64_t reserved_56_56 : 1;
15021 uint64_t tp0_sram_sbe : 1;
15022 uint64_t reserved_58_58 : 1;
15023 uint64_t tw0_cmd_fifo_ram_sbe : 1;
15024 uint64_t reserved_60_60 : 1;
15025 uint64_t rt_ram_sbe : 1;
15026 uint64_t sq_nt_ram_sbe : 1;
15027 uint64_t sq_pt_ram_sbe : 1;
15028 #endif
15029 } cn73xx;
15030 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_s cn78xx;
15031 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_s cn78xxp1;
15032 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_cn73xx cnf75xx;
15033 };
15034 typedef union cvmx_pko_pse_sq2_ecc_sbe_sts0 cvmx_pko_pse_sq2_ecc_sbe_sts0_t;
15035
15036
15037
15038
15039 union cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0 {
15040 uint64_t u64;
15041 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s {
15042 #ifdef __BIG_ENDIAN_BITFIELD
15043 uint64_t pse_sq2_sbe_cmb0 : 1;
15044
15045
15046
15047 uint64_t reserved_0_62 : 63;
15048 #else
15049 uint64_t reserved_0_62 : 63;
15050 uint64_t pse_sq2_sbe_cmb0 : 1;
15051 #endif
15052 } s;
15053 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s cn73xx;
15054 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s cn78xx;
15055 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s cn78xxp1;
15056 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s cnf75xx;
15057 };
15058 typedef union cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_t;
15059
15060
15061
15062
15063
15064
15065
15066 union cvmx_pko_pse_sq3_bist_status {
15067 uint64_t u64;
15068 struct cvmx_pko_pse_sq3_bist_status_s {
15069 #ifdef __BIG_ENDIAN_BITFIELD
15070 uint64_t reserved_29_63 : 35;
15071 uint64_t sc_sram : 1;
15072 uint64_t reserved_23_27 : 5;
15073 uint64_t tp3_sram : 1;
15074 uint64_t tp2_sram : 1;
15075 uint64_t tp1_sram : 1;
15076 uint64_t tp0_sram : 1;
15077 uint64_t reserved_18_18 : 1;
15078 uint64_t rt_sram : 1;
15079 uint64_t reserved_15_16 : 2;
15080 uint64_t tw3_cmd_fifo : 1;
15081 uint64_t reserved_12_13 : 2;
15082 uint64_t tw2_cmd_fifo : 1;
15083 uint64_t reserved_9_10 : 2;
15084 uint64_t tw1_cmd_fifo : 1;
15085 uint64_t std_sram : 1;
15086 uint64_t sts_sram : 1;
15087 uint64_t tw0_cmd_fifo : 1;
15088 uint64_t reserved_3_4 : 2;
15089 uint64_t nt_sram : 1;
15090 uint64_t pt_sram : 1;
15091 uint64_t wt_sram : 1;
15092 #else
15093 uint64_t wt_sram : 1;
15094 uint64_t pt_sram : 1;
15095 uint64_t nt_sram : 1;
15096 uint64_t reserved_3_4 : 2;
15097 uint64_t tw0_cmd_fifo : 1;
15098 uint64_t sts_sram : 1;
15099 uint64_t std_sram : 1;
15100 uint64_t tw1_cmd_fifo : 1;
15101 uint64_t reserved_9_10 : 2;
15102 uint64_t tw2_cmd_fifo : 1;
15103 uint64_t reserved_12_13 : 2;
15104 uint64_t tw3_cmd_fifo : 1;
15105 uint64_t reserved_15_16 : 2;
15106 uint64_t rt_sram : 1;
15107 uint64_t reserved_18_18 : 1;
15108 uint64_t tp0_sram : 1;
15109 uint64_t tp1_sram : 1;
15110 uint64_t tp2_sram : 1;
15111 uint64_t tp3_sram : 1;
15112 uint64_t reserved_23_27 : 5;
15113 uint64_t sc_sram : 1;
15114 uint64_t reserved_29_63 : 35;
15115 #endif
15116 } s;
15117 struct cvmx_pko_pse_sq3_bist_status_cn73xx {
15118 #ifdef __BIG_ENDIAN_BITFIELD
15119 uint64_t reserved_29_63 : 35;
15120 uint64_t sc_sram : 1;
15121 uint64_t reserved_20_27 : 8;
15122 uint64_t tp0_sram : 1;
15123 uint64_t reserved_18_18 : 1;
15124 uint64_t rt_sram : 1;
15125 uint64_t reserved_8_16 : 9;
15126 uint64_t std_sram : 1;
15127 uint64_t sts_sram : 1;
15128 uint64_t tw0_cmd_fifo : 1;
15129 uint64_t reserved_3_4 : 2;
15130 uint64_t nt_sram : 1;
15131 uint64_t pt_sram : 1;
15132 uint64_t wt_sram : 1;
15133 #else
15134 uint64_t wt_sram : 1;
15135 uint64_t pt_sram : 1;
15136 uint64_t nt_sram : 1;
15137 uint64_t reserved_3_4 : 2;
15138 uint64_t tw0_cmd_fifo : 1;
15139 uint64_t sts_sram : 1;
15140 uint64_t std_sram : 1;
15141 uint64_t reserved_8_16 : 9;
15142 uint64_t rt_sram : 1;
15143 uint64_t reserved_18_18 : 1;
15144 uint64_t tp0_sram : 1;
15145 uint64_t reserved_20_27 : 8;
15146 uint64_t sc_sram : 1;
15147 uint64_t reserved_29_63 : 35;
15148 #endif
15149 } cn73xx;
15150 struct cvmx_pko_pse_sq3_bist_status_s cn78xx;
15151 struct cvmx_pko_pse_sq3_bist_status_s cn78xxp1;
15152 struct cvmx_pko_pse_sq3_bist_status_cn73xx cnf75xx;
15153 };
15154 typedef union cvmx_pko_pse_sq3_bist_status cvmx_pko_pse_sq3_bist_status_t;
15155
15156
15157
15158
15159 union cvmx_pko_pse_sq3_ecc_ctl0 {
15160 uint64_t u64;
15161 struct cvmx_pko_pse_sq3_ecc_ctl0_s {
15162 #ifdef __BIG_ENDIAN_BITFIELD
15163 uint64_t sq_pt_ram_flip : 2;
15164 uint64_t sq_pt_ram_cdis : 1;
15165 uint64_t sq_nt_ram_flip : 2;
15166 uint64_t sq_nt_ram_cdis : 1;
15167 uint64_t rt_ram_flip : 2;
15168 uint64_t rt_ram_cdis : 1;
15169 uint64_t tw3_cmd_fifo_ram_flip : 2;
15170 uint64_t tw3_cmd_fifo_ram_cdis : 1;
15171 uint64_t tw2_cmd_fifo_ram_flip : 2;
15172 uint64_t tw2_cmd_fifo_ram_cdis : 1;
15173 uint64_t tw1_cmd_fifo_ram_flip : 2;
15174 uint64_t tw1_cmd_fifo_ram_cdis : 1;
15175 uint64_t tw0_cmd_fifo_ram_flip : 2;
15176 uint64_t tw0_cmd_fifo_ram_cdis : 1;
15177 uint64_t tp3_sram_flip : 2;
15178 uint64_t tp3_sram_cdis : 1;
15179 uint64_t tp2_sram_flip : 2;
15180 uint64_t tp2_sram_cdis : 1;
15181 uint64_t tp1_sram_flip : 2;
15182 uint64_t tp1_sram_cdis : 1;
15183 uint64_t tp0_sram_flip : 2;
15184 uint64_t tp0_sram_cdis : 1;
15185 uint64_t sts3_ram_flip : 2;
15186 uint64_t sts3_ram_cdis : 1;
15187 uint64_t sts2_ram_flip : 2;
15188 uint64_t sts2_ram_cdis : 1;
15189 uint64_t sts1_ram_flip : 2;
15190 uint64_t sts1_ram_cdis : 1;
15191 uint64_t sts0_ram_flip : 2;
15192 uint64_t sts0_ram_cdis : 1;
15193 uint64_t std3_ram_flip : 2;
15194 uint64_t std3_ram_cdis : 1;
15195 uint64_t std2_ram_flip : 2;
15196 uint64_t std2_ram_cdis : 1;
15197 uint64_t std1_ram_flip : 2;
15198 uint64_t std1_ram_cdis : 1;
15199 uint64_t std0_ram_flip : 2;
15200 uint64_t std0_ram_cdis : 1;
15201 uint64_t wt_ram_flip : 2;
15202 uint64_t wt_ram_cdis : 1;
15203 uint64_t sc_ram_flip : 2;
15204 uint64_t sc_ram_cdis : 1;
15205 uint64_t reserved_0_0 : 1;
15206 #else
15207 uint64_t reserved_0_0 : 1;
15208 uint64_t sc_ram_cdis : 1;
15209 uint64_t sc_ram_flip : 2;
15210 uint64_t wt_ram_cdis : 1;
15211 uint64_t wt_ram_flip : 2;
15212 uint64_t std0_ram_cdis : 1;
15213 uint64_t std0_ram_flip : 2;
15214 uint64_t std1_ram_cdis : 1;
15215 uint64_t std1_ram_flip : 2;
15216 uint64_t std2_ram_cdis : 1;
15217 uint64_t std2_ram_flip : 2;
15218 uint64_t std3_ram_cdis : 1;
15219 uint64_t std3_ram_flip : 2;
15220 uint64_t sts0_ram_cdis : 1;
15221 uint64_t sts0_ram_flip : 2;
15222 uint64_t sts1_ram_cdis : 1;
15223 uint64_t sts1_ram_flip : 2;
15224 uint64_t sts2_ram_cdis : 1;
15225 uint64_t sts2_ram_flip : 2;
15226 uint64_t sts3_ram_cdis : 1;
15227 uint64_t sts3_ram_flip : 2;
15228 uint64_t tp0_sram_cdis : 1;
15229 uint64_t tp0_sram_flip : 2;
15230 uint64_t tp1_sram_cdis : 1;
15231 uint64_t tp1_sram_flip : 2;
15232 uint64_t tp2_sram_cdis : 1;
15233 uint64_t tp2_sram_flip : 2;
15234 uint64_t tp3_sram_cdis : 1;
15235 uint64_t tp3_sram_flip : 2;
15236 uint64_t tw0_cmd_fifo_ram_cdis : 1;
15237 uint64_t tw0_cmd_fifo_ram_flip : 2;
15238 uint64_t tw1_cmd_fifo_ram_cdis : 1;
15239 uint64_t tw1_cmd_fifo_ram_flip : 2;
15240 uint64_t tw2_cmd_fifo_ram_cdis : 1;
15241 uint64_t tw2_cmd_fifo_ram_flip : 2;
15242 uint64_t tw3_cmd_fifo_ram_cdis : 1;
15243 uint64_t tw3_cmd_fifo_ram_flip : 2;
15244 uint64_t rt_ram_cdis : 1;
15245 uint64_t rt_ram_flip : 2;
15246 uint64_t sq_nt_ram_cdis : 1;
15247 uint64_t sq_nt_ram_flip : 2;
15248 uint64_t sq_pt_ram_cdis : 1;
15249 uint64_t sq_pt_ram_flip : 2;
15250 #endif
15251 } s;
15252 struct cvmx_pko_pse_sq3_ecc_ctl0_cn73xx {
15253 #ifdef __BIG_ENDIAN_BITFIELD
15254 uint64_t sq_pt_ram_flip : 2;
15255 uint64_t sq_pt_ram_cdis : 1;
15256 uint64_t sq_nt_ram_flip : 2;
15257 uint64_t sq_nt_ram_cdis : 1;
15258 uint64_t rt_ram_flip : 2;
15259 uint64_t rt_ram_cdis : 1;
15260 uint64_t reserved_46_54 : 9;
15261 uint64_t tw0_cmd_fifo_ram_flip : 2;
15262 uint64_t tw0_cmd_fifo_ram_cdis : 1;
15263 uint64_t reserved_34_42 : 9;
15264 uint64_t tp0_sram_flip : 2;
15265 uint64_t tp0_sram_cdis : 1;
15266 uint64_t reserved_22_30 : 9;
15267 uint64_t sts0_ram_flip : 2;
15268 uint64_t sts0_ram_cdis : 1;
15269 uint64_t reserved_10_18 : 9;
15270 uint64_t std0_ram_flip : 2;
15271 uint64_t std0_ram_cdis : 1;
15272 uint64_t wt_ram_flip : 2;
15273 uint64_t wt_ram_cdis : 1;
15274 uint64_t sc_ram_flip : 2;
15275 uint64_t sc_ram_cdis : 1;
15276 uint64_t reserved_0_0 : 1;
15277 #else
15278 uint64_t reserved_0_0 : 1;
15279 uint64_t sc_ram_cdis : 1;
15280 uint64_t sc_ram_flip : 2;
15281 uint64_t wt_ram_cdis : 1;
15282 uint64_t wt_ram_flip : 2;
15283 uint64_t std0_ram_cdis : 1;
15284 uint64_t std0_ram_flip : 2;
15285 uint64_t reserved_10_18 : 9;
15286 uint64_t sts0_ram_cdis : 1;
15287 uint64_t sts0_ram_flip : 2;
15288 uint64_t reserved_22_30 : 9;
15289 uint64_t tp0_sram_cdis : 1;
15290 uint64_t tp0_sram_flip : 2;
15291 uint64_t reserved_34_42 : 9;
15292 uint64_t tw0_cmd_fifo_ram_cdis : 1;
15293 uint64_t tw0_cmd_fifo_ram_flip : 2;
15294 uint64_t reserved_46_54 : 9;
15295 uint64_t rt_ram_cdis : 1;
15296 uint64_t rt_ram_flip : 2;
15297 uint64_t sq_nt_ram_cdis : 1;
15298 uint64_t sq_nt_ram_flip : 2;
15299 uint64_t sq_pt_ram_cdis : 1;
15300 uint64_t sq_pt_ram_flip : 2;
15301 #endif
15302 } cn73xx;
15303 struct cvmx_pko_pse_sq3_ecc_ctl0_s cn78xx;
15304 struct cvmx_pko_pse_sq3_ecc_ctl0_s cn78xxp1;
15305 struct cvmx_pko_pse_sq3_ecc_ctl0_cn73xx cnf75xx;
15306 };
15307 typedef union cvmx_pko_pse_sq3_ecc_ctl0 cvmx_pko_pse_sq3_ecc_ctl0_t;
15308
15309
15310
15311
15312 union cvmx_pko_pse_sq3_ecc_dbe_sts0 {
15313 uint64_t u64;
15314 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_s {
15315 #ifdef __BIG_ENDIAN_BITFIELD
15316 uint64_t sq_pt_ram_dbe : 1;
15317 uint64_t sq_nt_ram_dbe : 1;
15318 uint64_t rt_ram_dbe : 1;
15319 uint64_t tw3_cmd_fifo_ram_dbe : 1;
15320 uint64_t tw2_cmd_fifo_ram_dbe : 1;
15321 uint64_t tw1_cmd_fifo_ram_dbe : 1;
15322 uint64_t tw0_cmd_fifo_ram_dbe : 1;
15323 uint64_t tp3_sram_dbe : 1;
15324 uint64_t tp2_sram_dbe : 1;
15325 uint64_t tp1_sram_dbe : 1;
15326 uint64_t tp0_sram_dbe : 1;
15327 uint64_t sts3_ram_dbe : 1;
15328 uint64_t sts2_ram_dbe : 1;
15329 uint64_t sts1_ram_dbe : 1;
15330 uint64_t sts0_ram_dbe : 1;
15331 uint64_t std3_ram_dbe : 1;
15332 uint64_t std2_ram_dbe : 1;
15333 uint64_t std1_ram_dbe : 1;
15334 uint64_t std0_ram_dbe : 1;
15335 uint64_t wt_ram_dbe : 1;
15336 uint64_t sc_ram_dbe : 1;
15337 uint64_t reserved_0_42 : 43;
15338 #else
15339 uint64_t reserved_0_42 : 43;
15340 uint64_t sc_ram_dbe : 1;
15341 uint64_t wt_ram_dbe : 1;
15342 uint64_t std0_ram_dbe : 1;
15343 uint64_t std1_ram_dbe : 1;
15344 uint64_t std2_ram_dbe : 1;
15345 uint64_t std3_ram_dbe : 1;
15346 uint64_t sts0_ram_dbe : 1;
15347 uint64_t sts1_ram_dbe : 1;
15348 uint64_t sts2_ram_dbe : 1;
15349 uint64_t sts3_ram_dbe : 1;
15350 uint64_t tp0_sram_dbe : 1;
15351 uint64_t tp1_sram_dbe : 1;
15352 uint64_t tp2_sram_dbe : 1;
15353 uint64_t tp3_sram_dbe : 1;
15354 uint64_t tw0_cmd_fifo_ram_dbe : 1;
15355 uint64_t tw1_cmd_fifo_ram_dbe : 1;
15356 uint64_t tw2_cmd_fifo_ram_dbe : 1;
15357 uint64_t tw3_cmd_fifo_ram_dbe : 1;
15358 uint64_t rt_ram_dbe : 1;
15359 uint64_t sq_nt_ram_dbe : 1;
15360 uint64_t sq_pt_ram_dbe : 1;
15361 #endif
15362 } s;
15363 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_cn73xx {
15364 #ifdef __BIG_ENDIAN_BITFIELD
15365 uint64_t sq_pt_ram_dbe : 1;
15366 uint64_t sq_nt_ram_dbe : 1;
15367 uint64_t rt_ram_dbe : 1;
15368 uint64_t reserved_58_60 : 3;
15369 uint64_t tw0_cmd_fifo_ram_dbe : 1;
15370 uint64_t reserved_54_56 : 3;
15371 uint64_t tp0_sram_dbe : 1;
15372 uint64_t reserved_50_52 : 3;
15373 uint64_t sts0_ram_dbe : 1;
15374 uint64_t reserved_46_48 : 3;
15375 uint64_t std0_ram_dbe : 1;
15376 uint64_t wt_ram_dbe : 1;
15377 uint64_t sc_ram_dbe : 1;
15378 uint64_t reserved_0_42 : 43;
15379 #else
15380 uint64_t reserved_0_42 : 43;
15381 uint64_t sc_ram_dbe : 1;
15382 uint64_t wt_ram_dbe : 1;
15383 uint64_t std0_ram_dbe : 1;
15384 uint64_t reserved_46_48 : 3;
15385 uint64_t sts0_ram_dbe : 1;
15386 uint64_t reserved_50_52 : 3;
15387 uint64_t tp0_sram_dbe : 1;
15388 uint64_t reserved_54_56 : 3;
15389 uint64_t tw0_cmd_fifo_ram_dbe : 1;
15390 uint64_t reserved_58_60 : 3;
15391 uint64_t rt_ram_dbe : 1;
15392 uint64_t sq_nt_ram_dbe : 1;
15393 uint64_t sq_pt_ram_dbe : 1;
15394 #endif
15395 } cn73xx;
15396 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_s cn78xx;
15397 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_s cn78xxp1;
15398 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_cn73xx cnf75xx;
15399 };
15400 typedef union cvmx_pko_pse_sq3_ecc_dbe_sts0 cvmx_pko_pse_sq3_ecc_dbe_sts0_t;
15401
15402
15403
15404
15405 union cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0 {
15406 uint64_t u64;
15407 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s {
15408 #ifdef __BIG_ENDIAN_BITFIELD
15409 uint64_t pse_sq3_dbe_cmb0 : 1;
15410
15411
15412
15413 uint64_t reserved_0_62 : 63;
15414 #else
15415 uint64_t reserved_0_62 : 63;
15416 uint64_t pse_sq3_dbe_cmb0 : 1;
15417 #endif
15418 } s;
15419 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s cn73xx;
15420 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s cn78xx;
15421 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s cn78xxp1;
15422 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s cnf75xx;
15423 };
15424 typedef union cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_t;
15425
15426
15427
15428
15429 union cvmx_pko_pse_sq3_ecc_sbe_sts0 {
15430 uint64_t u64;
15431 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_s {
15432 #ifdef __BIG_ENDIAN_BITFIELD
15433 uint64_t sq_pt_ram_sbe : 1;
15434 uint64_t sq_nt_ram_sbe : 1;
15435 uint64_t rt_ram_sbe : 1;
15436 uint64_t tw3_cmd_fifo_ram_sbe : 1;
15437 uint64_t tw2_cmd_fifo_ram_sbe : 1;
15438 uint64_t tw1_cmd_fifo_ram_sbe : 1;
15439 uint64_t tw0_cmd_fifo_ram_sbe : 1;
15440 uint64_t tp3_sram_sbe : 1;
15441 uint64_t tp2_sram_sbe : 1;
15442 uint64_t tp1_sram_sbe : 1;
15443 uint64_t tp0_sram_sbe : 1;
15444 uint64_t sts3_ram_sbe : 1;
15445 uint64_t sts2_ram_sbe : 1;
15446 uint64_t sts1_ram_sbe : 1;
15447 uint64_t sts0_ram_sbe : 1;
15448 uint64_t std3_ram_sbe : 1;
15449 uint64_t std2_ram_sbe : 1;
15450 uint64_t std1_ram_sbe : 1;
15451 uint64_t std0_ram_sbe : 1;
15452 uint64_t wt_ram_sbe : 1;
15453 uint64_t sc_ram_sbe : 1;
15454 uint64_t reserved_0_42 : 43;
15455 #else
15456 uint64_t reserved_0_42 : 43;
15457 uint64_t sc_ram_sbe : 1;
15458 uint64_t wt_ram_sbe : 1;
15459 uint64_t std0_ram_sbe : 1;
15460 uint64_t std1_ram_sbe : 1;
15461 uint64_t std2_ram_sbe : 1;
15462 uint64_t std3_ram_sbe : 1;
15463 uint64_t sts0_ram_sbe : 1;
15464 uint64_t sts1_ram_sbe : 1;
15465 uint64_t sts2_ram_sbe : 1;
15466 uint64_t sts3_ram_sbe : 1;
15467 uint64_t tp0_sram_sbe : 1;
15468 uint64_t tp1_sram_sbe : 1;
15469 uint64_t tp2_sram_sbe : 1;
15470 uint64_t tp3_sram_sbe : 1;
15471 uint64_t tw0_cmd_fifo_ram_sbe : 1;
15472 uint64_t tw1_cmd_fifo_ram_sbe : 1;
15473 uint64_t tw2_cmd_fifo_ram_sbe : 1;
15474 uint64_t tw3_cmd_fifo_ram_sbe : 1;
15475 uint64_t rt_ram_sbe : 1;
15476 uint64_t sq_nt_ram_sbe : 1;
15477 uint64_t sq_pt_ram_sbe : 1;
15478 #endif
15479 } s;
15480 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_cn73xx {
15481 #ifdef __BIG_ENDIAN_BITFIELD
15482 uint64_t sq_pt_ram_sbe : 1;
15483 uint64_t sq_nt_ram_sbe : 1;
15484 uint64_t rt_ram_sbe : 1;
15485 uint64_t reserved_58_60 : 3;
15486 uint64_t tw0_cmd_fifo_ram_sbe : 1;
15487 uint64_t reserved_54_56 : 3;
15488 uint64_t tp0_sram_sbe : 1;
15489 uint64_t reserved_50_52 : 3;
15490 uint64_t sts0_ram_sbe : 1;
15491 uint64_t reserved_46_48 : 3;
15492 uint64_t std0_ram_sbe : 1;
15493 uint64_t wt_ram_sbe : 1;
15494 uint64_t sc_ram_sbe : 1;
15495 uint64_t reserved_0_42 : 43;
15496 #else
15497 uint64_t reserved_0_42 : 43;
15498 uint64_t sc_ram_sbe : 1;
15499 uint64_t wt_ram_sbe : 1;
15500 uint64_t std0_ram_sbe : 1;
15501 uint64_t reserved_46_48 : 3;
15502 uint64_t sts0_ram_sbe : 1;
15503 uint64_t reserved_50_52 : 3;
15504 uint64_t tp0_sram_sbe : 1;
15505 uint64_t reserved_54_56 : 3;
15506 uint64_t tw0_cmd_fifo_ram_sbe : 1;
15507 uint64_t reserved_58_60 : 3;
15508 uint64_t rt_ram_sbe : 1;
15509 uint64_t sq_nt_ram_sbe : 1;
15510 uint64_t sq_pt_ram_sbe : 1;
15511 #endif
15512 } cn73xx;
15513 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_s cn78xx;
15514 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_s cn78xxp1;
15515 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_cn73xx cnf75xx;
15516 };
15517 typedef union cvmx_pko_pse_sq3_ecc_sbe_sts0 cvmx_pko_pse_sq3_ecc_sbe_sts0_t;
15518
15519
15520
15521
15522 union cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0 {
15523 uint64_t u64;
15524 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s {
15525 #ifdef __BIG_ENDIAN_BITFIELD
15526 uint64_t pse_sq3_sbe_cmb0 : 1;
15527
15528
15529
15530 uint64_t reserved_0_62 : 63;
15531 #else
15532 uint64_t reserved_0_62 : 63;
15533 uint64_t pse_sq3_sbe_cmb0 : 1;
15534 #endif
15535 } s;
15536 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s cn73xx;
15537 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s cn78xx;
15538 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s cn78xxp1;
15539 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s cnf75xx;
15540 };
15541 typedef union cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_t;
15542
15543
15544
15545
15546
15547
15548
15549 union cvmx_pko_pse_sq4_bist_status {
15550 uint64_t u64;
15551 struct cvmx_pko_pse_sq4_bist_status_s {
15552 #ifdef __BIG_ENDIAN_BITFIELD
15553 uint64_t reserved_29_63 : 35;
15554 uint64_t sc_sram : 1;
15555 uint64_t reserved_23_27 : 5;
15556 uint64_t tp3_sram : 1;
15557 uint64_t tp2_sram : 1;
15558 uint64_t tp1_sram : 1;
15559 uint64_t tp0_sram : 1;
15560 uint64_t reserved_18_18 : 1;
15561 uint64_t rt_sram : 1;
15562 uint64_t reserved_15_16 : 2;
15563 uint64_t tw3_cmd_fifo : 1;
15564 uint64_t reserved_12_13 : 2;
15565 uint64_t tw2_cmd_fifo : 1;
15566 uint64_t reserved_9_10 : 2;
15567 uint64_t tw1_cmd_fifo : 1;
15568 uint64_t std_sram : 1;
15569 uint64_t sts_sram : 1;
15570 uint64_t tw0_cmd_fifo : 1;
15571 uint64_t reserved_3_4 : 2;
15572 uint64_t nt_sram : 1;
15573 uint64_t pt_sram : 1;
15574 uint64_t wt_sram : 1;
15575 #else
15576 uint64_t wt_sram : 1;
15577 uint64_t pt_sram : 1;
15578 uint64_t nt_sram : 1;
15579 uint64_t reserved_3_4 : 2;
15580 uint64_t tw0_cmd_fifo : 1;
15581 uint64_t sts_sram : 1;
15582 uint64_t std_sram : 1;
15583 uint64_t tw1_cmd_fifo : 1;
15584 uint64_t reserved_9_10 : 2;
15585 uint64_t tw2_cmd_fifo : 1;
15586 uint64_t reserved_12_13 : 2;
15587 uint64_t tw3_cmd_fifo : 1;
15588 uint64_t reserved_15_16 : 2;
15589 uint64_t rt_sram : 1;
15590 uint64_t reserved_18_18 : 1;
15591 uint64_t tp0_sram : 1;
15592 uint64_t tp1_sram : 1;
15593 uint64_t tp2_sram : 1;
15594 uint64_t tp3_sram : 1;
15595 uint64_t reserved_23_27 : 5;
15596 uint64_t sc_sram : 1;
15597 uint64_t reserved_29_63 : 35;
15598 #endif
15599 } s;
15600 struct cvmx_pko_pse_sq4_bist_status_s cn78xx;
15601 struct cvmx_pko_pse_sq4_bist_status_s cn78xxp1;
15602 };
15603 typedef union cvmx_pko_pse_sq4_bist_status cvmx_pko_pse_sq4_bist_status_t;
15604
15605
15606
15607
15608 union cvmx_pko_pse_sq4_ecc_ctl0 {
15609 uint64_t u64;
15610 struct cvmx_pko_pse_sq4_ecc_ctl0_s {
15611 #ifdef __BIG_ENDIAN_BITFIELD
15612 uint64_t sq_pt_ram_flip : 2;
15613 uint64_t sq_pt_ram_cdis : 1;
15614 uint64_t sq_nt_ram_flip : 2;
15615 uint64_t sq_nt_ram_cdis : 1;
15616 uint64_t rt_ram_flip : 2;
15617 uint64_t rt_ram_cdis : 1;
15618 uint64_t tw3_cmd_fifo_ram_flip : 2;
15619 uint64_t tw3_cmd_fifo_ram_cdis : 1;
15620 uint64_t tw2_cmd_fifo_ram_flip : 2;
15621 uint64_t tw2_cmd_fifo_ram_cdis : 1;
15622 uint64_t tw1_cmd_fifo_ram_flip : 2;
15623 uint64_t tw1_cmd_fifo_ram_cdis : 1;
15624 uint64_t tw0_cmd_fifo_ram_flip : 2;
15625 uint64_t tw0_cmd_fifo_ram_cdis : 1;
15626 uint64_t tp3_sram_flip : 2;
15627 uint64_t tp3_sram_cdis : 1;
15628 uint64_t tp2_sram_flip : 2;
15629 uint64_t tp2_sram_cdis : 1;
15630 uint64_t tp1_sram_flip : 2;
15631 uint64_t tp1_sram_cdis : 1;
15632 uint64_t tp0_sram_flip : 2;
15633 uint64_t tp0_sram_cdis : 1;
15634 uint64_t sts3_ram_flip : 2;
15635 uint64_t sts3_ram_cdis : 1;
15636 uint64_t sts2_ram_flip : 2;
15637 uint64_t sts2_ram_cdis : 1;
15638 uint64_t sts1_ram_flip : 2;
15639 uint64_t sts1_ram_cdis : 1;
15640 uint64_t sts0_ram_flip : 2;
15641 uint64_t sts0_ram_cdis : 1;
15642 uint64_t std3_ram_flip : 2;
15643 uint64_t std3_ram_cdis : 1;
15644 uint64_t std2_ram_flip : 2;
15645 uint64_t std2_ram_cdis : 1;
15646 uint64_t std1_ram_flip : 2;
15647 uint64_t std1_ram_cdis : 1;
15648 uint64_t std0_ram_flip : 2;
15649 uint64_t std0_ram_cdis : 1;
15650 uint64_t wt_ram_flip : 2;
15651 uint64_t wt_ram_cdis : 1;
15652 uint64_t sc_ram_flip : 2;
15653 uint64_t sc_ram_cdis : 1;
15654 uint64_t reserved_0_0 : 1;
15655 #else
15656 uint64_t reserved_0_0 : 1;
15657 uint64_t sc_ram_cdis : 1;
15658 uint64_t sc_ram_flip : 2;
15659 uint64_t wt_ram_cdis : 1;
15660 uint64_t wt_ram_flip : 2;
15661 uint64_t std0_ram_cdis : 1;
15662 uint64_t std0_ram_flip : 2;
15663 uint64_t std1_ram_cdis : 1;
15664 uint64_t std1_ram_flip : 2;
15665 uint64_t std2_ram_cdis : 1;
15666 uint64_t std2_ram_flip : 2;
15667 uint64_t std3_ram_cdis : 1;
15668 uint64_t std3_ram_flip : 2;
15669 uint64_t sts0_ram_cdis : 1;
15670 uint64_t sts0_ram_flip : 2;
15671 uint64_t sts1_ram_cdis : 1;
15672 uint64_t sts1_ram_flip : 2;
15673 uint64_t sts2_ram_cdis : 1;
15674 uint64_t sts2_ram_flip : 2;
15675 uint64_t sts3_ram_cdis : 1;
15676 uint64_t sts3_ram_flip : 2;
15677 uint64_t tp0_sram_cdis : 1;
15678 uint64_t tp0_sram_flip : 2;
15679 uint64_t tp1_sram_cdis : 1;
15680 uint64_t tp1_sram_flip : 2;
15681 uint64_t tp2_sram_cdis : 1;
15682 uint64_t tp2_sram_flip : 2;
15683 uint64_t tp3_sram_cdis : 1;
15684 uint64_t tp3_sram_flip : 2;
15685 uint64_t tw0_cmd_fifo_ram_cdis : 1;
15686 uint64_t tw0_cmd_fifo_ram_flip : 2;
15687 uint64_t tw1_cmd_fifo_ram_cdis : 1;
15688 uint64_t tw1_cmd_fifo_ram_flip : 2;
15689 uint64_t tw2_cmd_fifo_ram_cdis : 1;
15690 uint64_t tw2_cmd_fifo_ram_flip : 2;
15691 uint64_t tw3_cmd_fifo_ram_cdis : 1;
15692 uint64_t tw3_cmd_fifo_ram_flip : 2;
15693 uint64_t rt_ram_cdis : 1;
15694 uint64_t rt_ram_flip : 2;
15695 uint64_t sq_nt_ram_cdis : 1;
15696 uint64_t sq_nt_ram_flip : 2;
15697 uint64_t sq_pt_ram_cdis : 1;
15698 uint64_t sq_pt_ram_flip : 2;
15699 #endif
15700 } s;
15701 struct cvmx_pko_pse_sq4_ecc_ctl0_s cn78xx;
15702 struct cvmx_pko_pse_sq4_ecc_ctl0_s cn78xxp1;
15703 };
15704 typedef union cvmx_pko_pse_sq4_ecc_ctl0 cvmx_pko_pse_sq4_ecc_ctl0_t;
15705
15706
15707
15708
15709 union cvmx_pko_pse_sq4_ecc_dbe_sts0 {
15710 uint64_t u64;
15711 struct cvmx_pko_pse_sq4_ecc_dbe_sts0_s {
15712 #ifdef __BIG_ENDIAN_BITFIELD
15713 uint64_t sq_pt_ram_dbe : 1;
15714 uint64_t sq_nt_ram_dbe : 1;
15715 uint64_t rt_ram_dbe : 1;
15716 uint64_t tw3_cmd_fifo_ram_dbe : 1;
15717 uint64_t tw2_cmd_fifo_ram_dbe : 1;
15718 uint64_t tw1_cmd_fifo_ram_dbe : 1;
15719 uint64_t tw0_cmd_fifo_ram_dbe : 1;
15720 uint64_t tp3_sram_dbe : 1;
15721 uint64_t tp2_sram_dbe : 1;
15722 uint64_t tp1_sram_dbe : 1;
15723 uint64_t tp0_sram_dbe : 1;
15724 uint64_t sts3_ram_dbe : 1;
15725 uint64_t sts2_ram_dbe : 1;
15726 uint64_t sts1_ram_dbe : 1;
15727 uint64_t sts0_ram_dbe : 1;
15728 uint64_t std3_ram_dbe : 1;
15729 uint64_t std2_ram_dbe : 1;
15730 uint64_t std1_ram_dbe : 1;
15731 uint64_t std0_ram_dbe : 1;
15732 uint64_t wt_ram_dbe : 1;
15733 uint64_t sc_ram_dbe : 1;
15734 uint64_t reserved_0_42 : 43;
15735 #else
15736 uint64_t reserved_0_42 : 43;
15737 uint64_t sc_ram_dbe : 1;
15738 uint64_t wt_ram_dbe : 1;
15739 uint64_t std0_ram_dbe : 1;
15740 uint64_t std1_ram_dbe : 1;
15741 uint64_t std2_ram_dbe : 1;
15742 uint64_t std3_ram_dbe : 1;
15743 uint64_t sts0_ram_dbe : 1;
15744 uint64_t sts1_ram_dbe : 1;
15745 uint64_t sts2_ram_dbe : 1;
15746 uint64_t sts3_ram_dbe : 1;
15747 uint64_t tp0_sram_dbe : 1;
15748 uint64_t tp1_sram_dbe : 1;
15749 uint64_t tp2_sram_dbe : 1;
15750 uint64_t tp3_sram_dbe : 1;
15751 uint64_t tw0_cmd_fifo_ram_dbe : 1;
15752 uint64_t tw1_cmd_fifo_ram_dbe : 1;
15753 uint64_t tw2_cmd_fifo_ram_dbe : 1;
15754 uint64_t tw3_cmd_fifo_ram_dbe : 1;
15755 uint64_t rt_ram_dbe : 1;
15756 uint64_t sq_nt_ram_dbe : 1;
15757 uint64_t sq_pt_ram_dbe : 1;
15758 #endif
15759 } s;
15760 struct cvmx_pko_pse_sq4_ecc_dbe_sts0_s cn78xx;
15761 struct cvmx_pko_pse_sq4_ecc_dbe_sts0_s cn78xxp1;
15762 };
15763 typedef union cvmx_pko_pse_sq4_ecc_dbe_sts0 cvmx_pko_pse_sq4_ecc_dbe_sts0_t;
15764
15765
15766
15767
15768 union cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0 {
15769 uint64_t u64;
15770 struct cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0_s {
15771 #ifdef __BIG_ENDIAN_BITFIELD
15772 uint64_t pse_sq4_dbe_cmb0 : 1;
15773
15774
15775
15776 uint64_t reserved_0_62 : 63;
15777 #else
15778 uint64_t reserved_0_62 : 63;
15779 uint64_t pse_sq4_dbe_cmb0 : 1;
15780 #endif
15781 } s;
15782 struct cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0_s cn78xx;
15783 struct cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0_s cn78xxp1;
15784 };
15785 typedef union cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0_t;
15786
15787
15788
15789
15790 union cvmx_pko_pse_sq4_ecc_sbe_sts0 {
15791 uint64_t u64;
15792 struct cvmx_pko_pse_sq4_ecc_sbe_sts0_s {
15793 #ifdef __BIG_ENDIAN_BITFIELD
15794 uint64_t sq_pt_ram_sbe : 1;
15795 uint64_t sq_nt_ram_sbe : 1;
15796 uint64_t rt_ram_sbe : 1;
15797 uint64_t tw3_cmd_fifo_ram_sbe : 1;
15798 uint64_t tw2_cmd_fifo_ram_sbe : 1;
15799 uint64_t tw1_cmd_fifo_ram_sbe : 1;
15800 uint64_t tw0_cmd_fifo_ram_sbe : 1;
15801 uint64_t tp3_sram_sbe : 1;
15802 uint64_t tp2_sram_sbe : 1;
15803 uint64_t tp1_sram_sbe : 1;
15804 uint64_t tp0_sram_sbe : 1;
15805 uint64_t sts3_ram_sbe : 1;
15806 uint64_t sts2_ram_sbe : 1;
15807 uint64_t sts1_ram_sbe : 1;
15808 uint64_t sts0_ram_sbe : 1;
15809 uint64_t std3_ram_sbe : 1;
15810 uint64_t std2_ram_sbe : 1;
15811 uint64_t std1_ram_sbe : 1;
15812 uint64_t std0_ram_sbe : 1;
15813 uint64_t wt_ram_sbe : 1;
15814 uint64_t sc_ram_sbe : 1;
15815 uint64_t reserved_0_42 : 43;
15816 #else
15817 uint64_t reserved_0_42 : 43;
15818 uint64_t sc_ram_sbe : 1;
15819 uint64_t wt_ram_sbe : 1;
15820 uint64_t std0_ram_sbe : 1;
15821 uint64_t std1_ram_sbe : 1;
15822 uint64_t std2_ram_sbe : 1;
15823 uint64_t std3_ram_sbe : 1;
15824 uint64_t sts0_ram_sbe : 1;
15825 uint64_t sts1_ram_sbe : 1;
15826 uint64_t sts2_ram_sbe : 1;
15827 uint64_t sts3_ram_sbe : 1;
15828 uint64_t tp0_sram_sbe : 1;
15829 uint64_t tp1_sram_sbe : 1;
15830 uint64_t tp2_sram_sbe : 1;
15831 uint64_t tp3_sram_sbe : 1;
15832 uint64_t tw0_cmd_fifo_ram_sbe : 1;
15833 uint64_t tw1_cmd_fifo_ram_sbe : 1;
15834 uint64_t tw2_cmd_fifo_ram_sbe : 1;
15835 uint64_t tw3_cmd_fifo_ram_sbe : 1;
15836 uint64_t rt_ram_sbe : 1;
15837 uint64_t sq_nt_ram_sbe : 1;
15838 uint64_t sq_pt_ram_sbe : 1;
15839 #endif
15840 } s;
15841 struct cvmx_pko_pse_sq4_ecc_sbe_sts0_s cn78xx;
15842 struct cvmx_pko_pse_sq4_ecc_sbe_sts0_s cn78xxp1;
15843 };
15844 typedef union cvmx_pko_pse_sq4_ecc_sbe_sts0 cvmx_pko_pse_sq4_ecc_sbe_sts0_t;
15845
15846
15847
15848
15849 union cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0 {
15850 uint64_t u64;
15851 struct cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0_s {
15852 #ifdef __BIG_ENDIAN_BITFIELD
15853 uint64_t pse_sq4_sbe_cmb0 : 1;
15854
15855
15856
15857 uint64_t reserved_0_62 : 63;
15858 #else
15859 uint64_t reserved_0_62 : 63;
15860 uint64_t pse_sq4_sbe_cmb0 : 1;
15861 #endif
15862 } s;
15863 struct cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0_s cn78xx;
15864 struct cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0_s cn78xxp1;
15865 };
15866 typedef union cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0_t;
15867
15868
15869
15870
15871
15872
15873
15874 union cvmx_pko_pse_sq5_bist_status {
15875 uint64_t u64;
15876 struct cvmx_pko_pse_sq5_bist_status_s {
15877 #ifdef __BIG_ENDIAN_BITFIELD
15878 uint64_t reserved_29_63 : 35;
15879 uint64_t sc_sram : 1;
15880 uint64_t reserved_23_27 : 5;
15881 uint64_t tp3_sram : 1;
15882 uint64_t tp2_sram : 1;
15883 uint64_t tp1_sram : 1;
15884 uint64_t tp0_sram : 1;
15885 uint64_t reserved_18_18 : 1;
15886 uint64_t rt_sram : 1;
15887 uint64_t reserved_15_16 : 2;
15888 uint64_t tw3_cmd_fifo : 1;
15889 uint64_t reserved_12_13 : 2;
15890 uint64_t tw2_cmd_fifo : 1;
15891 uint64_t reserved_9_10 : 2;
15892 uint64_t tw1_cmd_fifo : 1;
15893 uint64_t std_sram : 1;
15894 uint64_t sts_sram : 1;
15895 uint64_t tw0_cmd_fifo : 1;
15896 uint64_t reserved_3_4 : 2;
15897 uint64_t nt_sram : 1;
15898 uint64_t pt_sram : 1;
15899 uint64_t wt_sram : 1;
15900 #else
15901 uint64_t wt_sram : 1;
15902 uint64_t pt_sram : 1;
15903 uint64_t nt_sram : 1;
15904 uint64_t reserved_3_4 : 2;
15905 uint64_t tw0_cmd_fifo : 1;
15906 uint64_t sts_sram : 1;
15907 uint64_t std_sram : 1;
15908 uint64_t tw1_cmd_fifo : 1;
15909 uint64_t reserved_9_10 : 2;
15910 uint64_t tw2_cmd_fifo : 1;
15911 uint64_t reserved_12_13 : 2;
15912 uint64_t tw3_cmd_fifo : 1;
15913 uint64_t reserved_15_16 : 2;
15914 uint64_t rt_sram : 1;
15915 uint64_t reserved_18_18 : 1;
15916 uint64_t tp0_sram : 1;
15917 uint64_t tp1_sram : 1;
15918 uint64_t tp2_sram : 1;
15919 uint64_t tp3_sram : 1;
15920 uint64_t reserved_23_27 : 5;
15921 uint64_t sc_sram : 1;
15922 uint64_t reserved_29_63 : 35;
15923 #endif
15924 } s;
15925 struct cvmx_pko_pse_sq5_bist_status_s cn78xx;
15926 struct cvmx_pko_pse_sq5_bist_status_s cn78xxp1;
15927 };
15928 typedef union cvmx_pko_pse_sq5_bist_status cvmx_pko_pse_sq5_bist_status_t;
15929
15930
15931
15932
15933 union cvmx_pko_pse_sq5_ecc_ctl0 {
15934 uint64_t u64;
15935 struct cvmx_pko_pse_sq5_ecc_ctl0_s {
15936 #ifdef __BIG_ENDIAN_BITFIELD
15937 uint64_t sq_pt_ram_flip : 2;
15938 uint64_t sq_pt_ram_cdis : 1;
15939 uint64_t sq_nt_ram_flip : 2;
15940 uint64_t sq_nt_ram_cdis : 1;
15941 uint64_t rt_ram_flip : 2;
15942 uint64_t rt_ram_cdis : 1;
15943 uint64_t tw3_cmd_fifo_ram_flip : 2;
15944 uint64_t tw3_cmd_fifo_ram_cdis : 1;
15945 uint64_t tw2_cmd_fifo_ram_flip : 2;
15946 uint64_t tw2_cmd_fifo_ram_cdis : 1;
15947 uint64_t tw1_cmd_fifo_ram_flip : 2;
15948 uint64_t tw1_cmd_fifo_ram_cdis : 1;
15949 uint64_t tw0_cmd_fifo_ram_flip : 2;
15950 uint64_t tw0_cmd_fifo_ram_cdis : 1;
15951 uint64_t tp3_sram_flip : 2;
15952 uint64_t tp3_sram_cdis : 1;
15953 uint64_t tp2_sram_flip : 2;
15954 uint64_t tp2_sram_cdis : 1;
15955 uint64_t tp1_sram_flip : 2;
15956 uint64_t tp1_sram_cdis : 1;
15957 uint64_t tp0_sram_flip : 2;
15958 uint64_t tp0_sram_cdis : 1;
15959 uint64_t sts3_ram_flip : 2;
15960 uint64_t sts3_ram_cdis : 1;
15961 uint64_t sts2_ram_flip : 2;
15962 uint64_t sts2_ram_cdis : 1;
15963 uint64_t sts1_ram_flip : 2;
15964 uint64_t sts1_ram_cdis : 1;
15965 uint64_t sts0_ram_flip : 2;
15966 uint64_t sts0_ram_cdis : 1;
15967 uint64_t std3_ram_flip : 2;
15968 uint64_t std3_ram_cdis : 1;
15969 uint64_t std2_ram_flip : 2;
15970 uint64_t std2_ram_cdis : 1;
15971 uint64_t std1_ram_flip : 2;
15972 uint64_t std1_ram_cdis : 1;
15973 uint64_t std0_ram_flip : 2;
15974 uint64_t std0_ram_cdis : 1;
15975 uint64_t wt_ram_flip : 2;
15976 uint64_t wt_ram_cdis : 1;
15977 uint64_t sc_ram_flip : 2;
15978 uint64_t sc_ram_cdis : 1;
15979 uint64_t reserved_0_0 : 1;
15980 #else
15981 uint64_t reserved_0_0 : 1;
15982 uint64_t sc_ram_cdis : 1;
15983 uint64_t sc_ram_flip : 2;
15984 uint64_t wt_ram_cdis : 1;
15985 uint64_t wt_ram_flip : 2;
15986 uint64_t std0_ram_cdis : 1;
15987 uint64_t std0_ram_flip : 2;
15988 uint64_t std1_ram_cdis : 1;
15989 uint64_t std1_ram_flip : 2;
15990 uint64_t std2_ram_cdis : 1;
15991 uint64_t std2_ram_flip : 2;
15992 uint64_t std3_ram_cdis : 1;
15993 uint64_t std3_ram_flip : 2;
15994 uint64_t sts0_ram_cdis : 1;
15995 uint64_t sts0_ram_flip : 2;
15996 uint64_t sts1_ram_cdis : 1;
15997 uint64_t sts1_ram_flip : 2;
15998 uint64_t sts2_ram_cdis : 1;
15999 uint64_t sts2_ram_flip : 2;
16000 uint64_t sts3_ram_cdis : 1;
16001 uint64_t sts3_ram_flip : 2;
16002 uint64_t tp0_sram_cdis : 1;
16003 uint64_t tp0_sram_flip : 2;
16004 uint64_t tp1_sram_cdis : 1;
16005 uint64_t tp1_sram_flip : 2;
16006 uint64_t tp2_sram_cdis : 1;
16007 uint64_t tp2_sram_flip : 2;
16008 uint64_t tp3_sram_cdis : 1;
16009 uint64_t tp3_sram_flip : 2;
16010 uint64_t tw0_cmd_fifo_ram_cdis : 1;
16011 uint64_t tw0_cmd_fifo_ram_flip : 2;
16012 uint64_t tw1_cmd_fifo_ram_cdis : 1;
16013 uint64_t tw1_cmd_fifo_ram_flip : 2;
16014 uint64_t tw2_cmd_fifo_ram_cdis : 1;
16015 uint64_t tw2_cmd_fifo_ram_flip : 2;
16016 uint64_t tw3_cmd_fifo_ram_cdis : 1;
16017 uint64_t tw3_cmd_fifo_ram_flip : 2;
16018 uint64_t rt_ram_cdis : 1;
16019 uint64_t rt_ram_flip : 2;
16020 uint64_t sq_nt_ram_cdis : 1;
16021 uint64_t sq_nt_ram_flip : 2;
16022 uint64_t sq_pt_ram_cdis : 1;
16023 uint64_t sq_pt_ram_flip : 2;
16024 #endif
16025 } s;
16026 struct cvmx_pko_pse_sq5_ecc_ctl0_s cn78xx;
16027 struct cvmx_pko_pse_sq5_ecc_ctl0_s cn78xxp1;
16028 };
16029 typedef union cvmx_pko_pse_sq5_ecc_ctl0 cvmx_pko_pse_sq5_ecc_ctl0_t;
16030
16031
16032
16033
16034 union cvmx_pko_pse_sq5_ecc_dbe_sts0 {
16035 uint64_t u64;
16036 struct cvmx_pko_pse_sq5_ecc_dbe_sts0_s {
16037 #ifdef __BIG_ENDIAN_BITFIELD
16038 uint64_t sq_pt_ram_dbe : 1;
16039 uint64_t sq_nt_ram_dbe : 1;
16040 uint64_t rt_ram_dbe : 1;
16041 uint64_t tw3_cmd_fifo_ram_dbe : 1;
16042 uint64_t tw2_cmd_fifo_ram_dbe : 1;
16043 uint64_t tw1_cmd_fifo_ram_dbe : 1;
16044 uint64_t tw0_cmd_fifo_ram_dbe : 1;
16045 uint64_t tp3_sram_dbe : 1;
16046 uint64_t tp2_sram_dbe : 1;
16047 uint64_t tp1_sram_dbe : 1;
16048 uint64_t tp0_sram_dbe : 1;
16049 uint64_t sts3_ram_dbe : 1;
16050 uint64_t sts2_ram_dbe : 1;
16051 uint64_t sts1_ram_dbe : 1;
16052 uint64_t sts0_ram_dbe : 1;
16053 uint64_t std3_ram_dbe : 1;
16054 uint64_t std2_ram_dbe : 1;
16055 uint64_t std1_ram_dbe : 1;
16056 uint64_t std0_ram_dbe : 1;
16057 uint64_t wt_ram_dbe : 1;
16058 uint64_t sc_ram_dbe : 1;
16059 uint64_t reserved_0_42 : 43;
16060 #else
16061 uint64_t reserved_0_42 : 43;
16062 uint64_t sc_ram_dbe : 1;
16063 uint64_t wt_ram_dbe : 1;
16064 uint64_t std0_ram_dbe : 1;
16065 uint64_t std1_ram_dbe : 1;
16066 uint64_t std2_ram_dbe : 1;
16067 uint64_t std3_ram_dbe : 1;
16068 uint64_t sts0_ram_dbe : 1;
16069 uint64_t sts1_ram_dbe : 1;
16070 uint64_t sts2_ram_dbe : 1;
16071 uint64_t sts3_ram_dbe : 1;
16072 uint64_t tp0_sram_dbe : 1;
16073 uint64_t tp1_sram_dbe : 1;
16074 uint64_t tp2_sram_dbe : 1;
16075 uint64_t tp3_sram_dbe : 1;
16076 uint64_t tw0_cmd_fifo_ram_dbe : 1;
16077 uint64_t tw1_cmd_fifo_ram_dbe : 1;
16078 uint64_t tw2_cmd_fifo_ram_dbe : 1;
16079 uint64_t tw3_cmd_fifo_ram_dbe : 1;
16080 uint64_t rt_ram_dbe : 1;
16081 uint64_t sq_nt_ram_dbe : 1;
16082 uint64_t sq_pt_ram_dbe : 1;
16083 #endif
16084 } s;
16085 struct cvmx_pko_pse_sq5_ecc_dbe_sts0_s cn78xx;
16086 struct cvmx_pko_pse_sq5_ecc_dbe_sts0_s cn78xxp1;
16087 };
16088 typedef union cvmx_pko_pse_sq5_ecc_dbe_sts0 cvmx_pko_pse_sq5_ecc_dbe_sts0_t;
16089
16090
16091
16092
16093 union cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0 {
16094 uint64_t u64;
16095 struct cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0_s {
16096 #ifdef __BIG_ENDIAN_BITFIELD
16097 uint64_t pse_sq5_dbe_cmb0 : 1;
16098
16099
16100
16101 uint64_t reserved_0_62 : 63;
16102 #else
16103 uint64_t reserved_0_62 : 63;
16104 uint64_t pse_sq5_dbe_cmb0 : 1;
16105 #endif
16106 } s;
16107 struct cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0_s cn78xx;
16108 struct cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0_s cn78xxp1;
16109 };
16110 typedef union cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0_t;
16111
16112
16113
16114
16115 union cvmx_pko_pse_sq5_ecc_sbe_sts0 {
16116 uint64_t u64;
16117 struct cvmx_pko_pse_sq5_ecc_sbe_sts0_s {
16118 #ifdef __BIG_ENDIAN_BITFIELD
16119 uint64_t sq_pt_ram_sbe : 1;
16120 uint64_t sq_nt_ram_sbe : 1;
16121 uint64_t rt_ram_sbe : 1;
16122 uint64_t tw3_cmd_fifo_ram_sbe : 1;
16123 uint64_t tw2_cmd_fifo_ram_sbe : 1;
16124 uint64_t tw1_cmd_fifo_ram_sbe : 1;
16125 uint64_t tw0_cmd_fifo_ram_sbe : 1;
16126 uint64_t tp3_sram_sbe : 1;
16127 uint64_t tp2_sram_sbe : 1;
16128 uint64_t tp1_sram_sbe : 1;
16129 uint64_t tp0_sram_sbe : 1;
16130 uint64_t sts3_ram_sbe : 1;
16131 uint64_t sts2_ram_sbe : 1;
16132 uint64_t sts1_ram_sbe : 1;
16133 uint64_t sts0_ram_sbe : 1;
16134 uint64_t std3_ram_sbe : 1;
16135 uint64_t std2_ram_sbe : 1;
16136 uint64_t std1_ram_sbe : 1;
16137 uint64_t std0_ram_sbe : 1;
16138 uint64_t wt_ram_sbe : 1;
16139 uint64_t sc_ram_sbe : 1;
16140 uint64_t reserved_0_42 : 43;
16141 #else
16142 uint64_t reserved_0_42 : 43;
16143 uint64_t sc_ram_sbe : 1;
16144 uint64_t wt_ram_sbe : 1;
16145 uint64_t std0_ram_sbe : 1;
16146 uint64_t std1_ram_sbe : 1;
16147 uint64_t std2_ram_sbe : 1;
16148 uint64_t std3_ram_sbe : 1;
16149 uint64_t sts0_ram_sbe : 1;
16150 uint64_t sts1_ram_sbe : 1;
16151 uint64_t sts2_ram_sbe : 1;
16152 uint64_t sts3_ram_sbe : 1;
16153 uint64_t tp0_sram_sbe : 1;
16154 uint64_t tp1_sram_sbe : 1;
16155 uint64_t tp2_sram_sbe : 1;
16156 uint64_t tp3_sram_sbe : 1;
16157 uint64_t tw0_cmd_fifo_ram_sbe : 1;
16158 uint64_t tw1_cmd_fifo_ram_sbe : 1;
16159 uint64_t tw2_cmd_fifo_ram_sbe : 1;
16160 uint64_t tw3_cmd_fifo_ram_sbe : 1;
16161 uint64_t rt_ram_sbe : 1;
16162 uint64_t sq_nt_ram_sbe : 1;
16163 uint64_t sq_pt_ram_sbe : 1;
16164 #endif
16165 } s;
16166 struct cvmx_pko_pse_sq5_ecc_sbe_sts0_s cn78xx;
16167 struct cvmx_pko_pse_sq5_ecc_sbe_sts0_s cn78xxp1;
16168 };
16169 typedef union cvmx_pko_pse_sq5_ecc_sbe_sts0 cvmx_pko_pse_sq5_ecc_sbe_sts0_t;
16170
16171
16172
16173
16174 union cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0 {
16175 uint64_t u64;
16176 struct cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0_s {
16177 #ifdef __BIG_ENDIAN_BITFIELD
16178 uint64_t pse_sq5_sbe_cmb0 : 1;
16179
16180
16181
16182 uint64_t reserved_0_62 : 63;
16183 #else
16184 uint64_t reserved_0_62 : 63;
16185 uint64_t pse_sq5_sbe_cmb0 : 1;
16186 #endif
16187 } s;
16188 struct cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0_s cn78xx;
16189 struct cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0_s cn78xxp1;
16190 };
16191 typedef union cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0_t;
16192
16193
16194
16195
16196 union cvmx_pko_ptfx_status {
16197 uint64_t u64;
16198 struct cvmx_pko_ptfx_status_s {
16199 #ifdef __BIG_ENDIAN_BITFIELD
16200 uint64_t reserved_30_63 : 34;
16201 uint64_t tx_fifo_pkt_credit_cnt : 10;
16202 uint64_t total_in_flight_cnt : 8;
16203
16204 uint64_t in_flight_cnt : 7;
16205
16206 uint64_t mac_num : 5;
16207
16208
16209 #else
16210 uint64_t mac_num : 5;
16211 uint64_t in_flight_cnt : 7;
16212 uint64_t total_in_flight_cnt : 8;
16213 uint64_t tx_fifo_pkt_credit_cnt : 10;
16214 uint64_t reserved_30_63 : 34;
16215 #endif
16216 } s;
16217 struct cvmx_pko_ptfx_status_s cn73xx;
16218 struct cvmx_pko_ptfx_status_s cn78xx;
16219 struct cvmx_pko_ptfx_status_s cn78xxp1;
16220 struct cvmx_pko_ptfx_status_s cnf75xx;
16221 };
16222 typedef union cvmx_pko_ptfx_status cvmx_pko_ptfx_status_t;
16223
16224
16225
16226
16227 union cvmx_pko_ptf_iobp_cfg {
16228 uint64_t u64;
16229 struct cvmx_pko_ptf_iobp_cfg_s {
16230 #ifdef __BIG_ENDIAN_BITFIELD
16231 uint64_t reserved_44_63 : 20;
16232 uint64_t iobp1_ds_opt : 1;
16233 uint64_t iobp0_l2_allocate : 1;
16234
16235 uint64_t iobp1_magic_addr : 35;
16236 uint64_t max_read_size : 7;
16237 #else
16238 uint64_t max_read_size : 7;
16239 uint64_t iobp1_magic_addr : 35;
16240 uint64_t iobp0_l2_allocate : 1;
16241 uint64_t iobp1_ds_opt : 1;
16242 uint64_t reserved_44_63 : 20;
16243 #endif
16244 } s;
16245 struct cvmx_pko_ptf_iobp_cfg_s cn73xx;
16246 struct cvmx_pko_ptf_iobp_cfg_s cn78xx;
16247 struct cvmx_pko_ptf_iobp_cfg_s cn78xxp1;
16248 struct cvmx_pko_ptf_iobp_cfg_s cnf75xx;
16249 };
16250 typedef union cvmx_pko_ptf_iobp_cfg cvmx_pko_ptf_iobp_cfg_t;
16251
16252
16253
16254
16255
16256
16257
16258
16259
16260
16261
16262
16263
16264
16265
16266
16267
16268
16269
16270 union cvmx_pko_ptgfx_cfg {
16271 uint64_t u64;
16272 struct cvmx_pko_ptgfx_cfg_s {
16273 #ifdef __BIG_ENDIAN_BITFIELD
16274 uint64_t reserved_7_63 : 57;
16275 uint64_t reset : 1;
16276
16277 uint64_t rate : 3;
16278
16279
16280
16281
16282
16283
16284
16285
16286
16287
16288
16289
16290 uint64_t size : 3;
16291
16292
16293
16294
16295
16296
16297
16298
16299
16300
16301
16302
16303
16304
16305
16306
16307
16308
16309
16310
16311
16312
16313
16314
16315
16316
16317
16318
16319
16320 #else
16321 uint64_t size : 3;
16322 uint64_t rate : 3;
16323 uint64_t reset : 1;
16324 uint64_t reserved_7_63 : 57;
16325 #endif
16326 } s;
16327 struct cvmx_pko_ptgfx_cfg_cn73xx {
16328 #ifdef __BIG_ENDIAN_BITFIELD
16329 uint64_t reserved_7_63 : 57;
16330 uint64_t reset : 1;
16331
16332 uint64_t reserved_5_5 : 1;
16333 uint64_t rate : 2;
16334
16335
16336
16337
16338
16339
16340
16341
16342
16343
16344
16345
16346 uint64_t size : 3;
16347
16348
16349
16350
16351
16352
16353
16354
16355
16356
16357
16358
16359
16360
16361
16362
16363
16364
16365
16366
16367
16368
16369
16370
16371
16372
16373
16374
16375
16376 #else
16377 uint64_t size : 3;
16378 uint64_t rate : 2;
16379 uint64_t reserved_5_5 : 1;
16380 uint64_t reset : 1;
16381 uint64_t reserved_7_63 : 57;
16382 #endif
16383 } cn73xx;
16384 struct cvmx_pko_ptgfx_cfg_s cn78xx;
16385 struct cvmx_pko_ptgfx_cfg_s cn78xxp1;
16386 struct cvmx_pko_ptgfx_cfg_cn73xx cnf75xx;
16387 };
16388 typedef union cvmx_pko_ptgfx_cfg cvmx_pko_ptgfx_cfg_t;
16389
16390
16391
16392
16393
16394
16395
16396
16397 union cvmx_pko_reg_bist_result {
16398 uint64_t u64;
16399 struct cvmx_pko_reg_bist_result_s {
16400 #ifdef __BIG_ENDIAN_BITFIELD
16401 uint64_t reserved_0_63 : 64;
16402 #else
16403 uint64_t reserved_0_63 : 64;
16404 #endif
16405 } s;
16406 struct cvmx_pko_reg_bist_result_cn30xx {
16407 #ifdef __BIG_ENDIAN_BITFIELD
16408 uint64_t reserved_27_63 : 37;
16409 uint64_t psb2 : 5;
16410 uint64_t count : 1;
16411 uint64_t rif : 1;
16412 uint64_t wif : 1;
16413 uint64_t ncb : 1;
16414 uint64_t out : 1;
16415 uint64_t crc : 1;
16416 uint64_t chk : 1;
16417 uint64_t qsb : 2;
16418 uint64_t qcb : 2;
16419 uint64_t pdb : 4;
16420 uint64_t psb : 7;
16421 #else
16422 uint64_t psb : 7;
16423 uint64_t pdb : 4;
16424 uint64_t qcb : 2;
16425 uint64_t qsb : 2;
16426 uint64_t chk : 1;
16427 uint64_t crc : 1;
16428 uint64_t out : 1;
16429 uint64_t ncb : 1;
16430 uint64_t wif : 1;
16431 uint64_t rif : 1;
16432 uint64_t count : 1;
16433 uint64_t psb2 : 5;
16434 uint64_t reserved_27_63 : 37;
16435 #endif
16436 } cn30xx;
16437 struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
16438 struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
16439 struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
16440 struct cvmx_pko_reg_bist_result_cn50xx {
16441 #ifdef __BIG_ENDIAN_BITFIELD
16442 uint64_t reserved_33_63 : 31;
16443 uint64_t csr : 1;
16444 uint64_t iob : 1;
16445 uint64_t out_crc : 1;
16446 uint64_t out_ctl : 3;
16447 uint64_t out_sta : 1;
16448 uint64_t out_wif : 1;
16449 uint64_t prt_chk : 3;
16450 uint64_t prt_nxt : 1;
16451 uint64_t prt_psb : 6;
16452 uint64_t ncb_inb : 2;
16453 uint64_t prt_qcb : 2;
16454 uint64_t prt_qsb : 3;
16455 uint64_t dat_dat : 4;
16456 uint64_t dat_ptr : 4;
16457 #else
16458 uint64_t dat_ptr : 4;
16459 uint64_t dat_dat : 4;
16460 uint64_t prt_qsb : 3;
16461 uint64_t prt_qcb : 2;
16462 uint64_t ncb_inb : 2;
16463 uint64_t prt_psb : 6;
16464 uint64_t prt_nxt : 1;
16465 uint64_t prt_chk : 3;
16466 uint64_t out_wif : 1;
16467 uint64_t out_sta : 1;
16468 uint64_t out_ctl : 3;
16469 uint64_t out_crc : 1;
16470 uint64_t iob : 1;
16471 uint64_t csr : 1;
16472 uint64_t reserved_33_63 : 31;
16473 #endif
16474 } cn50xx;
16475 struct cvmx_pko_reg_bist_result_cn52xx {
16476 #ifdef __BIG_ENDIAN_BITFIELD
16477 uint64_t reserved_35_63 : 29;
16478 uint64_t csr : 1;
16479 uint64_t iob : 1;
16480 uint64_t out_dat : 1;
16481 uint64_t out_ctl : 3;
16482 uint64_t out_sta : 1;
16483 uint64_t out_wif : 1;
16484 uint64_t prt_chk : 3;
16485 uint64_t prt_nxt : 1;
16486 uint64_t prt_psb : 8;
16487 uint64_t ncb_inb : 2;
16488 uint64_t prt_qcb : 2;
16489 uint64_t prt_qsb : 3;
16490 uint64_t prt_ctl : 2;
16491 uint64_t dat_dat : 2;
16492 uint64_t dat_ptr : 4;
16493 #else
16494 uint64_t dat_ptr : 4;
16495 uint64_t dat_dat : 2;
16496 uint64_t prt_ctl : 2;
16497 uint64_t prt_qsb : 3;
16498 uint64_t prt_qcb : 2;
16499 uint64_t ncb_inb : 2;
16500 uint64_t prt_psb : 8;
16501 uint64_t prt_nxt : 1;
16502 uint64_t prt_chk : 3;
16503 uint64_t out_wif : 1;
16504 uint64_t out_sta : 1;
16505 uint64_t out_ctl : 3;
16506 uint64_t out_dat : 1;
16507 uint64_t iob : 1;
16508 uint64_t csr : 1;
16509 uint64_t reserved_35_63 : 29;
16510 #endif
16511 } cn52xx;
16512 struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
16513 struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
16514 struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
16515 struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
16516 struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
16517 struct cvmx_pko_reg_bist_result_cn52xx cn61xx;
16518 struct cvmx_pko_reg_bist_result_cn52xx cn63xx;
16519 struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1;
16520 struct cvmx_pko_reg_bist_result_cn52xx cn66xx;
16521 struct cvmx_pko_reg_bist_result_cn68xx {
16522 #ifdef __BIG_ENDIAN_BITFIELD
16523 uint64_t reserved_36_63 : 28;
16524 uint64_t crc : 1;
16525 uint64_t csr : 1;
16526 uint64_t iob : 1;
16527 uint64_t out_dat : 1;
16528 uint64_t reserved_31_31 : 1;
16529 uint64_t out_ctl : 2;
16530 uint64_t out_sta : 1;
16531 uint64_t out_wif : 1;
16532 uint64_t prt_chk : 3;
16533 uint64_t prt_nxt : 1;
16534 uint64_t prt_psb7 : 1;
16535 uint64_t reserved_21_21 : 1;
16536 uint64_t prt_psb : 6;
16537 uint64_t ncb_inb : 2;
16538 uint64_t prt_qcb : 2;
16539 uint64_t prt_qsb : 3;
16540 uint64_t prt_ctl : 2;
16541 uint64_t dat_dat : 2;
16542 uint64_t dat_ptr : 4;
16543 #else
16544 uint64_t dat_ptr : 4;
16545 uint64_t dat_dat : 2;
16546 uint64_t prt_ctl : 2;
16547 uint64_t prt_qsb : 3;
16548 uint64_t prt_qcb : 2;
16549 uint64_t ncb_inb : 2;
16550 uint64_t prt_psb : 6;
16551 uint64_t reserved_21_21 : 1;
16552 uint64_t prt_psb7 : 1;
16553 uint64_t prt_nxt : 1;
16554 uint64_t prt_chk : 3;
16555 uint64_t out_wif : 1;
16556 uint64_t out_sta : 1;
16557 uint64_t out_ctl : 2;
16558 uint64_t reserved_31_31 : 1;
16559 uint64_t out_dat : 1;
16560 uint64_t iob : 1;
16561 uint64_t csr : 1;
16562 uint64_t crc : 1;
16563 uint64_t reserved_36_63 : 28;
16564 #endif
16565 } cn68xx;
16566 struct cvmx_pko_reg_bist_result_cn68xxp1 {
16567 #ifdef __BIG_ENDIAN_BITFIELD
16568 uint64_t reserved_35_63 : 29;
16569 uint64_t csr : 1;
16570 uint64_t iob : 1;
16571 uint64_t out_dat : 1;
16572 uint64_t reserved_31_31 : 1;
16573 uint64_t out_ctl : 2;
16574 uint64_t out_sta : 1;
16575 uint64_t out_wif : 1;
16576 uint64_t prt_chk : 3;
16577 uint64_t prt_nxt : 1;
16578 uint64_t prt_psb7 : 1;
16579 uint64_t reserved_21_21 : 1;
16580 uint64_t prt_psb : 6;
16581 uint64_t ncb_inb : 2;
16582 uint64_t prt_qcb : 2;
16583 uint64_t prt_qsb : 3;
16584 uint64_t prt_ctl : 2;
16585 uint64_t dat_dat : 2;
16586 uint64_t dat_ptr : 4;
16587 #else
16588 uint64_t dat_ptr : 4;
16589 uint64_t dat_dat : 2;
16590 uint64_t prt_ctl : 2;
16591 uint64_t prt_qsb : 3;
16592 uint64_t prt_qcb : 2;
16593 uint64_t ncb_inb : 2;
16594 uint64_t prt_psb : 6;
16595 uint64_t reserved_21_21 : 1;
16596 uint64_t prt_psb7 : 1;
16597 uint64_t prt_nxt : 1;
16598 uint64_t prt_chk : 3;
16599 uint64_t out_wif : 1;
16600 uint64_t out_sta : 1;
16601 uint64_t out_ctl : 2;
16602 uint64_t reserved_31_31 : 1;
16603 uint64_t out_dat : 1;
16604 uint64_t iob : 1;
16605 uint64_t csr : 1;
16606 uint64_t reserved_35_63 : 29;
16607 #endif
16608 } cn68xxp1;
16609 struct cvmx_pko_reg_bist_result_cn70xx {
16610 #ifdef __BIG_ENDIAN_BITFIELD
16611 uint64_t reserved_30_63 : 34;
16612 uint64_t csr : 1;
16613 uint64_t iob : 1;
16614 uint64_t out_dat : 1;
16615 uint64_t out_ctl : 1;
16616 uint64_t out_sta : 1;
16617 uint64_t out_wif : 1;
16618 uint64_t prt_chk : 3;
16619 uint64_t prt_nxt : 1;
16620 uint64_t prt_psb : 8;
16621 uint64_t ncb_inb : 1;
16622 uint64_t prt_qcb : 1;
16623 uint64_t prt_qsb : 2;
16624 uint64_t prt_ctl : 2;
16625 uint64_t dat_dat : 2;
16626 uint64_t dat_ptr : 4;
16627 #else
16628 uint64_t dat_ptr : 4;
16629 uint64_t dat_dat : 2;
16630 uint64_t prt_ctl : 2;
16631 uint64_t prt_qsb : 2;
16632 uint64_t prt_qcb : 1;
16633 uint64_t ncb_inb : 1;
16634 uint64_t prt_psb : 8;
16635 uint64_t prt_nxt : 1;
16636 uint64_t prt_chk : 3;
16637 uint64_t out_wif : 1;
16638 uint64_t out_sta : 1;
16639 uint64_t out_ctl : 1;
16640 uint64_t out_dat : 1;
16641 uint64_t iob : 1;
16642 uint64_t csr : 1;
16643 uint64_t reserved_30_63 : 34;
16644 #endif
16645 } cn70xx;
16646 struct cvmx_pko_reg_bist_result_cn70xx cn70xxp1;
16647 struct cvmx_pko_reg_bist_result_cn52xx cnf71xx;
16648 };
16649 typedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t;
16650
16651
16652
16653
16654
16655
16656
16657
16658
16659 union cvmx_pko_reg_cmd_buf {
16660 uint64_t u64;
16661 struct cvmx_pko_reg_cmd_buf_s {
16662 #ifdef __BIG_ENDIAN_BITFIELD
16663 uint64_t reserved_23_63 : 41;
16664 uint64_t pool : 3;
16665 uint64_t reserved_13_19 : 7;
16666 uint64_t size : 13;
16667 #else
16668 uint64_t size : 13;
16669 uint64_t reserved_13_19 : 7;
16670 uint64_t pool : 3;
16671 uint64_t reserved_23_63 : 41;
16672 #endif
16673 } s;
16674 struct cvmx_pko_reg_cmd_buf_s cn30xx;
16675 struct cvmx_pko_reg_cmd_buf_s cn31xx;
16676 struct cvmx_pko_reg_cmd_buf_s cn38xx;
16677 struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
16678 struct cvmx_pko_reg_cmd_buf_s cn50xx;
16679 struct cvmx_pko_reg_cmd_buf_s cn52xx;
16680 struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
16681 struct cvmx_pko_reg_cmd_buf_s cn56xx;
16682 struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
16683 struct cvmx_pko_reg_cmd_buf_s cn58xx;
16684 struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
16685 struct cvmx_pko_reg_cmd_buf_s cn61xx;
16686 struct cvmx_pko_reg_cmd_buf_s cn63xx;
16687 struct cvmx_pko_reg_cmd_buf_s cn63xxp1;
16688 struct cvmx_pko_reg_cmd_buf_s cn66xx;
16689 struct cvmx_pko_reg_cmd_buf_s cn68xx;
16690 struct cvmx_pko_reg_cmd_buf_s cn68xxp1;
16691 struct cvmx_pko_reg_cmd_buf_cn70xx {
16692 #ifdef __BIG_ENDIAN_BITFIELD
16693 uint64_t reserved_23_63 : 41;
16694 uint64_t pool : 3;
16695 uint64_t reserved_19_13 : 7;
16696 uint64_t size : 13;
16697 #else
16698 uint64_t size : 13;
16699 uint64_t reserved_19_13 : 7;
16700 uint64_t pool : 3;
16701 uint64_t reserved_23_63 : 41;
16702 #endif
16703 } cn70xx;
16704 struct cvmx_pko_reg_cmd_buf_cn70xx cn70xxp1;
16705 struct cvmx_pko_reg_cmd_buf_s cnf71xx;
16706 };
16707 typedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t;
16708
16709
16710
16711
16712
16713
16714
16715
16716 union cvmx_pko_reg_crc_ctlx {
16717 uint64_t u64;
16718 struct cvmx_pko_reg_crc_ctlx_s {
16719 #ifdef __BIG_ENDIAN_BITFIELD
16720 uint64_t reserved_2_63 : 62;
16721 uint64_t invres : 1;
16722 uint64_t refin : 1;
16723
16724
16725
16726 #else
16727 uint64_t refin : 1;
16728 uint64_t invres : 1;
16729 uint64_t reserved_2_63 : 62;
16730 #endif
16731 } s;
16732 struct cvmx_pko_reg_crc_ctlx_s cn38xx;
16733 struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
16734 struct cvmx_pko_reg_crc_ctlx_s cn58xx;
16735 struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
16736 };
16737 typedef union cvmx_pko_reg_crc_ctlx cvmx_pko_reg_crc_ctlx_t;
16738
16739
16740
16741
16742
16743
16744
16745
16746 union cvmx_pko_reg_crc_enable {
16747 uint64_t u64;
16748 struct cvmx_pko_reg_crc_enable_s {
16749 #ifdef __BIG_ENDIAN_BITFIELD
16750 uint64_t reserved_32_63 : 32;
16751 uint64_t enable : 32;
16752
16753
16754
16755 #else
16756 uint64_t enable : 32;
16757 uint64_t reserved_32_63 : 32;
16758 #endif
16759 } s;
16760 struct cvmx_pko_reg_crc_enable_s cn38xx;
16761 struct cvmx_pko_reg_crc_enable_s cn38xxp2;
16762 struct cvmx_pko_reg_crc_enable_s cn58xx;
16763 struct cvmx_pko_reg_crc_enable_s cn58xxp1;
16764 };
16765 typedef union cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_enable_t;
16766
16767
16768
16769
16770
16771
16772
16773
16774
16775
16776
16777
16778
16779
16780
16781
16782
16783
16784
16785
16786
16787
16788
16789
16790
16791
16792
16793
16794
16795
16796
16797
16798
16799
16800
16801
16802 union cvmx_pko_reg_crc_ivx {
16803 uint64_t u64;
16804 struct cvmx_pko_reg_crc_ivx_s {
16805 #ifdef __BIG_ENDIAN_BITFIELD
16806 uint64_t reserved_32_63 : 32;
16807 uint64_t iv : 32;
16808 #else
16809 uint64_t iv : 32;
16810 uint64_t reserved_32_63 : 32;
16811 #endif
16812 } s;
16813 struct cvmx_pko_reg_crc_ivx_s cn38xx;
16814 struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
16815 struct cvmx_pko_reg_crc_ivx_s cn58xx;
16816 struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
16817 };
16818 typedef union cvmx_pko_reg_crc_ivx cvmx_pko_reg_crc_ivx_t;
16819
16820
16821
16822
16823
16824
16825
16826
16827 union cvmx_pko_reg_debug0 {
16828 uint64_t u64;
16829 struct cvmx_pko_reg_debug0_s {
16830 #ifdef __BIG_ENDIAN_BITFIELD
16831 uint64_t asserts : 64;
16832 #else
16833 uint64_t asserts : 64;
16834 #endif
16835 } s;
16836 struct cvmx_pko_reg_debug0_cn30xx {
16837 #ifdef __BIG_ENDIAN_BITFIELD
16838 uint64_t reserved_17_63 : 47;
16839 uint64_t asserts : 17;
16840 #else
16841 uint64_t asserts : 17;
16842 uint64_t reserved_17_63 : 47;
16843 #endif
16844 } cn30xx;
16845 struct cvmx_pko_reg_debug0_cn30xx cn31xx;
16846 struct cvmx_pko_reg_debug0_cn30xx cn38xx;
16847 struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
16848 struct cvmx_pko_reg_debug0_s cn50xx;
16849 struct cvmx_pko_reg_debug0_s cn52xx;
16850 struct cvmx_pko_reg_debug0_s cn52xxp1;
16851 struct cvmx_pko_reg_debug0_s cn56xx;
16852 struct cvmx_pko_reg_debug0_s cn56xxp1;
16853 struct cvmx_pko_reg_debug0_s cn58xx;
16854 struct cvmx_pko_reg_debug0_s cn58xxp1;
16855 struct cvmx_pko_reg_debug0_s cn61xx;
16856 struct cvmx_pko_reg_debug0_s cn63xx;
16857 struct cvmx_pko_reg_debug0_s cn63xxp1;
16858 struct cvmx_pko_reg_debug0_s cn66xx;
16859 struct cvmx_pko_reg_debug0_s cn68xx;
16860 struct cvmx_pko_reg_debug0_s cn68xxp1;
16861 struct cvmx_pko_reg_debug0_s cn70xx;
16862 struct cvmx_pko_reg_debug0_s cn70xxp1;
16863 struct cvmx_pko_reg_debug0_s cnf71xx;
16864 };
16865 typedef union cvmx_pko_reg_debug0 cvmx_pko_reg_debug0_t;
16866
16867
16868
16869
16870 union cvmx_pko_reg_debug1 {
16871 uint64_t u64;
16872 struct cvmx_pko_reg_debug1_s {
16873 #ifdef __BIG_ENDIAN_BITFIELD
16874 uint64_t asserts : 64;
16875 #else
16876 uint64_t asserts : 64;
16877 #endif
16878 } s;
16879 struct cvmx_pko_reg_debug1_s cn50xx;
16880 struct cvmx_pko_reg_debug1_s cn52xx;
16881 struct cvmx_pko_reg_debug1_s cn52xxp1;
16882 struct cvmx_pko_reg_debug1_s cn56xx;
16883 struct cvmx_pko_reg_debug1_s cn56xxp1;
16884 struct cvmx_pko_reg_debug1_s cn58xx;
16885 struct cvmx_pko_reg_debug1_s cn58xxp1;
16886 struct cvmx_pko_reg_debug1_s cn61xx;
16887 struct cvmx_pko_reg_debug1_s cn63xx;
16888 struct cvmx_pko_reg_debug1_s cn63xxp1;
16889 struct cvmx_pko_reg_debug1_s cn66xx;
16890 struct cvmx_pko_reg_debug1_s cn68xx;
16891 struct cvmx_pko_reg_debug1_s cn68xxp1;
16892 struct cvmx_pko_reg_debug1_s cn70xx;
16893 struct cvmx_pko_reg_debug1_s cn70xxp1;
16894 struct cvmx_pko_reg_debug1_s cnf71xx;
16895 };
16896 typedef union cvmx_pko_reg_debug1 cvmx_pko_reg_debug1_t;
16897
16898
16899
16900
16901 union cvmx_pko_reg_debug2 {
16902 uint64_t u64;
16903 struct cvmx_pko_reg_debug2_s {
16904 #ifdef __BIG_ENDIAN_BITFIELD
16905 uint64_t asserts : 64;
16906 #else
16907 uint64_t asserts : 64;
16908 #endif
16909 } s;
16910 struct cvmx_pko_reg_debug2_s cn50xx;
16911 struct cvmx_pko_reg_debug2_s cn52xx;
16912 struct cvmx_pko_reg_debug2_s cn52xxp1;
16913 struct cvmx_pko_reg_debug2_s cn56xx;
16914 struct cvmx_pko_reg_debug2_s cn56xxp1;
16915 struct cvmx_pko_reg_debug2_s cn58xx;
16916 struct cvmx_pko_reg_debug2_s cn58xxp1;
16917 struct cvmx_pko_reg_debug2_s cn61xx;
16918 struct cvmx_pko_reg_debug2_s cn63xx;
16919 struct cvmx_pko_reg_debug2_s cn63xxp1;
16920 struct cvmx_pko_reg_debug2_s cn66xx;
16921 struct cvmx_pko_reg_debug2_s cn68xx;
16922 struct cvmx_pko_reg_debug2_s cn68xxp1;
16923 struct cvmx_pko_reg_debug2_s cn70xx;
16924 struct cvmx_pko_reg_debug2_s cn70xxp1;
16925 struct cvmx_pko_reg_debug2_s cnf71xx;
16926 };
16927 typedef union cvmx_pko_reg_debug2 cvmx_pko_reg_debug2_t;
16928
16929
16930
16931
16932 union cvmx_pko_reg_debug3 {
16933 uint64_t u64;
16934 struct cvmx_pko_reg_debug3_s {
16935 #ifdef __BIG_ENDIAN_BITFIELD
16936 uint64_t asserts : 64;
16937 #else
16938 uint64_t asserts : 64;
16939 #endif
16940 } s;
16941 struct cvmx_pko_reg_debug3_s cn50xx;
16942 struct cvmx_pko_reg_debug3_s cn52xx;
16943 struct cvmx_pko_reg_debug3_s cn52xxp1;
16944 struct cvmx_pko_reg_debug3_s cn56xx;
16945 struct cvmx_pko_reg_debug3_s cn56xxp1;
16946 struct cvmx_pko_reg_debug3_s cn58xx;
16947 struct cvmx_pko_reg_debug3_s cn58xxp1;
16948 struct cvmx_pko_reg_debug3_s cn61xx;
16949 struct cvmx_pko_reg_debug3_s cn63xx;
16950 struct cvmx_pko_reg_debug3_s cn63xxp1;
16951 struct cvmx_pko_reg_debug3_s cn66xx;
16952 struct cvmx_pko_reg_debug3_s cn68xx;
16953 struct cvmx_pko_reg_debug3_s cn68xxp1;
16954 struct cvmx_pko_reg_debug3_s cn70xx;
16955 struct cvmx_pko_reg_debug3_s cn70xxp1;
16956 struct cvmx_pko_reg_debug3_s cnf71xx;
16957 };
16958 typedef union cvmx_pko_reg_debug3 cvmx_pko_reg_debug3_t;
16959
16960
16961
16962
16963 union cvmx_pko_reg_debug4 {
16964 uint64_t u64;
16965 struct cvmx_pko_reg_debug4_s {
16966 #ifdef __BIG_ENDIAN_BITFIELD
16967 uint64_t asserts : 64;
16968 #else
16969 uint64_t asserts : 64;
16970 #endif
16971 } s;
16972 struct cvmx_pko_reg_debug4_s cn68xx;
16973 struct cvmx_pko_reg_debug4_s cn68xxp1;
16974 };
16975 typedef union cvmx_pko_reg_debug4 cvmx_pko_reg_debug4_t;
16976
16977
16978
16979
16980
16981
16982
16983
16984 union cvmx_pko_reg_engine_inflight {
16985 uint64_t u64;
16986 struct cvmx_pko_reg_engine_inflight_s {
16987 #ifdef __BIG_ENDIAN_BITFIELD
16988 uint64_t engine15 : 4;
16989 uint64_t engine14 : 4;
16990 uint64_t engine13 : 4;
16991 uint64_t engine12 : 4;
16992 uint64_t engine11 : 4;
16993 uint64_t engine10 : 4;
16994 uint64_t engine9 : 4;
16995 uint64_t engine8 : 4;
16996 uint64_t engine7 : 4;
16997 uint64_t engine6 : 4;
16998 uint64_t engine5 : 4;
16999 uint64_t engine4 : 4;
17000 uint64_t engine3 : 4;
17001 uint64_t engine2 : 4;
17002 uint64_t engine1 : 4;
17003 uint64_t engine0 : 4;
17004 #else
17005 uint64_t engine0 : 4;
17006 uint64_t engine1 : 4;
17007 uint64_t engine2 : 4;
17008 uint64_t engine3 : 4;
17009 uint64_t engine4 : 4;
17010 uint64_t engine5 : 4;
17011 uint64_t engine6 : 4;
17012 uint64_t engine7 : 4;
17013 uint64_t engine8 : 4;
17014 uint64_t engine9 : 4;
17015 uint64_t engine10 : 4;
17016 uint64_t engine11 : 4;
17017 uint64_t engine12 : 4;
17018 uint64_t engine13 : 4;
17019 uint64_t engine14 : 4;
17020 uint64_t engine15 : 4;
17021 #endif
17022 } s;
17023 struct cvmx_pko_reg_engine_inflight_cn52xx {
17024 #ifdef __BIG_ENDIAN_BITFIELD
17025 uint64_t reserved_40_63 : 24;
17026 uint64_t engine9 : 4;
17027 uint64_t engine8 : 4;
17028 uint64_t engine7 : 4;
17029 uint64_t engine6 : 4;
17030 uint64_t engine5 : 4;
17031 uint64_t engine4 : 4;
17032 uint64_t engine3 : 4;
17033 uint64_t engine2 : 4;
17034 uint64_t engine1 : 4;
17035 uint64_t engine0 : 4;
17036 #else
17037 uint64_t engine0 : 4;
17038 uint64_t engine1 : 4;
17039 uint64_t engine2 : 4;
17040 uint64_t engine3 : 4;
17041 uint64_t engine4 : 4;
17042 uint64_t engine5 : 4;
17043 uint64_t engine6 : 4;
17044 uint64_t engine7 : 4;
17045 uint64_t engine8 : 4;
17046 uint64_t engine9 : 4;
17047 uint64_t reserved_40_63 : 24;
17048 #endif
17049 } cn52xx;
17050 struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1;
17051 struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx;
17052 struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1;
17053 struct cvmx_pko_reg_engine_inflight_cn61xx {
17054 #ifdef __BIG_ENDIAN_BITFIELD
17055 uint64_t reserved_56_63 : 8;
17056 uint64_t engine13 : 4;
17057 uint64_t engine12 : 4;
17058 uint64_t engine11 : 4;
17059 uint64_t engine10 : 4;
17060 uint64_t engine9 : 4;
17061 uint64_t engine8 : 4;
17062 uint64_t engine7 : 4;
17063 uint64_t engine6 : 4;
17064 uint64_t engine5 : 4;
17065 uint64_t engine4 : 4;
17066 uint64_t engine3 : 4;
17067 uint64_t engine2 : 4;
17068 uint64_t engine1 : 4;
17069 uint64_t engine0 : 4;
17070 #else
17071 uint64_t engine0 : 4;
17072 uint64_t engine1 : 4;
17073 uint64_t engine2 : 4;
17074 uint64_t engine3 : 4;
17075 uint64_t engine4 : 4;
17076 uint64_t engine5 : 4;
17077 uint64_t engine6 : 4;
17078 uint64_t engine7 : 4;
17079 uint64_t engine8 : 4;
17080 uint64_t engine9 : 4;
17081 uint64_t engine10 : 4;
17082 uint64_t engine11 : 4;
17083 uint64_t engine12 : 4;
17084 uint64_t engine13 : 4;
17085 uint64_t reserved_56_63 : 8;
17086 #endif
17087 } cn61xx;
17088 struct cvmx_pko_reg_engine_inflight_cn63xx {
17089 #ifdef __BIG_ENDIAN_BITFIELD
17090 uint64_t reserved_48_63 : 16;
17091 uint64_t engine11 : 4;
17092 uint64_t engine10 : 4;
17093 uint64_t engine9 : 4;
17094 uint64_t engine8 : 4;
17095 uint64_t engine7 : 4;
17096 uint64_t engine6 : 4;
17097 uint64_t engine5 : 4;
17098 uint64_t engine4 : 4;
17099 uint64_t engine3 : 4;
17100 uint64_t engine2 : 4;
17101 uint64_t engine1 : 4;
17102 uint64_t engine0 : 4;
17103 #else
17104 uint64_t engine0 : 4;
17105 uint64_t engine1 : 4;
17106 uint64_t engine2 : 4;
17107 uint64_t engine3 : 4;
17108 uint64_t engine4 : 4;
17109 uint64_t engine5 : 4;
17110 uint64_t engine6 : 4;
17111 uint64_t engine7 : 4;
17112 uint64_t engine8 : 4;
17113 uint64_t engine9 : 4;
17114 uint64_t engine10 : 4;
17115 uint64_t engine11 : 4;
17116 uint64_t reserved_48_63 : 16;
17117 #endif
17118 } cn63xx;
17119 struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1;
17120 struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx;
17121 struct cvmx_pko_reg_engine_inflight_s cn68xx;
17122 struct cvmx_pko_reg_engine_inflight_s cn68xxp1;
17123 struct cvmx_pko_reg_engine_inflight_cn61xx cn70xx;
17124 struct cvmx_pko_reg_engine_inflight_cn61xx cn70xxp1;
17125 struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx;
17126 };
17127 typedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t;
17128
17129
17130
17131
17132
17133
17134
17135
17136 union cvmx_pko_reg_engine_inflight1 {
17137 uint64_t u64;
17138 struct cvmx_pko_reg_engine_inflight1_s {
17139 #ifdef __BIG_ENDIAN_BITFIELD
17140 uint64_t reserved_16_63 : 48;
17141 uint64_t engine19 : 4;
17142 uint64_t engine18 : 4;
17143 uint64_t engine17 : 4;
17144 uint64_t engine16 : 4;
17145 #else
17146 uint64_t engine16 : 4;
17147 uint64_t engine17 : 4;
17148 uint64_t engine18 : 4;
17149 uint64_t engine19 : 4;
17150 uint64_t reserved_16_63 : 48;
17151 #endif
17152 } s;
17153 struct cvmx_pko_reg_engine_inflight1_s cn68xx;
17154 struct cvmx_pko_reg_engine_inflight1_s cn68xxp1;
17155 };
17156 typedef union cvmx_pko_reg_engine_inflight1 cvmx_pko_reg_engine_inflight1_t;
17157
17158
17159
17160
17161
17162
17163
17164
17165 union cvmx_pko_reg_engine_storagex {
17166 uint64_t u64;
17167 struct cvmx_pko_reg_engine_storagex_s {
17168 #ifdef __BIG_ENDIAN_BITFIELD
17169 uint64_t engine15 : 4;
17170
17171
17172
17173 uint64_t engine14 : 4;
17174
17175
17176
17177 uint64_t engine13 : 4;
17178
17179
17180
17181 uint64_t engine12 : 4;
17182
17183
17184
17185 uint64_t engine11 : 4;
17186
17187
17188
17189 uint64_t engine10 : 4;
17190
17191
17192
17193 uint64_t engine9 : 4;
17194
17195
17196
17197 uint64_t engine8 : 4;
17198
17199
17200
17201 uint64_t engine7 : 4;
17202
17203
17204
17205 uint64_t engine6 : 4;
17206
17207
17208
17209 uint64_t engine5 : 4;
17210
17211
17212
17213 uint64_t engine4 : 4;
17214
17215
17216
17217 uint64_t engine3 : 4;
17218
17219 uint64_t engine2 : 4;
17220
17221 uint64_t engine1 : 4;
17222
17223 uint64_t engine0 : 4;
17224
17225 #else
17226 uint64_t engine0 : 4;
17227 uint64_t engine1 : 4;
17228 uint64_t engine2 : 4;
17229 uint64_t engine3 : 4;
17230 uint64_t engine4 : 4;
17231 uint64_t engine5 : 4;
17232 uint64_t engine6 : 4;
17233 uint64_t engine7 : 4;
17234 uint64_t engine8 : 4;
17235 uint64_t engine9 : 4;
17236 uint64_t engine10 : 4;
17237 uint64_t engine11 : 4;
17238 uint64_t engine12 : 4;
17239 uint64_t engine13 : 4;
17240 uint64_t engine14 : 4;
17241 uint64_t engine15 : 4;
17242 #endif
17243 } s;
17244 struct cvmx_pko_reg_engine_storagex_s cn68xx;
17245 struct cvmx_pko_reg_engine_storagex_s cn68xxp1;
17246 };
17247 typedef union cvmx_pko_reg_engine_storagex cvmx_pko_reg_engine_storagex_t;
17248
17249
17250
17251
17252
17253
17254
17255
17256
17257
17258
17259
17260
17261 union cvmx_pko_reg_engine_thresh {
17262 uint64_t u64;
17263 struct cvmx_pko_reg_engine_thresh_s {
17264 #ifdef __BIG_ENDIAN_BITFIELD
17265 uint64_t reserved_20_63 : 44;
17266 uint64_t mask : 20;
17267
17268
17269 #else
17270 uint64_t mask : 20;
17271 uint64_t reserved_20_63 : 44;
17272 #endif
17273 } s;
17274 struct cvmx_pko_reg_engine_thresh_cn52xx {
17275 #ifdef __BIG_ENDIAN_BITFIELD
17276 uint64_t reserved_10_63 : 54;
17277 uint64_t mask : 10;
17278
17279
17280 #else
17281 uint64_t mask : 10;
17282 uint64_t reserved_10_63 : 54;
17283 #endif
17284 } cn52xx;
17285 struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1;
17286 struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx;
17287 struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1;
17288 struct cvmx_pko_reg_engine_thresh_cn61xx {
17289 #ifdef __BIG_ENDIAN_BITFIELD
17290 uint64_t reserved_14_63 : 50;
17291 uint64_t mask : 14;
17292
17293
17294 #else
17295 uint64_t mask : 14;
17296 uint64_t reserved_14_63 : 50;
17297 #endif
17298 } cn61xx;
17299 struct cvmx_pko_reg_engine_thresh_cn63xx {
17300 #ifdef __BIG_ENDIAN_BITFIELD
17301 uint64_t reserved_12_63 : 52;
17302 uint64_t mask : 12;
17303
17304
17305 #else
17306 uint64_t mask : 12;
17307 uint64_t reserved_12_63 : 52;
17308 #endif
17309 } cn63xx;
17310 struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1;
17311 struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx;
17312 struct cvmx_pko_reg_engine_thresh_s cn68xx;
17313 struct cvmx_pko_reg_engine_thresh_s cn68xxp1;
17314 struct cvmx_pko_reg_engine_thresh_cn61xx cn70xx;
17315 struct cvmx_pko_reg_engine_thresh_cn61xx cn70xxp1;
17316 struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx;
17317 };
17318 typedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t;
17319
17320
17321
17322
17323
17324
17325
17326
17327 union cvmx_pko_reg_error {
17328 uint64_t u64;
17329 struct cvmx_pko_reg_error_s {
17330 #ifdef __BIG_ENDIAN_BITFIELD
17331 uint64_t reserved_4_63 : 60;
17332 uint64_t loopback : 1;
17333 uint64_t currzero : 1;
17334 uint64_t doorbell : 1;
17335 uint64_t parity : 1;
17336 #else
17337 uint64_t parity : 1;
17338 uint64_t doorbell : 1;
17339 uint64_t currzero : 1;
17340 uint64_t loopback : 1;
17341 uint64_t reserved_4_63 : 60;
17342 #endif
17343 } s;
17344 struct cvmx_pko_reg_error_cn30xx {
17345 #ifdef __BIG_ENDIAN_BITFIELD
17346 uint64_t reserved_2_63 : 62;
17347 uint64_t doorbell : 1;
17348 uint64_t parity : 1;
17349 #else
17350 uint64_t parity : 1;
17351 uint64_t doorbell : 1;
17352 uint64_t reserved_2_63 : 62;
17353 #endif
17354 } cn30xx;
17355 struct cvmx_pko_reg_error_cn30xx cn31xx;
17356 struct cvmx_pko_reg_error_cn30xx cn38xx;
17357 struct cvmx_pko_reg_error_cn30xx cn38xxp2;
17358 struct cvmx_pko_reg_error_cn50xx {
17359 #ifdef __BIG_ENDIAN_BITFIELD
17360 uint64_t reserved_3_63 : 61;
17361 uint64_t currzero : 1;
17362 uint64_t doorbell : 1;
17363 uint64_t parity : 1;
17364 #else
17365 uint64_t parity : 1;
17366 uint64_t doorbell : 1;
17367 uint64_t currzero : 1;
17368 uint64_t reserved_3_63 : 61;
17369 #endif
17370 } cn50xx;
17371 struct cvmx_pko_reg_error_cn50xx cn52xx;
17372 struct cvmx_pko_reg_error_cn50xx cn52xxp1;
17373 struct cvmx_pko_reg_error_cn50xx cn56xx;
17374 struct cvmx_pko_reg_error_cn50xx cn56xxp1;
17375 struct cvmx_pko_reg_error_cn50xx cn58xx;
17376 struct cvmx_pko_reg_error_cn50xx cn58xxp1;
17377 struct cvmx_pko_reg_error_cn50xx cn61xx;
17378 struct cvmx_pko_reg_error_cn50xx cn63xx;
17379 struct cvmx_pko_reg_error_cn50xx cn63xxp1;
17380 struct cvmx_pko_reg_error_cn50xx cn66xx;
17381 struct cvmx_pko_reg_error_s cn68xx;
17382 struct cvmx_pko_reg_error_s cn68xxp1;
17383 struct cvmx_pko_reg_error_cn50xx cn70xx;
17384 struct cvmx_pko_reg_error_cn50xx cn70xxp1;
17385 struct cvmx_pko_reg_error_cn50xx cnf71xx;
17386 };
17387 typedef union cvmx_pko_reg_error cvmx_pko_reg_error_t;
17388
17389
17390
17391
17392
17393
17394
17395
17396
17397
17398 union cvmx_pko_reg_flags {
17399 uint64_t u64;
17400 struct cvmx_pko_reg_flags_s {
17401 #ifdef __BIG_ENDIAN_BITFIELD
17402 uint64_t reserved_9_63 : 55;
17403 uint64_t dis_perf3 : 1;
17404 uint64_t dis_perf2 : 1;
17405 uint64_t dis_perf1 : 1;
17406 uint64_t dis_perf0 : 1;
17407 uint64_t ena_throttle : 1;
17408
17409
17410
17411
17412
17413
17414 uint64_t reset : 1;
17415 uint64_t store_be : 1;
17416 uint64_t ena_dwb : 1;
17417 uint64_t ena_pko : 1;
17418 #else
17419 uint64_t ena_pko : 1;
17420 uint64_t ena_dwb : 1;
17421 uint64_t store_be : 1;
17422 uint64_t reset : 1;
17423 uint64_t ena_throttle : 1;
17424 uint64_t dis_perf0 : 1;
17425 uint64_t dis_perf1 : 1;
17426 uint64_t dis_perf2 : 1;
17427 uint64_t dis_perf3 : 1;
17428 uint64_t reserved_9_63 : 55;
17429 #endif
17430 } s;
17431 struct cvmx_pko_reg_flags_cn30xx {
17432 #ifdef __BIG_ENDIAN_BITFIELD
17433 uint64_t reserved_4_63 : 60;
17434 uint64_t reset : 1;
17435 uint64_t store_be : 1;
17436 uint64_t ena_dwb : 1;
17437 uint64_t ena_pko : 1;
17438 #else
17439 uint64_t ena_pko : 1;
17440 uint64_t ena_dwb : 1;
17441 uint64_t store_be : 1;
17442 uint64_t reset : 1;
17443 uint64_t reserved_4_63 : 60;
17444 #endif
17445 } cn30xx;
17446 struct cvmx_pko_reg_flags_cn30xx cn31xx;
17447 struct cvmx_pko_reg_flags_cn30xx cn38xx;
17448 struct cvmx_pko_reg_flags_cn30xx cn38xxp2;
17449 struct cvmx_pko_reg_flags_cn30xx cn50xx;
17450 struct cvmx_pko_reg_flags_cn30xx cn52xx;
17451 struct cvmx_pko_reg_flags_cn30xx cn52xxp1;
17452 struct cvmx_pko_reg_flags_cn30xx cn56xx;
17453 struct cvmx_pko_reg_flags_cn30xx cn56xxp1;
17454 struct cvmx_pko_reg_flags_cn30xx cn58xx;
17455 struct cvmx_pko_reg_flags_cn30xx cn58xxp1;
17456 struct cvmx_pko_reg_flags_cn61xx {
17457 #ifdef __BIG_ENDIAN_BITFIELD
17458 uint64_t reserved_9_63 : 55;
17459 uint64_t dis_perf3 : 1;
17460 uint64_t dis_perf2 : 1;
17461 uint64_t reserved_4_6 : 3;
17462 uint64_t reset : 1;
17463 uint64_t store_be : 1;
17464 uint64_t ena_dwb : 1;
17465 uint64_t ena_pko : 1;
17466 #else
17467 uint64_t ena_pko : 1;
17468 uint64_t ena_dwb : 1;
17469 uint64_t store_be : 1;
17470 uint64_t reset : 1;
17471 uint64_t reserved_4_6 : 3;
17472 uint64_t dis_perf2 : 1;
17473 uint64_t dis_perf3 : 1;
17474 uint64_t reserved_9_63 : 55;
17475 #endif
17476 } cn61xx;
17477 struct cvmx_pko_reg_flags_cn30xx cn63xx;
17478 struct cvmx_pko_reg_flags_cn30xx cn63xxp1;
17479 struct cvmx_pko_reg_flags_cn61xx cn66xx;
17480 struct cvmx_pko_reg_flags_s cn68xx;
17481 struct cvmx_pko_reg_flags_cn68xxp1 {
17482 #ifdef __BIG_ENDIAN_BITFIELD
17483 uint64_t reserved_7_63 : 57;
17484 uint64_t dis_perf1 : 1;
17485 uint64_t dis_perf0 : 1;
17486 uint64_t ena_throttle : 1;
17487
17488
17489
17490
17491
17492
17493 uint64_t reset : 1;
17494 uint64_t store_be : 1;
17495 uint64_t ena_dwb : 1;
17496 uint64_t ena_pko : 1;
17497 #else
17498 uint64_t ena_pko : 1;
17499 uint64_t ena_dwb : 1;
17500 uint64_t store_be : 1;
17501 uint64_t reset : 1;
17502 uint64_t ena_throttle : 1;
17503 uint64_t dis_perf0 : 1;
17504 uint64_t dis_perf1 : 1;
17505 uint64_t reserved_7_63 : 57;
17506 #endif
17507 } cn68xxp1;
17508 struct cvmx_pko_reg_flags_cn61xx cn70xx;
17509 struct cvmx_pko_reg_flags_cn61xx cn70xxp1;
17510 struct cvmx_pko_reg_flags_cn61xx cnf71xx;
17511 };
17512 typedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t;
17513
17514
17515
17516
17517
17518
17519
17520
17521
17522
17523
17524
17525
17526
17527
17528
17529
17530
17531 union cvmx_pko_reg_gmx_port_mode {
17532 uint64_t u64;
17533 struct cvmx_pko_reg_gmx_port_mode_s {
17534 #ifdef __BIG_ENDIAN_BITFIELD
17535 uint64_t reserved_6_63 : 58;
17536 uint64_t mode1 : 3;
17537 uint64_t mode0 : 3;
17538 #else
17539 uint64_t mode0 : 3;
17540 uint64_t mode1 : 3;
17541 uint64_t reserved_6_63 : 58;
17542 #endif
17543 } s;
17544 struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
17545 struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
17546 struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
17547 struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
17548 struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
17549 struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
17550 struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
17551 struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
17552 struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
17553 struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
17554 struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
17555 struct cvmx_pko_reg_gmx_port_mode_s cn61xx;
17556 struct cvmx_pko_reg_gmx_port_mode_s cn63xx;
17557 struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1;
17558 struct cvmx_pko_reg_gmx_port_mode_s cn66xx;
17559 struct cvmx_pko_reg_gmx_port_mode_s cn70xx;
17560 struct cvmx_pko_reg_gmx_port_mode_s cn70xxp1;
17561 struct cvmx_pko_reg_gmx_port_mode_s cnf71xx;
17562 };
17563 typedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t;
17564
17565
17566
17567
17568
17569
17570
17571
17572 union cvmx_pko_reg_int_mask {
17573 uint64_t u64;
17574 struct cvmx_pko_reg_int_mask_s {
17575 #ifdef __BIG_ENDIAN_BITFIELD
17576 uint64_t reserved_4_63 : 60;
17577 uint64_t loopback : 1;
17578 uint64_t currzero : 1;
17579 uint64_t doorbell : 1;
17580 uint64_t parity : 1;
17581 #else
17582 uint64_t parity : 1;
17583 uint64_t doorbell : 1;
17584 uint64_t currzero : 1;
17585 uint64_t loopback : 1;
17586 uint64_t reserved_4_63 : 60;
17587 #endif
17588 } s;
17589 struct cvmx_pko_reg_int_mask_cn30xx {
17590 #ifdef __BIG_ENDIAN_BITFIELD
17591 uint64_t reserved_2_63 : 62;
17592 uint64_t doorbell : 1;
17593 uint64_t parity : 1;
17594 #else
17595 uint64_t parity : 1;
17596 uint64_t doorbell : 1;
17597 uint64_t reserved_2_63 : 62;
17598 #endif
17599 } cn30xx;
17600 struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
17601 struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
17602 struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
17603 struct cvmx_pko_reg_int_mask_cn50xx {
17604 #ifdef __BIG_ENDIAN_BITFIELD
17605 uint64_t reserved_3_63 : 61;
17606 uint64_t currzero : 1;
17607 uint64_t doorbell : 1;
17608 uint64_t parity : 1;
17609 #else
17610 uint64_t parity : 1;
17611 uint64_t doorbell : 1;
17612 uint64_t currzero : 1;
17613 uint64_t reserved_3_63 : 61;
17614 #endif
17615 } cn50xx;
17616 struct cvmx_pko_reg_int_mask_cn50xx cn52xx;
17617 struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1;
17618 struct cvmx_pko_reg_int_mask_cn50xx cn56xx;
17619 struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1;
17620 struct cvmx_pko_reg_int_mask_cn50xx cn58xx;
17621 struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1;
17622 struct cvmx_pko_reg_int_mask_cn50xx cn61xx;
17623 struct cvmx_pko_reg_int_mask_cn50xx cn63xx;
17624 struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1;
17625 struct cvmx_pko_reg_int_mask_cn50xx cn66xx;
17626 struct cvmx_pko_reg_int_mask_s cn68xx;
17627 struct cvmx_pko_reg_int_mask_s cn68xxp1;
17628 struct cvmx_pko_reg_int_mask_cn50xx cn70xx;
17629 struct cvmx_pko_reg_int_mask_cn50xx cn70xxp1;
17630 struct cvmx_pko_reg_int_mask_cn50xx cnf71xx;
17631 };
17632 typedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t;
17633
17634
17635
17636
17637
17638
17639
17640
17641 union cvmx_pko_reg_loopback_bpid {
17642 uint64_t u64;
17643 struct cvmx_pko_reg_loopback_bpid_s {
17644 #ifdef __BIG_ENDIAN_BITFIELD
17645 uint64_t reserved_59_63 : 5;
17646 uint64_t bpid7 : 6;
17647 uint64_t reserved_52_52 : 1;
17648 uint64_t bpid6 : 6;
17649 uint64_t reserved_45_45 : 1;
17650 uint64_t bpid5 : 6;
17651 uint64_t reserved_38_38 : 1;
17652 uint64_t bpid4 : 6;
17653 uint64_t reserved_31_31 : 1;
17654 uint64_t bpid3 : 6;
17655 uint64_t reserved_24_24 : 1;
17656 uint64_t bpid2 : 6;
17657 uint64_t reserved_17_17 : 1;
17658 uint64_t bpid1 : 6;
17659 uint64_t reserved_10_10 : 1;
17660 uint64_t bpid0 : 6;
17661 uint64_t reserved_0_3 : 4;
17662 #else
17663 uint64_t reserved_0_3 : 4;
17664 uint64_t bpid0 : 6;
17665 uint64_t reserved_10_10 : 1;
17666 uint64_t bpid1 : 6;
17667 uint64_t reserved_17_17 : 1;
17668 uint64_t bpid2 : 6;
17669 uint64_t reserved_24_24 : 1;
17670 uint64_t bpid3 : 6;
17671 uint64_t reserved_31_31 : 1;
17672 uint64_t bpid4 : 6;
17673 uint64_t reserved_38_38 : 1;
17674 uint64_t bpid5 : 6;
17675 uint64_t reserved_45_45 : 1;
17676 uint64_t bpid6 : 6;
17677 uint64_t reserved_52_52 : 1;
17678 uint64_t bpid7 : 6;
17679 uint64_t reserved_59_63 : 5;
17680 #endif
17681 } s;
17682 struct cvmx_pko_reg_loopback_bpid_s cn68xx;
17683 struct cvmx_pko_reg_loopback_bpid_s cn68xxp1;
17684 };
17685 typedef union cvmx_pko_reg_loopback_bpid cvmx_pko_reg_loopback_bpid_t;
17686
17687
17688
17689
17690
17691
17692
17693
17694 union cvmx_pko_reg_loopback_pkind {
17695 uint64_t u64;
17696 struct cvmx_pko_reg_loopback_pkind_s {
17697 #ifdef __BIG_ENDIAN_BITFIELD
17698 uint64_t reserved_59_63 : 5;
17699 uint64_t pkind7 : 6;
17700 uint64_t reserved_52_52 : 1;
17701 uint64_t pkind6 : 6;
17702 uint64_t reserved_45_45 : 1;
17703 uint64_t pkind5 : 6;
17704 uint64_t reserved_38_38 : 1;
17705 uint64_t pkind4 : 6;
17706 uint64_t reserved_31_31 : 1;
17707 uint64_t pkind3 : 6;
17708 uint64_t reserved_24_24 : 1;
17709 uint64_t pkind2 : 6;
17710 uint64_t reserved_17_17 : 1;
17711 uint64_t pkind1 : 6;
17712 uint64_t reserved_10_10 : 1;
17713 uint64_t pkind0 : 6;
17714 uint64_t num_ports : 4;
17715 #else
17716 uint64_t num_ports : 4;
17717 uint64_t pkind0 : 6;
17718 uint64_t reserved_10_10 : 1;
17719 uint64_t pkind1 : 6;
17720 uint64_t reserved_17_17 : 1;
17721 uint64_t pkind2 : 6;
17722 uint64_t reserved_24_24 : 1;
17723 uint64_t pkind3 : 6;
17724 uint64_t reserved_31_31 : 1;
17725 uint64_t pkind4 : 6;
17726 uint64_t reserved_38_38 : 1;
17727 uint64_t pkind5 : 6;
17728 uint64_t reserved_45_45 : 1;
17729 uint64_t pkind6 : 6;
17730 uint64_t reserved_52_52 : 1;
17731 uint64_t pkind7 : 6;
17732 uint64_t reserved_59_63 : 5;
17733 #endif
17734 } s;
17735 struct cvmx_pko_reg_loopback_pkind_s cn68xx;
17736 struct cvmx_pko_reg_loopback_pkind_s cn68xxp1;
17737 };
17738 typedef union cvmx_pko_reg_loopback_pkind cvmx_pko_reg_loopback_pkind_t;
17739
17740
17741
17742
17743
17744
17745
17746
17747
17748 union cvmx_pko_reg_min_pkt {
17749 uint64_t u64;
17750 struct cvmx_pko_reg_min_pkt_s {
17751 #ifdef __BIG_ENDIAN_BITFIELD
17752 uint64_t size7 : 8;
17753 uint64_t size6 : 8;
17754 uint64_t size5 : 8;
17755 uint64_t size4 : 8;
17756 uint64_t size3 : 8;
17757 uint64_t size2 : 8;
17758 uint64_t size1 : 8;
17759 uint64_t size0 : 8;
17760 #else
17761 uint64_t size0 : 8;
17762 uint64_t size1 : 8;
17763 uint64_t size2 : 8;
17764 uint64_t size3 : 8;
17765 uint64_t size4 : 8;
17766 uint64_t size5 : 8;
17767 uint64_t size6 : 8;
17768 uint64_t size7 : 8;
17769 #endif
17770 } s;
17771 struct cvmx_pko_reg_min_pkt_s cn68xx;
17772 struct cvmx_pko_reg_min_pkt_s cn68xxp1;
17773 };
17774 typedef union cvmx_pko_reg_min_pkt cvmx_pko_reg_min_pkt_t;
17775
17776
17777
17778
17779 union cvmx_pko_reg_preempt {
17780 uint64_t u64;
17781 struct cvmx_pko_reg_preempt_s {
17782 #ifdef __BIG_ENDIAN_BITFIELD
17783 uint64_t reserved_16_63 : 48;
17784 uint64_t min_size : 16;
17785
17786
17787 #else
17788 uint64_t min_size : 16;
17789 uint64_t reserved_16_63 : 48;
17790 #endif
17791 } s;
17792 struct cvmx_pko_reg_preempt_s cn52xx;
17793 struct cvmx_pko_reg_preempt_s cn52xxp1;
17794 struct cvmx_pko_reg_preempt_s cn56xx;
17795 struct cvmx_pko_reg_preempt_s cn56xxp1;
17796 struct cvmx_pko_reg_preempt_s cn61xx;
17797 struct cvmx_pko_reg_preempt_s cn63xx;
17798 struct cvmx_pko_reg_preempt_s cn63xxp1;
17799 struct cvmx_pko_reg_preempt_s cn66xx;
17800 struct cvmx_pko_reg_preempt_s cn68xx;
17801 struct cvmx_pko_reg_preempt_s cn68xxp1;
17802 struct cvmx_pko_reg_preempt_s cn70xx;
17803 struct cvmx_pko_reg_preempt_s cn70xxp1;
17804 struct cvmx_pko_reg_preempt_s cnf71xx;
17805 };
17806 typedef union cvmx_pko_reg_preempt cvmx_pko_reg_preempt_t;
17807
17808
17809
17810
17811
17812
17813
17814
17815
17816
17817
17818
17819
17820
17821 union cvmx_pko_reg_queue_mode {
17822 uint64_t u64;
17823 struct cvmx_pko_reg_queue_mode_s {
17824 #ifdef __BIG_ENDIAN_BITFIELD
17825 uint64_t reserved_2_63 : 62;
17826 uint64_t mode : 2;
17827 #else
17828 uint64_t mode : 2;
17829 uint64_t reserved_2_63 : 62;
17830 #endif
17831 } s;
17832 struct cvmx_pko_reg_queue_mode_s cn30xx;
17833 struct cvmx_pko_reg_queue_mode_s cn31xx;
17834 struct cvmx_pko_reg_queue_mode_s cn38xx;
17835 struct cvmx_pko_reg_queue_mode_s cn38xxp2;
17836 struct cvmx_pko_reg_queue_mode_s cn50xx;
17837 struct cvmx_pko_reg_queue_mode_s cn52xx;
17838 struct cvmx_pko_reg_queue_mode_s cn52xxp1;
17839 struct cvmx_pko_reg_queue_mode_s cn56xx;
17840 struct cvmx_pko_reg_queue_mode_s cn56xxp1;
17841 struct cvmx_pko_reg_queue_mode_s cn58xx;
17842 struct cvmx_pko_reg_queue_mode_s cn58xxp1;
17843 struct cvmx_pko_reg_queue_mode_s cn61xx;
17844 struct cvmx_pko_reg_queue_mode_s cn63xx;
17845 struct cvmx_pko_reg_queue_mode_s cn63xxp1;
17846 struct cvmx_pko_reg_queue_mode_s cn66xx;
17847 struct cvmx_pko_reg_queue_mode_s cn68xx;
17848 struct cvmx_pko_reg_queue_mode_s cn68xxp1;
17849 struct cvmx_pko_reg_queue_mode_s cn70xx;
17850 struct cvmx_pko_reg_queue_mode_s cn70xxp1;
17851 struct cvmx_pko_reg_queue_mode_s cnf71xx;
17852 };
17853 typedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t;
17854
17855
17856
17857
17858
17859
17860
17861
17862
17863
17864
17865
17866
17867
17868
17869
17870 union cvmx_pko_reg_queue_preempt {
17871 uint64_t u64;
17872 struct cvmx_pko_reg_queue_preempt_s {
17873 #ifdef __BIG_ENDIAN_BITFIELD
17874 uint64_t reserved_2_63 : 62;
17875 uint64_t preemptee : 1;
17876
17877 uint64_t preempter : 1;
17878
17879
17880
17881 #else
17882 uint64_t preempter : 1;
17883 uint64_t preemptee : 1;
17884 uint64_t reserved_2_63 : 62;
17885 #endif
17886 } s;
17887 struct cvmx_pko_reg_queue_preempt_s cn52xx;
17888 struct cvmx_pko_reg_queue_preempt_s cn52xxp1;
17889 struct cvmx_pko_reg_queue_preempt_s cn56xx;
17890 struct cvmx_pko_reg_queue_preempt_s cn56xxp1;
17891 struct cvmx_pko_reg_queue_preempt_s cn61xx;
17892 struct cvmx_pko_reg_queue_preempt_s cn63xx;
17893 struct cvmx_pko_reg_queue_preempt_s cn63xxp1;
17894 struct cvmx_pko_reg_queue_preempt_s cn66xx;
17895 struct cvmx_pko_reg_queue_preempt_s cn68xx;
17896 struct cvmx_pko_reg_queue_preempt_s cn68xxp1;
17897 struct cvmx_pko_reg_queue_preempt_s cn70xx;
17898 struct cvmx_pko_reg_queue_preempt_s cn70xxp1;
17899 struct cvmx_pko_reg_queue_preempt_s cnf71xx;
17900 };
17901 typedef union cvmx_pko_reg_queue_preempt cvmx_pko_reg_queue_preempt_t;
17902
17903
17904
17905
17906
17907
17908
17909
17910
17911
17912
17913
17914 union cvmx_pko_reg_queue_ptrs1 {
17915 uint64_t u64;
17916 struct cvmx_pko_reg_queue_ptrs1_s {
17917 #ifdef __BIG_ENDIAN_BITFIELD
17918 uint64_t reserved_2_63 : 62;
17919 uint64_t idx3 : 1;
17920 uint64_t qid7 : 1;
17921 #else
17922 uint64_t qid7 : 1;
17923 uint64_t idx3 : 1;
17924 uint64_t reserved_2_63 : 62;
17925 #endif
17926 } s;
17927 struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
17928 struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
17929 struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
17930 struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
17931 struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
17932 struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
17933 struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
17934 struct cvmx_pko_reg_queue_ptrs1_s cn61xx;
17935 struct cvmx_pko_reg_queue_ptrs1_s cn63xx;
17936 struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1;
17937 struct cvmx_pko_reg_queue_ptrs1_s cn66xx;
17938 struct cvmx_pko_reg_queue_ptrs1_s cn70xx;
17939 struct cvmx_pko_reg_queue_ptrs1_s cn70xxp1;
17940 struct cvmx_pko_reg_queue_ptrs1_s cnf71xx;
17941 };
17942 typedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t;
17943
17944
17945
17946
17947
17948
17949
17950
17951
17952
17953
17954 union cvmx_pko_reg_read_idx {
17955 uint64_t u64;
17956 struct cvmx_pko_reg_read_idx_s {
17957 #ifdef __BIG_ENDIAN_BITFIELD
17958 uint64_t reserved_16_63 : 48;
17959 uint64_t inc : 8;
17960 uint64_t index : 8;
17961 #else
17962 uint64_t index : 8;
17963 uint64_t inc : 8;
17964 uint64_t reserved_16_63 : 48;
17965 #endif
17966 } s;
17967 struct cvmx_pko_reg_read_idx_s cn30xx;
17968 struct cvmx_pko_reg_read_idx_s cn31xx;
17969 struct cvmx_pko_reg_read_idx_s cn38xx;
17970 struct cvmx_pko_reg_read_idx_s cn38xxp2;
17971 struct cvmx_pko_reg_read_idx_s cn50xx;
17972 struct cvmx_pko_reg_read_idx_s cn52xx;
17973 struct cvmx_pko_reg_read_idx_s cn52xxp1;
17974 struct cvmx_pko_reg_read_idx_s cn56xx;
17975 struct cvmx_pko_reg_read_idx_s cn56xxp1;
17976 struct cvmx_pko_reg_read_idx_s cn58xx;
17977 struct cvmx_pko_reg_read_idx_s cn58xxp1;
17978 struct cvmx_pko_reg_read_idx_s cn61xx;
17979 struct cvmx_pko_reg_read_idx_s cn63xx;
17980 struct cvmx_pko_reg_read_idx_s cn63xxp1;
17981 struct cvmx_pko_reg_read_idx_s cn66xx;
17982 struct cvmx_pko_reg_read_idx_s cn68xx;
17983 struct cvmx_pko_reg_read_idx_s cn68xxp1;
17984 struct cvmx_pko_reg_read_idx_s cn70xx;
17985 struct cvmx_pko_reg_read_idx_s cn70xxp1;
17986 struct cvmx_pko_reg_read_idx_s cnf71xx;
17987 };
17988 typedef union cvmx_pko_reg_read_idx cvmx_pko_reg_read_idx_t;
17989
17990
17991
17992
17993
17994
17995
17996
17997
17998
17999
18000
18001 union cvmx_pko_reg_throttle {
18002 uint64_t u64;
18003 struct cvmx_pko_reg_throttle_s {
18004 #ifdef __BIG_ENDIAN_BITFIELD
18005 uint64_t reserved_32_63 : 32;
18006 uint64_t int_mask : 32;
18007 #else
18008 uint64_t int_mask : 32;
18009 uint64_t reserved_32_63 : 32;
18010 #endif
18011 } s;
18012 struct cvmx_pko_reg_throttle_s cn68xx;
18013 struct cvmx_pko_reg_throttle_s cn68xxp1;
18014 };
18015 typedef union cvmx_pko_reg_throttle cvmx_pko_reg_throttle_t;
18016
18017
18018
18019
18020
18021
18022
18023
18024 union cvmx_pko_reg_timestamp {
18025 uint64_t u64;
18026 struct cvmx_pko_reg_timestamp_s {
18027 #ifdef __BIG_ENDIAN_BITFIELD
18028 uint64_t reserved_4_63 : 60;
18029 uint64_t wqe_word : 4;
18030
18031 #else
18032 uint64_t wqe_word : 4;
18033 uint64_t reserved_4_63 : 60;
18034 #endif
18035 } s;
18036 struct cvmx_pko_reg_timestamp_s cn61xx;
18037 struct cvmx_pko_reg_timestamp_s cn63xx;
18038 struct cvmx_pko_reg_timestamp_s cn63xxp1;
18039 struct cvmx_pko_reg_timestamp_s cn66xx;
18040 struct cvmx_pko_reg_timestamp_s cn68xx;
18041 struct cvmx_pko_reg_timestamp_s cn68xxp1;
18042 struct cvmx_pko_reg_timestamp_s cn70xx;
18043 struct cvmx_pko_reg_timestamp_s cn70xxp1;
18044 struct cvmx_pko_reg_timestamp_s cnf71xx;
18045 };
18046 typedef union cvmx_pko_reg_timestamp cvmx_pko_reg_timestamp_t;
18047
18048
18049
18050
18051 union cvmx_pko_shaper_cfg {
18052 uint64_t u64;
18053 struct cvmx_pko_shaper_cfg_s {
18054 #ifdef __BIG_ENDIAN_BITFIELD
18055 uint64_t reserved_2_63 : 62;
18056 uint64_t color_aware : 1;
18057
18058 uint64_t red_send_as_yellow : 1;
18059
18060
18061
18062
18063
18064
18065
18066
18067
18068
18069
18070 #else
18071 uint64_t red_send_as_yellow : 1;
18072 uint64_t color_aware : 1;
18073 uint64_t reserved_2_63 : 62;
18074 #endif
18075 } s;
18076 struct cvmx_pko_shaper_cfg_s cn73xx;
18077 struct cvmx_pko_shaper_cfg_s cn78xx;
18078 struct cvmx_pko_shaper_cfg_s cn78xxp1;
18079 struct cvmx_pko_shaper_cfg_s cnf75xx;
18080 };
18081 typedef union cvmx_pko_shaper_cfg cvmx_pko_shaper_cfg_t;
18082
18083
18084
18085
18086
18087
18088
18089 union cvmx_pko_state_uid_in_usex_rd {
18090 uint64_t u64;
18091 struct cvmx_pko_state_uid_in_usex_rd_s {
18092 #ifdef __BIG_ENDIAN_BITFIELD
18093 uint64_t in_use : 64;
18094 #else
18095 uint64_t in_use : 64;
18096 #endif
18097 } s;
18098 struct cvmx_pko_state_uid_in_usex_rd_s cn73xx;
18099 struct cvmx_pko_state_uid_in_usex_rd_s cn78xx;
18100 struct cvmx_pko_state_uid_in_usex_rd_s cn78xxp1;
18101 struct cvmx_pko_state_uid_in_usex_rd_s cnf75xx;
18102 };
18103 typedef union cvmx_pko_state_uid_in_usex_rd cvmx_pko_state_uid_in_usex_rd_t;
18104
18105
18106
18107
18108 union cvmx_pko_status {
18109 uint64_t u64;
18110 struct cvmx_pko_status_s {
18111 #ifdef __BIG_ENDIAN_BITFIELD
18112 uint64_t pko_rdy : 1;
18113 uint64_t reserved_24_62 : 39;
18114 uint64_t c2qlut_rdy : 1;
18115 uint64_t ppfi_rdy : 1;
18116 uint64_t iobp1_rdy : 1;
18117 uint64_t ncb_rdy : 1;
18118 uint64_t pse_rdy : 1;
18119 uint64_t pdm_rdy : 1;
18120 uint64_t peb_rdy : 1;
18121 uint64_t csi_rdy : 1;
18122 uint64_t reserved_5_15 : 11;
18123 uint64_t ncb_bist_status : 1;
18124 uint64_t c2qlut_bist_status : 1;
18125 uint64_t pdm_bist_status : 1;
18126 uint64_t peb_bist_status : 1;
18127 uint64_t pse_bist_status : 1;
18128 #else
18129 uint64_t pse_bist_status : 1;
18130 uint64_t peb_bist_status : 1;
18131 uint64_t pdm_bist_status : 1;
18132 uint64_t c2qlut_bist_status : 1;
18133 uint64_t ncb_bist_status : 1;
18134 uint64_t reserved_5_15 : 11;
18135 uint64_t csi_rdy : 1;
18136 uint64_t peb_rdy : 1;
18137 uint64_t pdm_rdy : 1;
18138 uint64_t pse_rdy : 1;
18139 uint64_t ncb_rdy : 1;
18140 uint64_t iobp1_rdy : 1;
18141 uint64_t ppfi_rdy : 1;
18142 uint64_t c2qlut_rdy : 1;
18143 uint64_t reserved_24_62 : 39;
18144 uint64_t pko_rdy : 1;
18145 #endif
18146 } s;
18147 struct cvmx_pko_status_cn73xx {
18148 #ifdef __BIG_ENDIAN_BITFIELD
18149 uint64_t pko_rdy : 1;
18150 uint64_t reserved_62_24 : 39;
18151 uint64_t c2qlut_rdy : 1;
18152 uint64_t ppfi_rdy : 1;
18153 uint64_t iobp1_rdy : 1;
18154 uint64_t ncb_rdy : 1;
18155 uint64_t pse_rdy : 1;
18156 uint64_t pdm_rdy : 1;
18157 uint64_t peb_rdy : 1;
18158 uint64_t csi_rdy : 1;
18159 uint64_t reserved_15_5 : 11;
18160 uint64_t ncb_bist_status : 1;
18161 uint64_t c2qlut_bist_status : 1;
18162 uint64_t pdm_bist_status : 1;
18163 uint64_t peb_bist_status : 1;
18164 uint64_t pse_bist_status : 1;
18165 #else
18166 uint64_t pse_bist_status : 1;
18167 uint64_t peb_bist_status : 1;
18168 uint64_t pdm_bist_status : 1;
18169 uint64_t c2qlut_bist_status : 1;
18170 uint64_t ncb_bist_status : 1;
18171 uint64_t reserved_15_5 : 11;
18172 uint64_t csi_rdy : 1;
18173 uint64_t peb_rdy : 1;
18174 uint64_t pdm_rdy : 1;
18175 uint64_t pse_rdy : 1;
18176 uint64_t ncb_rdy : 1;
18177 uint64_t iobp1_rdy : 1;
18178 uint64_t ppfi_rdy : 1;
18179 uint64_t c2qlut_rdy : 1;
18180 uint64_t reserved_62_24 : 39;
18181 uint64_t pko_rdy : 1;
18182 #endif
18183 } cn73xx;
18184 struct cvmx_pko_status_cn73xx cn78xx;
18185 struct cvmx_pko_status_cn73xx cn78xxp1;
18186 struct cvmx_pko_status_cn73xx cnf75xx;
18187 };
18188 typedef union cvmx_pko_status cvmx_pko_status_t;
18189
18190
18191
18192
18193 union cvmx_pko_txfx_pkt_cnt_rd {
18194 uint64_t u64;
18195 struct cvmx_pko_txfx_pkt_cnt_rd_s {
18196 #ifdef __BIG_ENDIAN_BITFIELD
18197 uint64_t reserved_8_63 : 56;
18198 uint64_t cnt : 8;
18199 #else
18200 uint64_t cnt : 8;
18201 uint64_t reserved_8_63 : 56;
18202 #endif
18203 } s;
18204 struct cvmx_pko_txfx_pkt_cnt_rd_s cn73xx;
18205 struct cvmx_pko_txfx_pkt_cnt_rd_s cn78xx;
18206 struct cvmx_pko_txfx_pkt_cnt_rd_s cn78xxp1;
18207 struct cvmx_pko_txfx_pkt_cnt_rd_s cnf75xx;
18208 };
18209 typedef union cvmx_pko_txfx_pkt_cnt_rd cvmx_pko_txfx_pkt_cnt_rd_t;
18210
18211 #endif